STL25N15F3
N-channel 150 V, 0.045 Ω, 6 A PowerFLAT™ (6x5)
STripFET™ III Power MOSFET
Features
Type
VDSS
RDS(on)
max
ID
STL25N15F3
150 V
< 0.057 Ω
6 A (1)
)
s
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ct
1. The value is rated according Rthj-pcb
■
Improved die-to-footprint ratio
■
Very low profile package (1mm max)
■
Very low thermal resistance
■
Low on-resistance
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PowerFLAT™(6x5)
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Application
■
Switching application
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Description
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Figure 1.
Internal schematic diagram
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This product utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology
which is suitable for the most demanding DC-DC
converter applications where high efficiency is
required.
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Table 1.
Device summary
Order code
Marking
Package
Packaging
STL25N15F3
L25N15F3
PowerFLAT™ (6x5)
Tape and reel
March 2009
Rev 1
1/12
www.st.com
12
Contents
STL25N15F3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Electrical characteristics (curves)
............................. 7
3
Test circuit
................................................ 9
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STL25N15F3
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
150
V
VGS
Gate-source voltage
± 20
V
ID(1)
Drain current (continuous) at TC = 25 °C
25
A
ID (2)
A
ID
Drain current (continuous) at TC = 25 °C
6
(2)
Drain current (continuous) at TC = 100 °C
3.75
(3)
Drain current (pulsed)
IDM
Total dissipation at TC = 25 °C
PTOT (2)
Total dissipation at TC = 25 °C
TJ
Operating junction temperature
Storage temperature
PTOT
Tstg
ro
-55 to 150
°C
Value
Unit
Thermal resistance junction-case (Drain)
(steady state)
1.56
°C/W
Thermal resistance junction-pcb
31.3
°C/W
Value
Unit
)
(s
Thermal resistance
Symbol
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Parameter
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W
W
3. Pulse width limited by safe operating area
Rthj-pcb(1)
A
4
2. The value is rated according Rthj-pcb
Rthj-case
ct
du
80
1. The value is rated according Rthj-c
Table 3.
A
24
(1)
(s)
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
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Table 4.
O
bs
Symbol
Avalanche data
Parameter
IAS
Avalanche current repetitive or not repetitive,
(pulse width limited by Tj Max)
2.5
A
EAS
Single pulse avalanche energy
(starting Tj=25 °C, ID=IAS, VDD=50 V)
300
mJ
3/12
Electrical characteristics
2
STL25N15F3
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5.
On/off states
Symbol
Parameter
Drain-source breakdown
voltage
ID = 1 mA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating @125 °C
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 3 A
V(BR)DSS
Table 6.
Parameter
Test conditions
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Min.
Typ.
Max.
150
V
1
10
µA
µA
±100
nA
)
s
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ct
du
4
V
0.045
0.057
Ω
Typ.
Max.
2
o
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P
Min.
Unit
Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz,
VGS=0
1300
140
20.5
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD=15 V, ID = 6 A
VGS =10 V
Figure 14
29
3.6
14.6
nC
nC
nC
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
3.7
Ω
)
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Dynamic
Symbol
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Test conditions
RG
Gate input resistance
STL25N15F3
Electrical characteristics
Table 7.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 8.
ISDM(1)
VSD
(2)
trr
Qrr
IRRM
Min.
Typ.
Max.
9
13
46
20
VDD=15 V, ID= 3 A,
RG= 4.7 Ω, VGS=10 V
Figure 13
Unit
ns
ns
ns
ns
Source drain diode
Symbol
ISD
Test conditions
Parameter
Test conditions
Min
Typ.
Source-drain current
Max
ct
Forward on voltage
ISD=6 A, VGS=0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 6 A,
di/dt = 100 A/µs,
VDD=120 V, Tj=150 °C
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
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1. Pulse width limited by safe operating area
)
(s
(s)
6
Source-drain current (pulsed)
110
497
9.1
Unit
A
24
A
1.3
V
ns
nC
A
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Electrical characteristics
STL25N15F3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
AM03313v1
ID
(A)
100
10
Thermal impedance
ea
ar
Tj=150°C
Tc=25°C
is
n)
Sinlge
pulse
o
is DS(
th
in ax R
n
io y m
at
er d b
Op mite
Li
10ms
1
)
s
(
ct
100ms
0.1
1s
0.01
0.1
Figure 4.
100
10
1
u
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VDS(V)
Output characteristics
Figure 5.
Transfer characteristics
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Figure 6.
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Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
STL25N15F3
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
Figure 10. Normalized gate threshold voltage
vs temperature
Gate charge vs gate-source voltage
)
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u
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Figure 11. Normalized on resistance vs
temperature
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Figure 12. Source-drain diode forward
characteristics
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7/12
Test circuit
3
STL25N15F3
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
IG=CONST
VDD
VGS
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
)
s
(
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VG
2.7kΩ
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PW
47kΩ
1kΩ
PW
D.U.T.
AM01468v1
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AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
A
D
G
S
s
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t
c
3.3
µF
B
25 Ω
D
1000
µF
RG
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2200
µF
3.3
µF
VDD
ID
Vi
D.U.T.
Pw
let
AM01470v1
Figure 17. Unclamped inductive waveform
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VD
VDD
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G
so
)-
L=100µH
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AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/12
0
10%
AM01473v1
STL25N15F3
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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Package mechanical data
STL25N15F3
PowerFLAT™ (6x5) MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
0.80
0.83
0.93
0.031
0.032
0.036
A1
0.02
0.05
0.0007
0.0019
A3
0.20
A
b
0.35
0.40
0.007
0.47
0.196
D1
4.75
0.187
4.15
4.20
E
4.25
E1
3.53
E4
2.58
2.63
2.68
bs
0.80
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0.90
0.135
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1.27
0.70
0.167
0.226
3.48
O
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10/12
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5.75
3.43
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0.165
0.018
0.236
E2
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0.163
6.00
)
s
(
ct
0.015
5.00
D2
t
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0.013
D
0.027
0.137
0.139
0.103
0.105
0.050
0.031
0.035
STL25N15F3
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
03-Mar-2009
1
Changes
Initial release
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STL25N15F3
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Please Read Carefully:
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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