STL25N60M2-EP

STL25N60M2-EP Datasheet N-channel 600 V, 0.184 Ω typ., 16 A MDmesh™ M2 EP Power MOSFET in a PowerFLAT™ 8x8 HV package Features 5 4 3 2 1 PowerFLAT™ 8x8 HV Drain(5) Order code VDS @ TJmax RDS(on ) max. ID STL25N60M2-EP 650 V 0.205 Ω 16 A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • • Very low turn-off switching losses 100% avalanche tested Zener-protected Applications • • Gate(1) Switching applications Tailored for Very High Frequency Converters (f > 150 kHz) Description Driver source (2) Power source (3, 4) NG1DS2PS34D5Z This device is an N-channel Power MOSFET developed using MDmesh™ M2 EP enhanced performance technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance, optimized switching characteristics with very low turn-off switching losses, rendering it suitable for the most demanding very high frequency converters. Product status STL25N60M2-EP Device summary Order code STL25N60M2-EP Marking 25N60M2EP Package PowerFLAT™ 8x8 HV Packing Tape and reel DS10759 - Rev 5 - March 2018 For further information contact your local STMicroelectronics sales office. www.st.com STL25N60M2-EP Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ±25 V ID Drain current (continuous) at TC = 25 °C 16 A ID Drain current (continuous) at TC = 100 °C 10 A IDM (1) Drain current (pulsed) 64 A PTOT Total dissipation at TC = 25 °C 125 W dv/dt(2) Peak diode recovery voltage slope 15 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range - 55 to 150 °C VGS Tj Operating junction temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 16 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. 3. VDS ≤ 480 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case 1 °C/W Thermal resistance junction-pcb 45 °C/W 1. When mounted on FR-4 board of inch², 2oz Cu. Table 3. Avalanche characteristics Symbol DS10759 - Rev 5 Parameter Value Unit IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 3.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 180 mJ page 2/16 STL25N60M2-EP Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V, TC = 125 °C (1) 100 µA ±10 µA 4 4.75 V 0.184 0.205 Ω IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 8 A 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Ciss Parameter Test conditions Min. Typ. Max. Unit - 1090 - pF - 56 - pF Input capacitance VDS= 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance - 1.6 - pF Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 255 - pF - 7 - Ω - 29 - nC - 6 - nC - 12 - nC Coss eq. (1) RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge f = 1 MHz, ID = 0 A VDD = 480 V, ID = 18 A, VGS = 0 to 10 V (see Figure 15. Gate charge test circuit ) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching Energy Symbol E(off) DS10759 - Rev 5 Parameter Turn-off energy (from 90% VGS to 0% ID) Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 2 A, RG = 4.7 Ω, VGS = 10 V - 7 - µJ VDD = 400 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V - 8 - µJ page 3/16 STL25N60M2-EP Electrical characteristics Table 7. Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 9 A RG = 4.7 Ω, VGS = 10 V (see Figure 14. Switching times test circuit for resistive load and Figure 19. Switching time waveform) - 15 - ns - 10 - ns - 61 - ns - 16 - ns Min. Typ. Max. Unit Table 8. Source drain diode Symbol ISD Parameter Test conditions Source-drain current - 16 A ISDM Source-drain current (pulsed) - 64 A VSD (2) Forward on voltage VGS = 0 V, ISD = 16 A - 1.6 V trr Reverse recovery time - 360 ns Qrr Reverse recovery charge - 5 µC IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 28 A ISD = 18 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16. Test circuit for inductive load switching and diode recovery times ) - 445 ns - 6.5 µC - 29 A (1) trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1. Pulse width is limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS10759 - Rev 5 page 4/16 STL25N60M2-EP Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG220320181638SOA Zth PowerFLAT 8x8 HV K δ=0.5 0.2 10 1 tp = 10µs tp = 100µs 0.1 -1 10 0.05 0.02 10 0 tp = 1ms Operation in this area is limited by RDS(on) 10 -1 10 -1 10 10 0 10 1 Single pulse tp = 10ms Tj ≤ 150 °C,Tc = 25 °C VGS = 10 V, single pulse tp -2 VDS (V) 2 10 -5 10 Figure 3. Output characteristics ID (A) 10 Ƭ -2 -3 10 10 ID (A) VGS = 8, 9, 10 V 40 VGS =7 V 32 tp (s) GIPG090220181022TCH VDS =16 V 32 24 24 VGS =6 V 16 16 8 8 VGS =5 V 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) VDD = 480 V, ID = 18 A VDS 0 3 RDS(on) (Ω) 600 0.196 500 4 5 6 7 VGS (V) Figure 6. Static drain-source on-resistance (V) GADG260320181223QVG VDS 12 10 -4 Figure 4. Transfer characteristics GIPG090220181022OCH 40 Zth= K*R thJ-c δ= t p/Ƭ 0.01 GIPG210220181129RID VGS =10 V 0.192 8 400 6 300 4 200 2 100 0.18 0 Qg (nC) 0.176 0 0.188 0 0 DS10759 - Rev 5 5 10 15 20 25 30 0.184 4 8 12 16 ID (A) page 5/16 STL25N60M2-EP Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) GIPG090220181022CVR Ciss 10 3 GIPG090220181024EOS 8 6 10 2 Coss 10 1 f = 1 MHz 2 Crss 10 0 10 -1 10 0 10 1 VDS (V) 10 2 Figure 9. Turn-off switching energy vs drain current Eoff (µJ) GADG260320181227TSL 12 0 0 8 0.9 6 0.8 4 1 2 3 RDS(on) (norm.) 4 5 6 ID (A) GIPG090220181019RON VGS = 10 V 0.6 -75 500 600 VDS (V) ID = 250 µA 1.00 1.0 0.95 0.5 0.90 75 125 Tj (°C) 75 125 Tj (°C) GIPG090220181020BDV ID = 1 mA 1.10 1.5 25 25 V(BR)DSS (norm.) 1.05 -25 -25 Figure 12. Normalized V(BR)DSS vs temperature 2.0 DS10759 - Rev 5 400 0.7 Figure 11. Normalized on-resistance vs temperature 0.0 -75 300 GIPG090220181018VTH 1.1 1.0 2.5 200 Figure 10. Normalized gate threshold voltage vs temperature 10 2 0 100 VGS(th) (norm.) VDD = 400 V RG = 4.7Ω VGS = 10V 14 4 0.85 -75 -25 25 75 125 Tj (°C) page 6/16 STL25N60M2-EP Electrical characteristics (curves) Figure 13. Source-drain diode forward characteristics VSD (V) GIPG210220181132SDF 1.1 Tj = -50 °C 1.0 0.9 Tj = 25 °C 0.8 Tj = 150 °C 0.7 0.6 0.5 0 DS10759 - Rev 5 4 8 12 16 ISD (A) page 7/16 STL25N60M2-EP Test circuits 3 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12 V RL + VD VGS 3.3 µF 2200 µF 1 kΩ 100 nF VDD IG= CONST VGS RG 47 kΩ D.U.T. + pulse width 2.7 kΩ 2200 μF PW D.U.T. 100 Ω VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ AM15855v1 GND1 GND2 AM01469v2 Figure 16. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 17. Unclamped inductive load test circuit L A D G S 3.3 µF B B B VD L=100µH D 25Ω + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG Vi D.U.T. D.U.T. Pw GND1 GND2 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform V(BR)DSS ton VD td(on) IDM toff td(off) tr 90% tf 90% 10% ID VDD 10% 0 VDD VGS 0 VDS 90% 10% AM01472v1 AM01473v1 DS10759 - Rev 5 page 8/16 STL25N60M2-EP Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS10759 - Rev 5 page 9/16 STL25N60M2-EP PowerFLAT™ 8x8 HV package information 4.1 PowerFLAT™ 8x8 HV package information Figure 20. PowerFLAT™ 8x8 HV package outline 8222871_Rev_4 DS10759 - Rev 5 page 10/16 STL25N60M2-EP PowerFLAT™ 8x8 HV package information Table 9. PowerFLAT™ 8x8 HV mechanical data Dim. mm Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 21. PowerFLAT™ 8x8 HV footprint 8222871_REV_4_footprint Note: DS10759 - Rev 5 All dimensions are in millimeters. page 11/16 STL25N60M2-EP PowerFLAT™ 8x8 HV packing information 5 PowerFLAT™ 8x8 HV packing information Figure 22. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 23. PowerFLAT™ 8x8 HV package orientation in carrier tape DS10759 - Rev 5 page 12/16 STL25N60M2-EP PowerFLAT™ 8x8 HV packing information Figure 24. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA Note: DS10759 - Rev 5 All dimensions are in millimeters. page 13/16 STL25N60M2-EP Revision history Table 10. Document revision history Date Revision Changes 02-Dec-2014 1 First release. 12-Jan-2015 2 Updated product status from “preliminary data” to “production data”. Updated: cover image and Figure 1: "Internal schematic diagram" 20-Nov-2015 3 Updated: Section 3: "Test circuits" Modified: Section 4.1: "PowerFLAT 8x8 HV package information" Minor text changes Removed maturity status indication from cover page. The document status is production data. 21-Feb-2018 4 Modified Table 1. Absolute maximum ratings, Table 4. On/off states, Table 5. Dynamic, Table 6. Switching Energy, Table 7. Switching times and Table 8. Source drain diode. Modified the entire Section 2.1 Electrical characteristics (curves). Minor text changes. 26-Mar-2018 5 Modified Table 1. Absolute maximum ratings, Table 4. On/off states, Table 5. Dynamic, Table 6. Switching Energy, Table 7. Switching times, Table 8. Source drain diode and Section 2.1 Electrical characteristics (curves). Minor text changes. DS10759 - Rev 5 page 14/16 STL25N60M2-EP Contents Contents 1 Electrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 5 PowerFLAT™ 8x8 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS10759 - Rev 5 page 15/16 STL25N60M2-EP IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS10759 - Rev 5 page 16/16