STL26N65DM2

STL26N65DM2 Datasheet N-channel 650 V, 0.182 Ω typ., 20 A, MDmesh™ DM2 Power MOSFET in a PowerFLAT™ 8x8 HV package Features 5 4 3 2 • • • • • • 1 PowerFLAT™ 8x8 HV Drain(5) Order code VDS RDS(on) max. ID PTOT STL26N65DM2 650 V 0.206 Ω 20 A 140 W Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications • Gate(1) Switching applications Description Driver source (2) Power source (3, 4) NG1DS2PS34D5Z This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fastrecovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status link STL26N65DM2 Product summary Order code STL26N65DM2 Marking 26N65DM2 Package PowerFLAT™ 8x8 HV Packing Tape and reel DS12623 - Rev 1 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com STL26N65DM2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS ID Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 20 Drain current (continuous) at Tcase = 100 °C 12.6 A IDM(1) Drain current (pulsed) 53 A PTOT Total dissipation at Tcase = 25 °C 140 W dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 20 A, di/dt=900 A/μs, VDD = 400 V, VDS(peak) < V(BR)DSS 3. VDS ≤ 520 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case 0.89 Thermal resistance junction-pcb 45 °C/W 1. When mounted on an 1-inch² FR-4, 2oz Cu board Table 3. Avalanche characteristics Symbol IAR(1) (2) EAS Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 3 A 530 mJ 1. Pulse width limited by Tjmax 2. Starting Tj = 25 °C, ID = IAR, VDD = 50 V DS12623 - Rev 1 page 2/15 STL26N65DM2 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4. Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 IDSS Zero gate voltage drain current VGS = 0 V, VDS = 650 V, Tcase = 125 °C(1) 100 IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A 0.182 0.206 Ω Min. Typ. Max. Unit - 1480 - - 62 - - 2 - 3 µA 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 140 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4.6 - Ω Qg Total gate charge VDD = 520 V, ID = 20 A, - 35.5 - Qgs Gate-source charge VGS = 0 to 10 V - 8.2 - Gate-drain charge (see Figure 14. Gate charge test circuit) - 17.6 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12623 - Rev 1 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 325 V, ID = 10 A, - 17 - Rise time RG = 4.7 Ω, VGS = 10 V - 7 - Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 51 - - 10 - Fall time Unit ns page 3/15 STL26N65DM2 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 20 A Source-drain current (pulsed) - 53 A 1.6 V Forward on voltage VGS = 0 V, ISD = 20 A - trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 100 ns Qrr Reverse recovery charge VDD = 100 V - 0.365 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 7.3 A trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 200 ns Qrr Reverse recovery charge VDD = 100 V, Tj = 150 °C - 1.39 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 13.9 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 8. Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS12623 - Rev 1 page 4/15 STL26N65DM2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG120620181205SOA K PowerFLAT8x8HVzth δ =0.5 10 2 Operation in this area is limited by RDS(on) δ =0.2 δ =0.1 tp = 1 μs 10 1 tp =10 µs 10 -1 δ =0.05 10 0 Z th =K*R thj-c δ=t p / Ƭ δ =0.02 tp =100 µs δ =0.01 Single pulse, TC = 25 °C, TJ ≤ 150 °C tp =1 ms tp Single pulse Ƭ tp =10 ms 10 -1 10 -1 10 0 10 1 10 2 10 3 VDS (V) 10 -2 10 -5 Figure 3. Output characteristics ID (A) 50 ID (A) VGS = 8, 9, 10 V VGS = 7 V VDS = 20 V 40 30 VGS = 6 V 20 10 20 10 VGS = 5 V 0 0 5 10 15 20 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG201220170958QVG VDS (V) VDD = 520 V ID = 20 A 0 3 10 500 0.190 8 400 0.186 6 300 0.182 4 200 0.178 2 100 0.174 0 Qg (nC) 0.170 0 6 12 18 24 30 36 5 6 RDS(on) (Ω) 0.194 VDS 4 7 8 VGS (V) Figure 6. Static drain-source on-resistance 600 DS12623 - Rev 1 t p (s) 10 -2 GIPG201220170957TCH 50 30 0 0 10 -3 Figure 4. Transfer characteristics GIPG201220170957OCH 40 12 10 -4 GADG030720181100RID VGS = 10 V 4 8 12 16 20 ID (A) page 5/15 STL26N65DM2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG201220170957CVR VGS(th) (norm.) 10 4 GIPG201220170954VTH ID = 250 µA 1.1 CISS 10 3 1.0 0.9 10 2 COSS 10 1 f = 1 MHz CRSS 10 10 -1 0 10 0 10 1 VDS (V) 10 2 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG201220170954RON VGS = 10 V 2.2 0.8 0.7 0.6 -75 1.00 1.0 0.96 0.6 0.92 75 125 Tj (°C) Figure 11. Output capacitance stored energy EOSS (µJ) GIPG201220170958EOS 0.88 -75 10 1.0 8 0.9 6 0.8 4 0.7 2 0.6 DS12623 - Rev 1 200 300 ID = 1 mA 400 500 600 VDS (V) -25 25 75 VSD (V) 1.1 100 Tj (°C) 125 Tj (°C) Figure 12. Source-drain diode forward characteristics 12 0 0 125 GIPG201220170955BDV 1.08 1.4 25 75 V(BR)DSS (norm.) 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 0.5 0 GIPG201220170956SDF Tj = -50 °C Tj = 25 °C Tj = 150 °C 4 8 12 16 20 ISD (A) page 6/15 STL26N65DM2 Test circuits 3 Test circuits Figure 14. Gate charge test circuit Figure 13. Switching times test circuit for resistive load VDD 12 V RL + VD VGS µF VDD IG= CONST VGS RG 1 kΩ 100 nF 3.3 µF 2200 47 kΩ + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 AM01469v2 Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 16. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12623 - Rev 1 page 7/15 STL26N65DM2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12623 - Rev 1 page 8/15 STL26N65DM2 PowerFLAT™ 8x8 HV package information 4.1 PowerFLAT™ 8x8 HV package information Figure 19. PowerFLAT™ 8x8 HV package outline 8222871_Rev_4 DS12623 - Rev 1 page 9/15 STL26N65DM2 PowerFLAT™ 8x8 HV package information Table 9. PowerFLAT™ 8x8 HV mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 20. PowerFLAT™ 8x8 HV footprint 8222871_REV_4_footprint Note: DS12623 - Rev 1 All dimensions are in millimeters. page 10/15 STL26N65DM2 PowerFLAT™ 8x8 HV packing information 4.2 PowerFLAT™ 8x8 HV packing information Figure 21. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape DS12623 - Rev 1 page 11/15 STL26N65DM2 PowerFLAT™ 8x8 HV packing information Figure 23. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA Note: DS12623 - Rev 1 All dimensions are in millimeters. page 12/15 STL26N65DM2 Revision history Table 10. Document revision history DS12623 - Rev 1 Date Version 03-Jul-2018 1 Changes Initial release. page 13/15 STL26N65DM2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT™ 8x8 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12623 - Rev 1 page 14/15 STL26N65DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12623 - Rev 1 page 15/15