STL2N80K5

STL2N80K5 N-channel 800 V, 3.7 Ω typ., 1.5 A MDmesh™ K5 Power MOSFET in a PowerFLAT™ 5x6 VHV package Datasheet - production data Features Order code VDS RDS(on)max. ID STL2N80K5 800 V 4.5 Ω 1.5 A • Industry’s lowest RDS(on) • Industry’s best figure of merit (FoM) 1 2 3 • Ultra low gate charge 4 • 100% avalanche tested PowerFLAT™ 5x6 VHV • Zener-protected Applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 7 • Switching applications 5 6 Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in onresistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(4) 1 S(1, 2, 3) 2 3 4 Top View AM15540v1 Table 1. Device summary Order code Marking Packages Packaging STL2N80K5 2N80K5 PowerFLAT™ 5x6 VHV Tape and reel September 2015 This is information on a product in full production. DocID025104 Rev 3 1/17 www.st.com Contents STL2N80K5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 .............................................. 9 DocID025104 Rev 3 STL2N80K5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ± 30 V ID (1) Drain current (continuous) at TC = 25 °C 1.5 A ID (1) Drain current (continuous) at TC = 100 °C 1 A 6 A Total dissipation at TC = 25 °C 33 W IAR(3) Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 0.5 A EAS(4) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 60.5 mJ Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns VGS IDM (1),(2) Drain current (pulsed) PTOT(1) dv/dt (5) dv/dt (6) Tstg Tj Storage temperature °C - 55 to 150 Max. operating junction temperature °C 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. Pulse width limited by Tjmax 4. Starting Tj=25 °C, ID=IAR, VDD=50 V 5. ISD ≤ 1.5 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS 6. VDS ≤ 640 V Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 3.7 °C/W Rthj-amb(1) Thermal resistance junction-amb max 59 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DocID025104 Rev 3 3/17 17 Electrical characteristics 2 STL2N80K5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 800 V VGS = 0, VDS = 800 V 1 µA VDS = 800 V, TC=125 °C 50 µA ± 10 µA 4 5 V 3.7 4.5 Ω Min. Typ. Max. Unit - 105 - pF - 8 - pF - 0.5 - pF - 16 - pF - 7 - pF f = 1 MHz, ID=0 - 18 - Ω VDD = 640 V, ID = 2 A, VGS = 10 V (see Figure 16) - 5 - nC - 1 - nC - 3.7 - nC VDS = 0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on- resistance 3 VGS = 10 V, ID = 1 A Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VGS = 0, VDS = 100 V, f = 1 MHz VGS = 0, VDS = 0 to 640 V 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/17 DocID025104 Rev 3 STL2N80K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 400 V, ID = 1 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15), (see Figure 20) Rise time Turn-off delay time Fall time Min. Typ. Max Unit - 8 - ns - 12 - ns - 19 - ns - 32 - ns Min. Typ. Table 7. Source drain diode Symbol ISD ISDM VSD(1) trr Parameter Test conditions Max. Unit Source-drain current - 1.5 A Source-drain current (pulsed) - 6 A - 1.5 V VGS = 0, ISD = 2 A Forward on voltage Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 2 A, di/dt = 100 A/µs VDD = 60 V (see Figure 17) ISD = 2 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17) - 255 ns - 1 µC - 8 A - 285 ns - 1.45 µC - 7.5 A Min Typ. Max Unit 30 - - V 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID=0 The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID025104 Rev 3 5/17 17 Electrical characteristics 2.1 STL2N80K5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance *,3*6$ ,' $ K ZthPowerFlat_5x6_27 δ=0.5 0.2 2 SH P UDWL LWH RQ G LQ E\ W P KLV D[ DU 5 HD ' LV —$ 6 RQ   0.1 10 -1 —$ 0.05 0.02 /L P$ P$  0.01 case 10 -2 Single pulse 7M ƒ& 7F ƒ& 6LQJOHSXOVH      10 -3 10 -5 9'69 Figure 4. Output characteristics 10 0 10 -2 10 -1 10 1 tp(s) Figure 5. Transfer characteristics AM18075v1 ID (A) 10 -4 10 -3 VGS=10, 11V AM18085v1 ID (A) VDS=20V 3.0 3 2.5 9V 2.5 2.0 2 1.5 1.5 8V 1.0 1 0.5 7V 0.5 6V 0.0 0 4 2 6 8 10 Figure 6. Gate charge vs gate-source voltage AM18076v1 VDS VGS (V) 14 12 600 10 500 8 400 6 300 4 200 2 100 0 0 6/17 (V) 700 VDD = 640 V ID = 2 A VDS 1 2 3 4 0 5 12 14 16 VDS(V) 5 6 6 7 8 9 10 VGS(V) Figure 7. Static drain-source on-resistance AM18077v1 RDS(on) (Ω) 0 Qg(nC) DocID025104 Rev 3 VGS=10V 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 ID(A) STL2N80K5 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM18078v1 C (pF) AM18079v1 Eoss (μJ) f = 1MHz 100 100 Ciss 2 10 Coss Crss 1 0.1 0.1 1 100 10 0 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature 0 400 200 600 800 Figure 11. Normalized on-resistance vs temperature AM18082v1 VGS(th) VDS(V) AM18081v1 RDS(on) (norm) (norm) ID=100 μA 1.2 ID=1 A VGS=10 V 2.5 1.1 1 2 0.9 0.8 1.5 0.7 1 0.6 0.5 0.5 0.4 -100 -50 0 50 100 0 -100 150 TJ(°C) Figure 12. Normalized V(BR)DSS vs temperature 0 100 50 150 TJ(°C) Figure 13. Source-drain diode forward characteristics AM18083v1 V(BR)DSS AM18084v1 VSD(V) (norm) TJ=-50°C ID=1mA 1.1 1 1.05 0.9 1 0.8 0.95 0.7 0.9 0.6 0.85 -100 -50 TJ=25°C TJ=150°C 0.5 -50 0 50 100 TJ(°C) DocID025104 Rev 3 0 0.5 1 1.5 2 ISD(A) 7/17 17 Electrical characteristics STL2N80K5 Figure 14. Maximum avalanche energy vs starting TJ *,3*6$ ($6 P-         8/17        7-ƒ& DocID025104 Rev 3 STL2N80K5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID025104 Rev 3 10% AM01473v1 9/17 17 Package mechanical data 4 STL2N80K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/17 DocID025104 Rev 3 STL2N80K5 Package mechanical data Figure 21. PowerFLAT™ 5x6 VHV Bottom view Side view Top view 8368144_REV_B DocID025104 Rev 3 11/17 17 Package mechanical data STL2N80K5 Table 9. PowerFLAT™ 5x6 VHV mechanical data mm. DIM min. max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 2.40 2.50 2.60 e 12/17 typ. 0.50 1.27 L 0.50 0.55 0.60 K 2.60 2.70 2.80 aaa 0.15 bbb 0.15 ccc 0.10 eee 0.10 DocID025104 Rev 3 STL2N80K5 Package mechanical data Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm) 8368144_REV_B_footprint DocID025104 Rev 3 13/17 17 Packaging mechanical data 5 STL2N80K5 Packaging mechanical data Figure 23. PowerFLAT™ 5x6 tape P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape. Pin 1 identification 14/17 DocID025104 Rev 3 STL2N80K5 Packaging mechanical data Figure 25. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C DocID025104 Rev 3 15/17 17 Revision history 6 STL2N80K5 Revision history Table 10. Document revision history 16/17 Date Revision Changes 09-Aug-2013 1 First release. 24-Jul-2014 2 – – – – – – – – 25-Sep-2015 3 – Updated title in cover page. – Updated Figure 6, Figure 7 and Figure 8. – Minor text changes. Modified: title Modified: Features table Modified: ID, IDM, PTOT, IAR, EAS values and note 5 in Table 2 Modified: Rthj-case value in Table 3 Modified: RDS(on) values in Table 4 Modified: the entire typical values in Table 5, 6 and 7 Added: Section 2.1: Electrical characteristics (curves) Minor text changes. DocID025104 Rev 3 STL2N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025104 Rev 3 17/17 17