STL33N60DM2

STL33N60DM2 N-channel 600 V, 0.115 Ω typ., 21 A MDmesh™ DM2 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2   1     PowerFLAT™ 8x8 HV Order code VDS @ TJmax RDS(on)max ID STL33N60DM2 650 V 0.140 Ω 21 A Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Figure 1: Internal schematic diagram Applications  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packaging STL33N60DM2 33N60DM2 PowerFLAT™ 8x8 HV Tape and reel March 2016 DocID026781 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STL33N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 5 2/15 4.1 PowerFLAT™ 8x8 HV package mechanical data ........................... 10 4.2 PowerFLAT™ 8x8 HV packing information ..................................... 12 Revision history ............................................................................ 14 DocID026781 Rev 2 STL33N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Unit ± 25 V ID (1) Drain current (continuous) at TC = 25 °C 21 A ID (1) Drain current (continuous) at TC = 100 °C 15 A , Drain current (pulsed) 84 A (1) Total dissipation at TC = 25 °C 150 W IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 4.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 570 mJ IDM Gate-source voltage Value (1) (2) PTOT dv/dt (3) Peak diode recovery voltage slope 50 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Tstg Storage temperature range Tj Operating junction temperature range Notes: (1) (2) The value is rated according to Rthj-case and limited by package. Pulse width limited by safe operating area. (3) ISD ≤ 21 A, di/dt ≤ 900 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V. (4) VDS ≤ 480 V. Table 3: Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max Value Unit 0.83 °C/W 45 °C/W Notes: (1) When mounted on FR-4 board of inch², 2oz Cu. DocID026781 Rev 2 3/15 Electrical characteristics 2 STL33N60DM2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 600 V 1 µA VGS = 0, (1) VDS = 600 V, TC=125 °C 100 µA Gate-body leakage current VDS = 0, VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 10.5 A 0.115 0.140 Ω Min. Typ. Max. Unit - 1870 - pF - 87 - pF - 2 - pF IDSS Zero gate voltage drain current IGSS VGS = 0, VDS = 600 V 3 Notes: (1) Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 - 157 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 4.5 - Ω Qg Total gate charge - 43 - nC Qgs Gate-source charge - 9.8 - nC Qgd Gate-drain charge VDD = 480 V, ID = 21 A VGS = 10 V (see Figure 15: "Gate charge test circuit") - 21.4 - nC Coss eq. (1) Notes: (1) 4/15 Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. DocID026781 Rev 2 STL33N60DM2 Electrical characteristics Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time Min. Typ. Max. Unit - 17 - ns - 8 - ns - 62 - ns - 9 - ns VDD = 300 V, ID = 10.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load") Rise time Turn-off delay time Fall time Table 7: Source drain diode Symbol ISD ISDM Parameter (1) Source-drain current (1)(2) Source-drain current (pulsed) (3) VSD trr Test conditions Forward on voltage ISD = 21 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 21 A, di/dt = 100 A/µs VDD = 100 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 21 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Min. Typ. Max. Unit - 21 A - 84 A - 1.6 V - 120 ns - 0.53 µC - 8.8 A - 316 ns - 2.85 µC - 18 A Notes: (1) (2) (3) The value is rated according to Rthj-case and limited by package. Pulse width limited by safe operating area Pulsed: pulse duration = 300 μs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±250 µA, ID = 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID026781 Rev 2 5/15 Electrical characteristics 2.2 STL33N60DM2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 6/15 10 -4 10 -3 10 -2 Ƭ tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID026781 Rev 2 STL33N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source- drain diode forward characteristics DocID026781 Rev 2 7/15 Test circuits 3 STL33N60DM2 Test circuits Figure 15: Gate charge test circuit Figure 14: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G L S L=100µH 3.3 µF B 25Ω D VD + 1000 µF 3.3 µF VDD + ID G RG 2200 µF VDD S D.U.T. Vi GND1 GND2 D.U.T. Pw GND1 Figure 18: Unclamped inductive waveform 8/15 DocID026781 Rev 2 GND2 AM15858v1 Figure 19: Switching time waveform STL33N60DM2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID026781 Rev 2 9/15 Package mechanical data 4.1 STL33N60DM2 PowerFLAT™ 8x8 HV package mechanical data Figure 20: PowerFLAT™ 8x8 HV package outline 8222871_Rev_3_ A 10/15 DocID026781 Rev 2 STL33N60DM2 Package mechanical data Table 9: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 0.60 Figure 21: PowerFLAT™ 8x8 HV footprint All dimensions are in millimeters. DocID026781 Rev 2 11/15 Package mechanical data 4.2 STL33N60DM2 PowerFLAT™ 8x8 HV packing information Figure 22: PowerFLAT™ 8x8 HV tape Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape 12/15 DocID026781 Rev 2 STL33N60DM2 Package mechanical data Figure 24: PowerFLAT™ 8x8 HV reel DocID026781 Rev 2 13/15 Revision history 5 STL33N60DM2 Revision history Table 10: Document revision history Date Revision 08-Aug-2014 1 First release. 2 Updated title and internal schematic in cover page. Document status promoted from preliminary data to production data. Modified: Table 2: "Absolute maximum ratings", Table 4: "On /off states", Table 5: "Dynamic", Table 6: "Switching times" and Table 7: "Source drain diode" Added: Section 4.1: "Electrical characteristics (curves)" Updated: Section 6.1: "PowerFLAT™ 8x8 HV package mechanical data" Minor text changes 09-Mar-2016 14/15 Changes DocID026781 Rev 2 STL33N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID026781 Rev 2 15/15