STL33N60DM6

STL33N60DM6 Datasheet N-channel 600 V, 125 mΩ typ., 21 A, MDmesh DM6 Power MOSFET in a PowerFLAT 8x8 HV package Features 5 4 3 2 1 PowerFLAT 8x8 HV Drain(5) Gate(1) Driver source (2) Power source (3, 4) NG1DS2PS34D5Z Order code VDS RDS(on) max. ID STL33N60DM6 600 V 140 mΩ 21 A • • Fast-recovery body diode Lower RDS(on) per area vs previous generation • • • • Low gate charge, input capacitance and resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications • Switching applications Description This high-voltage N-channel Power MOSFET is part of the MDmesh DM6 fastrecovery diode series. Compared with the previous MDmesh fast generation, DM6 combines very low recovery charge (Qrr), recovery time (trr) and excellent improvement in RDS(on) per area with one of the most effective switching behaviors available in the market for the most demanding high-efficiency bridge topologies and ZVS phase-shift converters. Product status link STL33N60DM6 Product summary Order code STL33N60DM6 Marking 33N60DM6 Package PowerFLAT 8x8 HV Packing Tape and reel DS12985 - Rev 3 - February 2021 For further information contact your local STMicroelectronics sales office. www.st.com STL33N60DM6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 21 A Drain current (continuous) at TC = 100 °C 13 A Drain current (pulsed) 80 A Total power dissipation at TC = 25 °C 150 W dv/dt(2) Peak diode recovery voltage slope 100 V/ns (2) Peak diode recovery current slope 1000 A/µs dv/dt(3) MOSFET dv/dt ruggedness 100 V/ns Tstg Storage temperature range -55 to 150 °C Value Unit Thermal resistance, junction-to-case 0.83 °C/W Thermal resistance, junction-to-board 45 °C/W Value Unit VGS ID IDM (1) PTOT di/dt Tj Parameter Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 21 A, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol RthJC RthJB (1) Parameter 1. When mounted on FR-4 board of inch², 2oz Cu. Table 3. Avalanche characteristics Symbol DS12985 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 4 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 360 mJ page 2/14 STL33N60DM6 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current 1 µA 100 µA ±5 µA 4 4.75 V 125 140 mΩ Min. Typ. Max. Unit - 1500 - pF - 115 - pF - 3 - pF VGS = 0 V, VDS = 600 V, TC = 125 °C(1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10.5 A Unit V VGS = 0 V, VDS = 600 V IDSS Max. 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 225 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 1.8 - Ω Qg Total gate charge VDD = 480 V, ID = 25 A, - 35 - nC Qgs Gate-source charge VGS = 0 to 10 V - 10 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 15 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12985 - Rev 3 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 12.5 A, - 14 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 9 - ns Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 7 - ns - 35 - ns Fall time page 3/14 STL33N60DM6 Electrical characteristics Table 7. Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 21 A ISDM Source-drain current (pulsed) - 80 A VSD(2) Forward on voltage VGS = 0 V, ISD = 21 A - 1.6 V trr Reverse recovery time ISD = 25 A, di/dt = 100 A/µs, - 105 ns Qrr Reverse recovery charge VDD = 60 V - 0.47 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 9 A Reverse recovery time ISD = 25 A, di/dt = 100 A/µs, - 210 ns Reverse recovery charge VDD = 60 V, Tj = 150 °C - 1.68 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 16 A (1) trr Qrr IRRM 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. DS12985 - Rev 3 page 4/14 STL33N60DM6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Normalized thermal impedance GADG040420190941SOA K δ =0.5 tp = 1µs 10 1 δ =0.2 δ =0.1 tp = 10µs 10 10 0 10 0 tp = 100µs tp = 10ms 10 1 tp = 1ms VDS (V) 10 2 10 -2 10 -5 10 -4 10 -3 ID (A) GADG191220180852OCH VGS = 9 V Ƭ t p (s) 10 -2 GADG191220180853TCH 70 VGS = 8 V 60 VDS = 20 V 60 50 50 40 40 VGS = 7 V 30 30 20 20 10 10 VGS = 6 V 0 0 4 8 12 16 VDS (V) 0 4 Figure 5. Gate charge vs gate-source voltage VDS (V) GADG191220180853QVG VDD = 480 V, ID = 25 A 600 8 Qgd 300 6 200 4 100 2 5 10 15 5 6 7 8 9 VGS (V) Figure 6. Capacitance variations C (pF) GADG191220180854CVR 10 4 10 VDS Qgs VGS (V) 12 Qg 500 DS12985 - Rev 3 tp Figure 4. Transfer characteristics VGS = 10 V 70 0 0 Z th =K*R thj-c δ=t p / Ƭ δ =0.01 Figure 3. Output characteristics ID (A) δ =0.05 Single pulse T j ≤150 °C T c = 25°C single pulse 10 -2 10 -1 -1 δ =0.02 Operation in this area is limited by R DS(on) 10 -1 400 PowerFLAT8x8HVzth 20 25 30 35 0 Qg (nC) CISS 10 3 10 2 10 1 10 0 10 -1 COSS f = 1 MHz CRSS 10 0 10 1 10 2 VDS (V) page 5/14 STL33N60DM6 Electrical characteristics (curves) Figure 7. Static drain-source on-resistance RDS(on) (mΩ) GADG040420190941RID VGS =10 V 133 Figure 8. Normalized on-resistance vs temperature RDS(on) (norm.) GADG191220180856RON 2.5 2.0 129 VGS = 10 V 1.5 125 1.0 121 117 0 0.5 4 8 12 16 20 ID (A) Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GADG191220180856VTH -25 25 0.9 Tj (°C) V(BR)DSS (norm.) GADG191220180856BDV ID = 1 mA 1.00 ID = 250 µA 0.95 0.8 0.90 0.7 -25 25 75 125 Tj (°C) Figure 11. Output capacitance stored energy EOSS (μJ) 14 GADG191220180857EOS 0.85 -75 -25 25 75 125 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG040420190942SDF 1.1 12 Tj = -50 °C 1 10 0.9 Tj = 25 °C 8 0.8 6 Tj = 150 °C 0.7 4 0.6 2 DS12985 - Rev 3 125 Figure 10. Normalized V(BR)DSS vs temperature 1.05 1.0 0 0 75 1.10 1.1 0.6 -75 0.0 -75 100 200 300 400 500 600 VDS (V) 0.5 0 4 8 12 16 20 ISD (A) page 6/14 STL33N60DM6 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD RL + VD VGS 3.3 µF 2200 RL µF VDD IG= CONST VGS RG + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 GADG180720181011SA Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 16. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD VGS AM01472v1 0 VDS 10% 90% 10% AM01473v1 DS12985 - Rev 3 page 7/14 STL33N60DM6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 8x8 HV type A package information Figure 19. PowerFLAT 8x8 HV type A package outline 8222871_Rev_4 DS12985 - Rev 3 page 8/14 STL33N60DM6 PowerFLAT 8x8 HV type A package information Table 8. PowerFLAT 8x8 HV type A mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 20. PowerFLAT 8x8 HV footprint 8222871_REV_4_footprint Note: DS12985 - Rev 3 All dimensions are in millimeters. page 9/14 STL33N60DM6 PowerFLAT 8x8 HV packing information 4.2 PowerFLAT 8x8 HV packing information Figure 21. PowerFLAT 8x8 HV tape P0 (4.0±0.1) P2 (2.0±0.1) D0 ( 1.55±0.05) T (0.30±0.05) B0 (8.30±0.1) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 22. PowerFLAT 8x8 HV package orientation in carrier tape Pin 1 identification ST DS12985 - Rev 3 ST ST ST page 10/14 STL33N60DM6 PowerFLAT 8x8 HV packing information Figure 23. PowerFLAT 8x8 HV reel 8229819_Reel_revA Note: DS12985 - Rev 3 All dimensions are in millimeters. page 11/14 STL33N60DM6 Revision history Table 9. Document revision history DS12985 - Rev 3 Date Version Changes 04-Apr-2019 1 First release. 28-Jul-2020 2 Updated Table 1. Absolute maximum ratings, Table 7. Source drain diode and Figure 22. PowerFLAT 8x8 HV package orientation in carrier tape. 15-Feb-2021 3 Modified Figure 22. PowerFLAT 8x8 HV package orientation in carrier tape. Minor text changes. page 12/14 STL33N60DM6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 8x8 HV type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS12985 - Rev 3 page 13/14 STL33N60DM6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12985 - Rev 3 page 14/14