STL33N60M2

STL33N60M2 Datasheet N-channel 600 V, 0.115 Ω typ., 22 A MDmesh M2 Power MOSFET in a PowerFLAT 8x8 HV package Features 5 4 3 2 1 PowerFLAT 8x8 HV Order code V DS @ T Jmax RDS(on)max ID STL33N60M2 650 V 0.135 Ω 22 A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected Drain(5) Applications • • Gate(1) Driver source (2) Switching applications LLC converters, resonant converters Description Power source (3, 4) NG1DS2PS34D5Z This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL33N60M2 Product summary Order code STL33N60M2 Marking 33N60M2 Package PowerFLAT™ 8x8 HV Packing Tape & reel DS9512 - Rev 4 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL33N60M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit ± 25 V VGS Gate-source voltage ID (1) Drain current (continuous) at TC = 25 °C 22 A ID (1) Drain current (continuous) at TC = 100 °C 13.8 A IDM (2) Drain current (pulsed) 88 A PTOT Total power dissipation at TC = 25 °C 150 W 5 A 450 mJ IAR EAS Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range - 55 to 150 °C 150 °C Value Unit Tj Operating junction temperature range 1. The value is limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 22 A, di/dt ≤ 400 A/µs, VDS( peak) < V(BR)DSS, VDD = 400 V. 4. VDS ≤ 480 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.83 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 45 °C/W 1. When mounted on FR-4 board of 1 inch², 2oz Cu. DS9512 - Rev 4 page 2/15 STL33N60M2 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On /off states Symbol V(BR)DSS IDSS IGSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Zero gate voltage VGS = 0 V, VDS = 600 V drain current Gate-body leakage current VGS = 0 V, VDS = 600 V, TC =125 °C Min. Typ. 600 Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 11 A Unit V 1 µA 100 µA ±10 µA 3 4 V 0.115 0.135 Ω Min. Typ. Max. Unit - 1781 - pF - 85 - pF - 2.5 - pF (1) VDS = 0 V, VGS = ± 25 V VGS(th) Max. 2 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Ciss Coss Parameter Test conditions Input capacitance Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 135 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 5.2 - Ω Qg Total gate charge VDD = 480 V, ID = 26 A - 45.5 - nC Qgs Gate-source charge VGS = 0 to 10 V - 9.9 - nC Qgd Gate-drain charge (see Figure 15. Gate charge test circuit) - 18.5 - nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 5. Switching times Symbol td(on) tr td(off) tf DS9512 - Rev 4 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 13 A - 16 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 9.6 - ns Turn-off delay time (see Figure 14. Switching times test circuit for resistive load and Figure 19. Switching time waveform) - 109 - ns - 9 - ns Fall time page 3/15 STL33N60M2 Electrical characteristics Table 6. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 22 A ISDM (1) Source-drain current (pulsed) - 88 A VSD (2) Forward on voltage ISD = 22 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 60 V (see Figure 16. Test circuit for inductive load switching and diode recovery times) ISD = 26 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 375 ns - 5.6 µC - 30 A - 478 ns - 7.7 µC - 32.5 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS9512 - Rev 4 page 4/15 STL33N60M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Zth PowerFLAT 8x8 HV K δ=0.5 0.2 0.1 -1 10 0.05 0.02 Zth= K*R thJ-c δ= t p/Ƭ 0.01 Single pulse tp -2 10 -5 10 Figure 3. Output characteristics VGS=7, 8, 9, 10V 60 10 Ƭ -2 -3 tp (s) 10 10 Figure 4. Transfer characteristics GIPG080720141147MT ID (A) -4 GIPG080720141423MT ID (A) 60 6V 50 50 VDS=17V 40 40 5V 30 30 20 20 10 10 4V 0 0 10 5 15 20 VDS(V) Figure 5. Gate charge vs gate-source voltage GIPG230420141134MT VDS VGS (V) (V) VDD=480V ID=26A 12 500 VDS 10 400 0 0 2 6 4 8 10 VGS(V) Figure 6. Static drain-source on-resistance GIPG090720140852MT RDS(on) (Ω) VGS=10V 0.122 0.120 0.118 8 300 0.116 6 200 4 2 0 DS9512 - Rev 4 0 10 20 30 40 50 0.114 100 0.112 0 Qg (nC) 0.110 0 5 10 15 20 ID(A) page 5/15 STL33N60M2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations GIPG230420141135MT C (pF) GIPG230420141136MT VGS(th) (norm) ID=250µA 10000 1.1 Ciss 1000 1.0 100 Coss 10 0.9 0.8 Crss 1 0.1 1 100 10 VDS(V) Figure 9. Normalized on-resistance vs temperature GIPG090720140955MT RDS(on) (norm) 0.7 -50 -25 0 25 50 75 TJ(°C) 100 Figure 10. Normalized V(BR)DSS vs temperature GIPG090720141001MT V(BR)DSS (norm) VGS=10V 1.11 2.3 ID=1mA 1.09 2.1 1.07 1.9 1.05 1.03 1.7 1.5 1.01 1.3 0.99 1.1 0.97 0.9 0.95 0.7 0.5 -50 -25 0.93 0.91 -50 25 0 50 75 100 TJ(°C) Figure 11. Source-drain diode forward characteristics GIPG090720141014MT VSD(V) 1.4 -25 0 25 50 TJ(°C) 75 100 Figure 12. Output capacitance stored energy GIPG230420141137MT Eoss (µJ) 12 1.2 TJ=-50°C 10 1 8 0.8 6 0.6 0.4 TJ=150°C TJ=25°C 4 2 0.2 0 0 2 DS9512 - Rev 4 4 6 8 10 12 14 16 18 20 ISD(A) 0 0 100 200 300 400 500 600 VDS(V) page 6/15 STL33N60M2 Electrical characteristics (curves) Figure 13. Maximum avalanche energy vs temperature EAS (mJ) GADG070220191439EAS 400 300 ID = 5 A, VDD = 50 V 200 100 0 -75 DS9512 - Rev 4 -25 25 75 125 TJ (°C) page 7/15 STL33N60M2 Test circuits 3 Test circuits Figure 15. Gate charge test circuit Figure 14. Switching times test circuit for resistive load VDD 12 V RL + VD VGS µF VDD IG= CONST VGS RG 1 kΩ 100 nF 3.3 µF 2200 47 kΩ + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 AM01469v2 Figure 16. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 17. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 19. Switching time waveform Figure 18. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9512 - Rev 4 page 8/15 STL33N60M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 8x8 HV package information Figure 20. PowerFLAT 8x8 HV package outline 8222871_Rev_4 DS9512 - Rev 4 page 9/15 STL33N60M2 PowerFLAT 8x8 HV package information Table 7. PowerFLAT 8x8 HV mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 21. PowerFLAT 8x8 HV footprint 8222871_REV_4_footprint Note: DS9512 - Rev 4 All dimensions are in millimeters. page 10/15 STL33N60M2 PowerFLAT 8x8 HV packing information 4.2 PowerFLAT 8x8 HV packing information Figure 22. PowerFLAT 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 23. PowerFLAT 8x8 HV package orientation in carrier tape DS9512 - Rev 4 page 11/15 STL33N60M2 PowerFLAT 8x8 HV packing information Figure 24. PowerFLAT 8x8 HV reel 8229819_Reel_revA Note: DS9512 - Rev 4 All dimensions are in millimeters. page 12/15 STL33N60M2 Revision history Table 8. Document revision history Date Revision 26-Jun-2013 1 Changes First release. Updated the title, the features and the description in cover page. Document status promoted from preliminary data to production data. 23-Jul-2014 2 Updated Figure 1: "Internal schematic diagram", Section 1: "Electrical ratings", Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)" Updated Section 3: "Test circuits", Section 4.1: "PowerFLAT™ 8x8 HV package mechanical data".. Updated: cover image and Figure 1: "Internal schematic diagram" Table 2: "Absolute maximum ratings", Table 3: "Thermal data" and Table 6: "Switching times" 20-Nov-2015 3 Updated: Figure 3: "Thermal impedance" Updated: Section 5: "Test circuits" Updated: Section 6.1: "PowerFLAT™ 8x8 HV package mechanical data" Minor text changes Update Section 1 Electrical ratings. 11-Jun-2019 4 Added Figure 13. Maximum avalanche energy vs temperature. Minor text changes. DS9512 - Rev 4 page 13/15 STL33N60M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 PowerFLAT 8x8 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 PowerFLAT 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS9512 - Rev 4 page 14/15 STL33N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS9512 - Rev 4 page 15/15