STL33N65M2

STL33N65M2 N-channel 650 V, 0.124 Ω typ., 20 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2     1 PowerFLAT™ 8x8 HV Order code VDS RDS(on)max ID STL33N65M2 650 V 0.154 Ω 20 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications  Switching applications Figure 1: Internal schematic diagram Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STL33N65M2 33N65M2 PowerFLAT™ 8x8 HV Tape and reel April 2016 DocID026089 Rev 3 This is information on a product in full production. 1/15 www.st.com Contents STL33N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 8x8 HV package information .................................... 10 4.2 PowerFLAT™ 8x8 HV packing information ..................................... 12 Revision history ............................................................................ 14 DocID026089 Rev 3 STL33N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 20 A ID Drain current (continuous) at TC = 100 °C 12.6 A Drain current (pulsed) 80 A IDM Gate-source voltage Value (1) PTOT Total dissipation at TC = 25 °C 150 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range Tj Operating junction temperature range °C - 55 to 150 °C Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. ≤ 20 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V. DS ≤ 520 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case max 0.83 °C/W Thermal resistance junction-pcb max 45 °C/W Notes: (1)When mounted on FR-4 board of inch², 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tjmax) 2.2 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 600 mJ DocID026089 Rev 3 Value Unit 3/15 Electrical characteristics 2 STL33N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V 1 µA VGS = 0 V, VDS = 650 V, TC=125 °C (1) 100 µA Gate-body leakage current VDS = 0 V, VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 10 A 0.124 0.154 Ω Min. Typ. Max. Unit - 1790 - pF - 75 - pF - 2 - pF VDS = 0 to 520 V, VGS = 0 - 380 - pF VDD = 520 V, ID = 24 A VGS = 10 V (see Figure 15: "Gate charge test circuit") - 41.5 - nC - 6.8 - nC - 18 - nC IDSS Zero gate voltage drain current IGSS VGS = 0 V, VDS = 650 V 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Voltage rise time Turn-off delay time Current fall time Test conditions Min. Typ. Max. Unit VDD = 325 V, ID = 12 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 13.5 - ns - 11.5 - ns - 72.5 - ns - 11.5 - ns DocID026089 Rev 3 STL33N65M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter ISD Source-drain current ISDM (1) Source-drain current (pulsed) VSD (2) Forward on voltage Reverse recovery time trr Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions ISD = 24 A, VGS = 0 V ISD = 24 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 24 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Min. Typ. Max. Unit - 20 A - 80 A - 1.6 V - 426 ns - 7 µC - 33.5 A - 544 ns - 10 µC - 36.5 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID026089 Rev 3 5/15 Electrical characteristics 2.1 STL33N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID026089 Rev 3 STL33N65M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID026089 Rev 3 7/15 Test circuits 3 STL33N65M2 Test circuits Figure 15: Gate charge test circuit Figure 14: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 17: Unclamped inductive load test circuit Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B A D G L S L=100µH VD 3.3 µF B 25Ω D + 1000 µF 3.3 µF VDD + ID G RG 2200 µF VDD S D.U.T. Vi GND1 GND2 D.U.T. Pw GND1 Figure 18: Unclamped inductive waveform 8/15 DocID026089 Rev 3 GND2 AM15858v1 Figure 19: Switching time waveform STL33N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026089 Rev 3 9/15 Package information 4.1 STL33N65M2 PowerFLAT™ 8x8 HV package information Figure 20: PowerFLAT™ 8x8 HV package outline 8222871_Rev_3_ A 10/15 DocID026089 Rev 3 STL33N65M2 Package information Table 9: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 0.60 Figure 21: PowerFLAT™ 8x8 HV footprint All dimensions are in millimeters. DocID026089 Rev 3 11/15 Package information 4.2 STL33N65M2 PowerFLAT™ 8x8 HV packing information Figure 22: PowerFLAT™ 8x8 HV tape All dimensions are in millimeters. Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape 12/15 DocID026089 Rev 3 STL33N65M2 Package information Figure 24: PowerFLAT™ 8x8 HV reel All dimensions are in millimeters. DocID026089 Rev 3 13/15 Revision history 5 STL33N65M2 Revision history Table 10: Document revision history Date Revision 26-Jun-2013 1 First release. 2 Text edits throughout document. On cover page, updated title, features and description. Updated Table 2: Absolute maximum ratings. Updated Table 3: Thermal data. Added Table 4: Avalanche characteristics. Updated Table 5: On /off states. Updated Table 6: Dynamic. Updated Table 7: Switching times. Updated Table 8: Source drain diode. 3 Updated cover image and Figure 1: "Internal schematic diagram". Updated Section 3: "Test circuits". Added footnote in Table 5: "On /off states". Removed footnote in Table 8: "Source drain diode". Updated Section 4: "Package information". Minor text changes. 23-Jul-2014 13-Apr-2016 14/15 Changes DocID026089 Rev 3 STL33N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID026089 Rev 3 15/15