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STL34N65M5

STL34N65M5

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    PowerFlat™HV-4

  • 描述:

    MOSFET N-CH 650V 3.2A PWRFLAT88

  • 详情介绍
  • 数据手册
  • 价格&库存
STL34N65M5 数据手册
STL34N65M5 N-channel 650 V, 0.099 Ω typ., 22.5 A MDmesh™ V Power MOSFET in PowerFLAT™ 8x8 HV package Datasheet - production data Features 6  6  6  %RWWRPYLHZ *  '  Order code VDS @ TJmax RDS(on) max ID STL34N65M5 710 V 0.120 Ω 22.5 A(1) 1. The value is rated according to Rthj-case and limited by package. • 100% avalanche tested • Low input capacitance and gate charge 3RZHU)/$7Œ[+9 • Low gate input resistance Applications Figure 1. Internal schematic diagram • Switching applications Description '  This device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. *  6  $0Y Table 1. Device summary Order code Marking Package Packaging STL34N65M5 34N65M5 PowerFLAT™ 8x8 HV Tape and reel April 2014 This is information on a product in full production. DocID023325 Rev 1 1/15 www.st.com Contents STL34N65M5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ........................... 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/15 .............................................. 8 DocID023325 Rev 1 STL34N65M5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 22.5 A Drain current (continuous) at TC = 100 °C 15 A ID (1) ID (1) IDM (1),(2) Drain current (pulsed) 90 A ID(3) Drain current (continuous) at Tamb = 25 °C 3.2 A ID(3) Drain current (continuous) at Tamb = 100 °C 2 A Total dissipation at Tamb = 25 °C 2.8 W Total dissipation at TC = 25 °C 150 W PTOT (3) PTOT (1) IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 6 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 510 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit 0.83 °C/W 45 °C/W dv/dt (4) Tstg Storage temperature Tj Max. operating junction temperature 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of inch², 2oz Cu. 4. ISD ≤ 22.5 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD= 400 V. Table 3. Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max 1. When mounted on FR-4 board of inch², 2oz Cu. DocID023325 Rev 1 3/15 15 Electrical characteristics 2 STL34N65M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 Min. Typ. Max. Unit 650 V IDSS Zero gate voltage VDS = 650 V drain current (VGS = 0) VDS = 650 V, TC=125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) ±100 nA 4 5 V 0.099 0.120 Ω Min. Typ. Max. Unit - 2700 - pF - 75 - pF - 6.3 - pF - 63 - pF - 220 - pF f = 1 MHz open drain - 1.95 - Ω VDD = 520 V, ID = 14 A, VGS = 10 V (see Figure 15) - 62.5 - nC - 17 - nC - 28 - nC VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onVGS = 10 V, ID = 12 A resistance 3 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Co(tr)(2) Equivalent output capacitance energy related Equivalent output capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VGS = 0, VDS = 0 to 80% V(BR)DSS 1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS 2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS 4/15 DocID023325 Rev 1 STL34N65M5 Electrical characteristics Table 6. Switching times Symbol td(v) Parameter Voltage delay time tr(v) Voltage rise time tf(i) Current fall time tc(off) Test conditions VDD = 400 V, ID = 18 A, RG = 4.7 Ω, VGS = 10 V (see Figure 19) Crossing time Min. Typ. Max. Unit - 59 - ns - 8.7 - ns - 7.5 - ns - 12 - ns Min. Typ. Table 7. Source drain diode Symbol ISD(1) ISDM (1),(2) VSD (3) Parameter Test conditions Max. Unit Source-drain current - 22.5 A Source-drain current (pulsed) - 90 A - 1.5 V Forward on voltage ISD = 22.5 A, VGS = 0 trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V (see Figure 16) ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 16) - 330 ns - 5.3 µC - 32.5 A - 412 ns - 7.3 µC - 35.5 A 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID023325 Rev 1 5/15 15 Electrical characteristics 2.1 STL34N65M5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM14974v1 ID (A) Zth PowerFLAT 8x8 HV K a DS (o Op Lim era ite tion d by in th m is ax ar R e δ=0.5 n) is Tj=150°C Tc=25°C Single pulse 10 0.2 10µs 0.1 100µs -1 10 0.05 0.02 1 1ms 0.01 Single pulse 10ms -2 0.1 0.1 10 1 10 -5 10 VDS(V) 100 Figure 4. Output characteristics -4 -2 -3 10 tp (s) 10 10 Figure 5. Transfer characteristics AM14975v1 ID (A) AM14976v1 ID (A) VGS=10V 80 VDS=25V 80 8V 70 70 60 60 50 50 40 40 7V 30 30 20 20 10 10 6V 0 0 10 5 15 20 25 Figure 6. Gate charge vs gate-source voltage VGS (V) AM14978v1 VDS VDD=520V ID=14A 12 VDS 0 0 VDS(V) 2 4 6 8 10 12 VGS(V) Figure 7. Static drain-source on-resistance (V) RDS(on) (Ω) 500 0.115 AM14977v1 VGS=10V 0.110 10 400 8 0.105 300 0.100 6 200 4 100 2 0 0 6/15 10 20 30 40 50 60 0 70 Qg(nC) 0.095 0.090 0.085 0 DocID023325 Rev 1 5 10 15 20 ID(A) STL34N65M5 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM14979v1 C (pF) AM14980v1 Eoss (µJ) 12 10000 Ciss 10 1000 8 6 100 Coss 4 10 2 Crss 1 0.1 1 100 10 Figure 10. Normalized gate threshold voltage vs temperature AM05459v1 VGS(th) (norm) 1.10 0 0 VDS(V) ID = 250 µA 100 200 300 400 500 600 VDS(V) Figure 11. Normalized on-resistance vs temperature RDS(on) (norm) 2.1 AM05460v1 VGS = 10 V ID = 12 A 1.9 1.00 1.7 1.5 1.3 0.90 1.1 0.80 0.9 0.7 0.70 -50 -25 0 25 50 TJ(°C) 75 100 Figure 12. Switching losses vs gate resistance (1) AM14981v1 E (μJ) 500 0 25 50 75 100 TJ(°C) Figure 13. Normalized VDS vs temperature AM10399v1 VDS (norm) Eon ID=18A VDD=400V VGS=10V 0.5 -50 -25 1.08 ID = 1mA 1.06 400 1.04 1.02 300 1.00 200 0.98 Eoff 0.96 100 0.94 0 0 10 20 30 40 RG(Ω) 0.92 -50 -25 0 25 50 75 100 TJ(°C) 1. Eon including reverse recovery of a SiC diode DocID023325 Rev 1 7/15 15 Test circuits 3 STL34N65M5 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform V(BR)DSS Figure 19. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD 10%Id 10%Vds Vds Trise AM01472v1 8/15 DocID023325 Rev 1 Tfall Tcross --over AM05540v2 STL34N65M5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID023325 Rev 1 9/15 15 Package mechanical data STL34N65M5 Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data 8222871_REV_C 10/15 DocID023325 Rev 1 STL34N65M5 Package mechanical data Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.95 1.00 1.05 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e 2.00 L 0.40 0.50 0.60 Figure 21. PowerFLAT™ 8x8 HV recommended footprint 0.60 7.70 4.40 7.30 2.00 1.05 Footprin DocID023325 Rev 1 11/15 15 Packaging mechanical data 5 STL34N65M5 Packaging mechanical data Figure 22. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk quantity 3000 pcs 8229819_Tape_revA Figure 23. PowerFLAT™ 8x8 HV package orientation in carrier tape. 12/15 DocID023325 Rev 1 STL34N65M5 Packaging mechanical data Figure 24. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA DocID023325 Rev 1 13/15 15 Revision history 6 STL34N65M5 Revision history Table 9. Document revision history 14/15 Date Revision 07-Apr-2014 1 Changes First release. DocID023325 Rev 1 STL34N65M5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID023325 Rev 1 15/15 15
STL34N65M5
- 物料型号:STL34N65M5 - 器件简介:N-channel MDmesh™ V Power MOSFET,采用创新的垂直工艺技术,具有极低的导通电阻,特别适合需要高功率密度和卓越效率的应用。 - 引脚分配:文档中提供了内部原理图和引脚分配,例如: - G(1):栅极 - S(2):源极 - D(3):漏极 - 参数特性:包括电气额定值、热数据、电气特性等,例如: - Vps:漏源电压650V - VGS:栅源电压±25V - Rthj-case:结到外壳的热阻最大0.83°C/W - 功能详解:文档详细描述了器件的电气特性,包括导通和截止状态、动态特性、开关时间等。 - 应用信息:适用于开关应用。 - 封装信息:采用PowerFLAT™ 8x8 HV封装,文档提供了详细的机械数据和推荐足迹。
STL34N65M5 价格&库存

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