STL34N65M5
N-channel 650 V, 0.099 Ω typ., 22.5 A MDmesh™ V
Power MOSFET in PowerFLAT™ 8x8 HV package
Datasheet - production data
Features
6
6
6
%RWWRPYLHZ
*
'
Order code
VDS @
TJmax
RDS(on)
max
ID
STL34N65M5
710 V
0.120 Ω
22.5 A(1)
1. The value is rated according to Rthj-case and limited by
package.
• 100% avalanche tested
• Low input capacitance and gate charge
3RZHU)/$7[+9
• Low gate input resistance
Applications
Figure 1. Internal schematic diagram
• Switching applications
Description
'
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
*
6
$0Y
Table 1. Device summary
Order code
Marking
Package
Packaging
STL34N65M5
34N65M5
PowerFLAT™ 8x8 HV
Tape and reel
April 2014
This is information on a product in full production.
DocID023325 Rev 1
1/15
www.st.com
Contents
STL34N65M5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
........................... 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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DocID023325 Rev 1
STL34N65M5
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
650
V
VGS
Gate-source voltage
± 25
V
Drain current (continuous) at TC = 25 °C
22.5
A
Drain current (continuous) at TC = 100 °C
15
A
ID
(1)
ID (1)
IDM
(1),(2)
Drain current (pulsed)
90
A
ID(3)
Drain current (continuous) at Tamb = 25 °C
3.2
A
ID(3)
Drain current (continuous) at Tamb = 100 °C
2
A
Total dissipation at Tamb = 25 °C
2.8
W
Total dissipation at TC = 25 °C
150
W
PTOT (3)
PTOT
(1)
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
6
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
510
mJ
Peak diode recovery voltage slope
15
V/ns
- 55 to 150
°C
150
°C
Value
Unit
0.83
°C/W
45
°C/W
dv/dt (4)
Tstg
Storage temperature
Tj
Max. operating junction temperature
1. The value is rated according to Rthj-case and limited by package.
2. Pulse width limited by safe operating area.
3. When mounted on FR-4 board of inch², 2oz Cu.
4. ISD ≤ 22.5 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD= 400 V.
Table 3. Thermal data
Symbol
Rthj-case
Rthj-amb
(1)
Parameter
Thermal resistance junction-case max
Thermal resistance junction-ambient max
1. When mounted on FR-4 board of inch², 2oz Cu.
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Electrical characteristics
2
STL34N65M5
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4. On /off states
Symbol
V(BR)DSS
Parameter
Drain-source
breakdown voltage
Test conditions
ID = 1 mA, VGS = 0
Min.
Typ.
Max.
Unit
650
V
IDSS
Zero gate voltage
VDS = 650 V
drain current (VGS = 0) VDS = 650 V, TC=125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
±100
nA
4
5
V
0.099
0.120
Ω
Min.
Typ.
Max.
Unit
-
2700
-
pF
-
75
-
pF
-
6.3
-
pF
-
63
-
pF
-
220
-
pF
f = 1 MHz open drain
-
1.95
-
Ω
VDD = 520 V, ID = 14 A,
VGS = 10 V
(see Figure 15)
-
62.5
-
nC
-
17
-
nC
-
28
-
nC
VGS = ± 25 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source onVGS = 10 V, ID = 12 A
resistance
3
Table 5. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Co(er)(1)
Co(tr)(2)
Equivalent output
capacitance energy
related
Equivalent output
capacitance time
related
RG
Intrinsic gate
resistance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0
VGS = 0,
VDS = 0 to 80% V(BR)DSS
1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0
to 80% VDSS
2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0
to 80% VDSS
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STL34N65M5
Electrical characteristics
Table 6. Switching times
Symbol
td(v)
Parameter
Voltage delay time
tr(v)
Voltage rise time
tf(i)
Current fall time
tc(off)
Test conditions
VDD = 400 V, ID = 18 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 19)
Crossing time
Min.
Typ.
Max. Unit
-
59
-
ns
-
8.7
-
ns
-
7.5
-
ns
-
12
-
ns
Min.
Typ.
Table 7. Source drain diode
Symbol
ISD(1)
ISDM
(1),(2)
VSD
(3)
Parameter
Test conditions
Max. Unit
Source-drain current
-
22.5
A
Source-drain current (pulsed)
-
90
A
-
1.5
V
Forward on voltage
ISD = 22.5 A, VGS = 0
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 22.5 A,
di/dt = 100 A/µs
VDD = 100 V (see Figure 16)
ISD = 22.5 A,
di/dt = 100 A/µs
VDD = 100 V, Tj = 150 °C
(see Figure 16)
-
330
ns
-
5.3
µC
-
32.5
A
-
412
ns
-
7.3
µC
-
35.5
A
1. The value is rated according to Rthj-case and limited by package.
2. Pulse width limited by safe operating area.
3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
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Electrical characteristics
2.1
STL34N65M5
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
AM14974v1
ID
(A)
Zth PowerFLAT 8x8 HV
K
a
DS
(o
Op
Lim era
ite tion
d
by in th
m is
ax ar
R e
δ=0.5
n)
is
Tj=150°C
Tc=25°C
Single pulse
10
0.2
10µs
0.1
100µs
-1
10
0.05
0.02
1
1ms
0.01
Single pulse
10ms
-2
0.1
0.1
10
1
10 -5
10
VDS(V)
100
Figure 4. Output characteristics
-4
-2
-3
10
tp (s)
10
10
Figure 5. Transfer characteristics
AM14975v1
ID (A)
AM14976v1
ID (A)
VGS=10V
80
VDS=25V
80
8V
70
70
60
60
50
50
40
40
7V
30
30
20
20
10
10
6V
0
0
10
5
15
20
25
Figure 6. Gate charge vs gate-source voltage
VGS
(V)
AM14978v1
VDS
VDD=520V
ID=14A
12
VDS
0
0
VDS(V)
2
4
6
8
10
12
VGS(V)
Figure 7. Static drain-source on-resistance
(V)
RDS(on)
(Ω)
500
0.115
AM14977v1
VGS=10V
0.110
10
400
8
0.105
300
0.100
6
200
4
100
2
0
0
6/15
10
20
30
40
50
60
0
70 Qg(nC)
0.095
0.090
0.085
0
DocID023325 Rev 1
5
10
15
20
ID(A)
STL34N65M5
Electrical characteristics
Figure 8. Capacitance variations
Figure 9. Output capacitance stored energy
AM14979v1
C
(pF)
AM14980v1
Eoss
(µJ)
12
10000
Ciss
10
1000
8
6
100
Coss
4
10
2
Crss
1
0.1
1
100
10
Figure 10. Normalized gate threshold voltage vs
temperature
AM05459v1
VGS(th)
(norm)
1.10
0
0
VDS(V)
ID = 250 µA
100
200 300
400 500 600
VDS(V)
Figure 11. Normalized on-resistance vs
temperature
RDS(on)
(norm)
2.1
AM05460v1
VGS = 10 V
ID = 12 A
1.9
1.00
1.7
1.5
1.3
0.90
1.1
0.80
0.9
0.7
0.70
-50 -25
0
25
50
TJ(°C)
75 100
Figure 12. Switching losses vs gate resistance
(1)
AM14981v1
E
(μJ)
500
0
25
50
75 100
TJ(°C)
Figure 13. Normalized VDS vs temperature
AM10399v1
VDS
(norm)
Eon
ID=18A
VDD=400V
VGS=10V
0.5
-50 -25
1.08
ID = 1mA
1.06
400
1.04
1.02
300
1.00
200
0.98
Eoff
0.96
100
0.94
0
0
10
20
30
40
RG(Ω)
0.92
-50 -25
0
25
50
75 100
TJ(°C)
1. Eon including reverse recovery of a SiC diode
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Test circuits
3
STL34N65M5
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
Figure 16. Test circuit for inductive load
switching and diode recovery times
A
A
D.U.T.
FAST
DIODE
B
B
AM01469v1
Figure 17. Unclamped inductive load test circuit
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 18. Unclamped inductive waveform
V(BR)DSS
Figure 19. Switching time waveform
Concept waveform for Inductive Load Turn-off
Id
VD
90%Vds
90%Id
Tdelay-off
-off
IDM
Vgs
90%Vgs
on
ID
Vgs(I(t))
))
VDD
VDD
10%Id
10%Vds
Vds
Trise
AM01472v1
8/15
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Tfall
Tcross --over
AM05540v2
STL34N65M5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID023325 Rev 1
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Package mechanical data
STL34N65M5
Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data
8222871_REV_C
10/15
DocID023325 Rev 1
STL34N65M5
Package mechanical data
Table 8. PowerFLAT™ 8x8 HV mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.95
1.00
1.05
D
8.00
E
8.00
D2
7.05
7.20
7.30
E2
4.15
4.30
4.40
e
2.00
L
0.40
0.50
0.60
Figure 21. PowerFLAT™ 8x8 HV recommended footprint
0.60
7.70
4.40
7.30
2.00
1.05
Footprin
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Packaging mechanical data
5
STL34N65M5
Packaging mechanical data
Figure 22. PowerFLAT™ 8x8 HV tape
P2 (2.0±0.1)
T (0.30±0.05)
P0 (4.0±0.1)
D0 ( 1.55±0.05)
D1 ( 1.5 Min)
P1 (12.00±0.1)
W (16.00±0.3)
F (7.50±0.1)
B0 (8.30±0.1)
E (1.75±0.1)
A0 (8.30±0.1)
K0 (1.10±0.1)
Note: Base and Bulk quantity 3000 pcs
8229819_Tape_revA
Figure 23. PowerFLAT™ 8x8 HV package orientation in carrier tape.
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STL34N65M5
Packaging mechanical data
Figure 24. PowerFLAT™ 8x8 HV reel
8229819_Reel_revA
DocID023325 Rev 1
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15
Revision history
6
STL34N65M5
Revision history
Table 9. Document revision history
14/15
Date
Revision
07-Apr-2014
1
Changes
First release.
DocID023325 Rev 1
STL34N65M5
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