STL35N75LF3

STL35N75LF3 N-channel 75 V, 20 mΩ typ., 32 A STripFET™ F3 Power MOSFET in a PowerFLAT™ 3.3x3.3 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STL35N75LF3 75 V 25 mΩ 32 A 50 W   Low gate charge Low threshold voltage device Applications  Switching applications Description Figure 1: Internal schematic diagram This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. Table 1: Device summary Order code Marking Package Packing STL35N75LF3 35N75 PowerFLAT™ 3.3x3.3 Tape and reel August 2016 DocID026698 Rev 4 This is information on a product in full production. 1/14 www.st.com Contents STL35N75LF3 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/14 PowerFLAT™ 3.3x3.3 package information .................................... 10 Revision history ............................................................................ 13 DocID026698 Rev 4 STL35N75LF3 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 75 V VGS Gate-source voltage ±20 V Drain current (continuous) at Tcase = 25 °C 32 Drain current (continuous) at Tcase = 100 °C 20 Drain current (pulsed) 128 ID(1) IDM(1)(2) A A Drain current (continuous) at Tpcb = 25 °C 8 Drain current (continuous) at Tpcb = 100 °C 5 PTOT(1) Total dissipation at Tcase = 25 °C 50 PTOT(3) Total dissipation at Tpcb = 25 °C 2.9 W EAS(4) Single pulse avalanche energy 230 mJ -55 to 150 °C ID(3) Tstg Storage temperature range Tj Operating junction temperature range A W Notes: (1)The (2) value is rated according to Rthj-case. Pulse width is limited by safe operating area. (3)The value is rated according to Rthj-pcb. (4)Starting Tj = 25 °C, ID = 6 A, VDD = 50 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Thermal resistance junction-case max. 2.5 Thermal resistance junction-pcb max. 42.8 Unit °C/W Notes: (1)When mounted on a 1 inch², 2 oz Cu, FR-4 board, t < 10 s. DocID026698 Rev 4 3/14 Electrical characteristics 2 STL35N75LF3 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 µA Min. Typ. Max. 75 Unit V VGS = 0 V, VDS = 75 V 1 VGS = 0 V, VDS = 75 V, Tcase = 125 °C(1) 10 Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 20 25 mΩ VGS = 4.5 V, ID = 4 A 25 30 mΩ Min. Typ. Max. Unit - 800 - - 110 - - 15 - - 7.5 - - 3.2 - - 3.0 - Min. Typ. Max. - 6.8 - - 3 - - 22.8 - - 2.2 - IDSS Zero gate voltage drain current IGSS 1 µA Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 37.5 V, ID = 8 A, VGS = 4.5 V (see Figure 14: "Test circuit for gate charge behavior") pF nC Table 6: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 37.5 V, ID = 4 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") DocID026698 Rev 4 Unit ns STL35N75LF3 Electrical characteristics Table 7: Source-drain diode Symbol VSD(1) trr Parameter Test conditions Forward on voltage VGS = 0 V, ISD = 8 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V Min. Typ. - Max. Unit 1.1 V - 26 ns - 24 nC - 1.8 A Notes: (1) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID026698 Rev 4 5/14 Electrical characteristics 2.1 6/14 STL35N75LF3 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized gate threshold voltage vs. temperature Figure 7: Normalized V(BR)DSS vs. temperature DocID026698 Rev 4 STL35N75LF3 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs. gate-source voltage Figure 11: Capacitance variations Figure 12: Source-drain diode forward characteristics DocID026698 Rev 4 7/14 Test circuits 3 8/14 STL35N75LF3 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID026698 Rev 4 STL35N75LF3 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026698 Rev 4 9/14 Package information 4.1 STL35N75LF3 PowerFLAT™ 3.3x3.3 package information Figure 19: PowerFLAT™ 3.3x3.3 package outline BOTTOM VIEW SIDE VIEW TOP VIEW 8465286_ A 10/14 DocID026698 Rev 4 STL35N75LF3 Package information Table 8: PowerFLAT™ 3.3x3.3 package mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 030 0.45 0.60 L1 0.05 0.15 0.25 L2 θ 0.15 8° DocID026698 Rev 4 10° 12° 11/14 Package information STL35N75LF3 Figure 20: PowerFLAT™ 3.3x3.3 recommended footprint 8465286_footprint 12/14 DocID026698 Rev 4 STL35N75LF3 5 Revision history Revision history Table 9: Document revision history Date Revision 16-Jul-2014 1 First release. 2 Document status promoted from preliminary to production data. Added Section 2.1: Electrical characteristics (curves). Minor text changes. 27-Jun-2016 3 Updated title and package silhouette in cover page. Updated Section 1: "Electrical ratings". Updated Section 2: "Electrical characteristics". Updated Section 2.1: "Electrical characteristics (curves)". Minor text edits. 08-Aug-2016 4 Updated Section 2: "Electrical characteristics". 12-Nov-2014 Changes DocID026698 Rev 4 13/14 STL35N75LF3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 14/14 DocID026698 Rev 4