STL36N55M5

STL36N55M5 N-channel 550 V, 0.066 Ω typ., 22.5 A MDmesh™ M5 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet — production data Features 6 6 6 %RWWRPYLHZ * Order code VDS @ TJmax RDS(on) max ID STL36N55M5 600 V 0.090 Ω 22.5 A ' • Extremely low RDS(on) • Low gate charge and input 3RZHU)/$7Œ[+9 • capacitance • Excellent switching performance • 100% avalanche tested Applications Figure 1. Internal schematic diagram • Switching applications Description ' This device is an N-channel Power MOSFET based on MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. * 6 $0Y Table 1. Device summary Order code Marking Package Packaging STL36N55M5 36N55M5 PowerFLAT™ 8x8 HV Tape and reel September 2014 This is information on a product in full production. DocID022602 Rev 4 1/16 www.st.com Contents STL36N55M5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 9 DocID022602 Rev 4 STL36N55M5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 550 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 22.5 A Drain current (continuous) at TC = 100 °C 17 A ID (1) ID (1) IDM (1),(2) Drain current (pulsed) 90 A ID(3) Drain current (continuous) at Tamb = 25 °C 3.7 A ID(3) Drain current (continuous) at Tamb = 100 °C 2.2 A Total dissipation at Tamb = 25 °C 2.8 W Total dissipation at TC = 25 °C 150 W 7 A PTOT (3) PTOT (1) IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 510 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit 0.83 °C/W 45 °C/W dv/dt (4) Tstg Storage temperature Tj Max. operating junction temperature 1. The value is rated according to Rthj-case and limited by package.. 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of inch², 2 oz Cu. 4. ISD ≤ 22.5 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 340 V Table 3. Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max 1. When mounted on FR-4 board of inch², 2 oz Cu. DocID022602 Rev 4 3/16 16 Electrical characteristics 2 STL36N55M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 IDSS VDS = 550 V Zero gate voltage drain current (VGS = 0) VDS = 550 V, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Min. Typ. Max. Unit 550 V 1 µA 100 µA ±100 nA 4 5 V 0.066 0.090 Ω Min. Typ. Max. Unit - 2670 - pF - 75 - pF - 6.6 - pF - 71 - pF - 192 - pF f = 1 MHz open drain - 1.85 - Ω VDD = 440 V, ID = 16.5 A, VGS = 10 V (see Figure 16) - 62 - nC - 15 - nC - 27 - nC VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onVGS = 10 V, ID = 16.5 A resistance 3 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Co(tr)(2) Equivalent output capacitance energy related Equivalent output capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VGS = 0, VDS = 0 to 440 V 1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS 2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS 4/16 DocID022602 Rev 4 STL36N55M5 Electrical characteristics Table 6. Switching times Symbol td(V) Parameter Voltage delay time tr(V) Voltage rise time tf(i) Current fall time tc(off) Test conditions VDD = 400 V, ID = 22 A, RG = 4.7 Ω VGS = 10 V (see Figure 20) Crossing time Min. Typ. Max Unit - 56 - ns - 13 - ns - 13 - ns - 17 - ns Table 7. Source drain diode Symbol ISD (1) ISDM (1),(2) VSD (3) trr Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 22.5 A Source-drain current (pulsed) - 90 A - 1.5 V Forward on voltage ISD = 22.5 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V (see Figure 17) ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 17) - 292 ns - 4.2 µC - 29 A - 364 ns - 6 µC - 33 A 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area 3. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID022602 Rev 4 5/16 16 Electrical characteristics 2.1 STL36N55M5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM14937v1 ID (A) Zth PowerFLAT 8x8 HV K (o n ) δ=0.5 DS Op Lim era ite tion d by in th ma is a x R re a is Tj=150°C Tc=25°C Single pulse 10 0.2 10µs 0.1 100µs -1 10 0.05 0.02 1 1ms 0.01 Single pulse 10ms -2 0.1 0.1 10 1 100 10 -5 10 VDS(V) Figure 4. Output characteristics -4 -2 -3 10 tp (s) 10 10 Figure 5. Transfer characteristics AM14930v1 ID (A) AM14931v1 ID (A) VGS=9, 10V 8V 70 VDS=25V 70 7V 60 60 50 50 40 40 30 30 6V 20 20 10 10 0 0 5 10 15 0 20 25 VDS(V) Figure 6. Gate charge vs gate-source voltage AM14932v1 VDS(V) VGS (V) VDS 12 VDD=440V ID=16.5A 10 5 6 7 8 VGS(V) 9 AM14933v2 RDS(on) (Ω) 0.071 400 0.069 300 4 Figure 7. Static drain-source on-resistance 450 350 8 3 VGS=10V 0.067 0.065 250 6 200 4 2 0 0 6/16 10 20 30 40 50 60 0.063 150 0.061 100 0.059 50 0.057 0 70 Qg(nC) 0.055 0 DocID022602 Rev 4 5 10 15 20 ID(A) STL36N55M5 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM14934v1 C (pF) AM14935v1 Eoss (µJ) 10 10000 Ciss 8 1000 6 100 10 1 0.1 1 100 10 Coss 4 Crss 2 Figure 10. Normalized gate threshold voltage vs temperature AM05459v3 VGS(th) (norm) 1.10 0 0 VDS(V) ID=250µA 200 100 300 400 500 VDS(V) Figure 11. Normalized on-resistance vs temperature AM05460v3 RDS(on) (norm) 2.1 VGS=10V ID=16.5V 1.9 1.00 1.7 1.5 1.3 0.90 1.1 0.80 0.9 0.7 0.70 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Source-drain diode forward characteristics AM05461v3 VSD (V) 0.5 -50 -25 0 25 50 75 100 TJ(°C) Figure 13. Normalized V(BR)DSS vs temperature $0Y 9%5'66 QRUP TJ=-50°C  1.2 ,' P$  1.0  0.8  TJ=25°C  0.6 TJ=150°C  0.4  0.2 0  0 10 20 30 40 50 ISD(A)    DocID022602 Rev 4      7-ƒ& 7/16 16 Electrical characteristics STL36N55M5 Figure 14. Switching losses vs gate resistance (1) E (μJ) 600 AM14936v1 ID=22A VDD=400V VGS=10V Eon 500 400 300 Eoff 200 100 0 0 10 20 30 40 RG(Ω) 1. Eon including reverse recovery of a SiC diode. 8/16 DocID022602 Rev 4 STL36N55M5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform V(BR)DSS Figure 20. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD 10%Id 10%Vds Vds Trise AM01472v1 DocID022602 Rev 4 Tfall Tcross --over AM05540v2 9/16 16 Package mechanical data 4 STL36N55M5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10/16 DocID022602 Rev 4 STL36N55M5 Package mechanical data Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data 8222871_REV_C DocID022602 Rev 4 11/16 16 Package mechanical data STL36N55M5 Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.95 1.00 1.05 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e L 2.00 0.40 0.50 0.60 Figure 22. PowerFLAT™ 8x8 HV recommended footprint 8222871_REV_C_footprint 12/16 DocID022602 Rev 4 STL36N55M5 Packaging mechanical data Figure 23. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) E (1.75±0.1) B0 (8.30±0.1) 5 Packaging mechanical data A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk quantity 3000 pcs 8229819_Tape_revA Figure 24. PowerFLAT™ 8x8 HV package orientation in carrier tape. DocID022602 Rev 4 13/16 16 Packaging mechanical data STL36N55M5 Figure 25. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA 14/16 DocID022602 Rev 4 STL36N55M5 6 Revision history Revision history Table 9. Document revision history Date Revision Changes 14-Dec-2011 1 First release. 17-Oct-2012 2 Updated: Table 5, 6 and Table 7.: Source drain diode typ. values 24-Jan-2013 3 – Modified: Figure 1: Internal schematic diagram 4 and 6 – Document status promoted from preliminary data to production data – Modified: VDD on Table 5 – Minor text changes 22-Sep-2014 4 – Updated title, features and description in cover page. – Updated Figure 1: Internal schematic diagram. – Updated Section 4: Package mechanical data. DocID022602 Rev 4 15/16 16 STL36N55M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 16/16 DocID022602 Rev 4