STL38N65M5

STL38N65M5 N-channel 650 V, 0.090 Ω typ., 22.5 A MDmesh™ M5 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2 Order code VDS @ TJmax RDS(on) max. ID STL38N65M5 710 V 0.105 Ω 22.5 A     1 PowerFLAT™ 8x8 HV Extremely low RDS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications  Switching applications Figure 1: Internal schematic diagram Description Drain(5) This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Gate(1) Driver source (2) Power source (3, 4) NG1DS2PS34D5 Table 1: Device summary Order code Marking Package Packaging STL38N65M5 38N65M5 PowerFLAT™ 8x8 HV Tape and reel August 2015 DocID023239 Rev 2 This is information on a product in full production. 1/16 www.st.com Contents STL38N65M5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 PowerFLAT™ 8x8 HV package information .................................... 11 4.2 PowerFLAT™ 8x8 HV packing information ..................................... 13 Revision history ............................................................................ 15 DocID023239 Rev 2 STL38N65M5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C 22.5 A ID(1) Drain current (continuous) at TC = 100 °C 16 A IDM(1)(2) Drain current (pulsed) 90 A ID(3) Drain current (continuous) at Tpcb = 25 °C 3.5 A ID(3) Drain current (continuous) at Tpcb = 100 °C 2.2 A Total dissipation at Tpcb = 25 °C 2.8 W Total dissipation at TC = 25 °C 150 W 7 A PTOT (3) PTOT(1) IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 660 mJ Peak diode recovery voltage slope 15 V/ns dv/dt(4) Tstg Storage temperature Tj - 55 to 150 Max. operating junction temperature 150 °C Notes: (1)The value is rated according to Rthj-case. (2)Pulse width limited by safe operating area. (3) When mounted on FR-4 board of 1 inch² , 2oz Cu. (4)I SD ≤ 22.5 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case max 0.83 °C/W Thermal resistance junction-pcb max 45 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu. DocID023239 Rev 2 3/16 Electrical characteristics 2 STL38N65M5 Electrical characteristics TC = 25 °C unless otherwise specified Table 4: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 12.5 A 0.090 0.105 Ω Min. Typ. Max. Unit - 3000 - pF - 74 - pF - 5.8 - pF - 70 - pF - 244 - pF - 2.4 - Ω - 71 - nC - 18 - nC - 30 - nC 3 Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Co(er)(1) Equivalent output capacitance energy related Co(tr)(2) Equivalent output capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 0 to 80% V(BR)DSS, VGS = 0 V f = 1 MHz VDD = 520 V, ID = 15 A, VGS = 10 V (see Figure 16: "Gate charge test circuit") Notes: (1)C o(er) is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2)C o(tr) is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS 4/16 DocID023239 Rev 2 STL38N65M5 Electrical characteristics Table 6: Switching times Symbol Parameter td(V) Voltage delay time tr(V) Voltage rise time tf(i) Crossing fall time tC(off) Crossing time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 20 A RG = 4.7 Ω, VGS = 10 V (see Figure 17: " Test circuit for inductive load switching and diode recovery times"and Figure 20: "Switching time waveform") - 66 - ns - 9 - ns - 9 - ns - 13 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol Parameter Test conditions ISD(1) Source-drain current - 22.5 A ISDM(1),(2) Source-drain current (pulsed) - 90 A VSD (3) Forward on voltage VGS = 0 V, ISD = 22.5 A - 1.5 V trr Reverse recovery time - 354 ns Qrr Reverse recovery charge - 6 µC IRRM Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 17: " Test circuit for inductive load switching and diode recovery times") - 34 A ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 17: " Test circuit for inductive load switching and diode recovery times") - 428 ns - 8 µC - 38 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)The value is rated according to Rthj-case and limited by package. (2)Pulse width is limited by safe operating area (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID023239 Rev 2 5/16 Electrical characteristics 2.1 STL38N65M5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 10 -4 10 -3 10 Ƭ -2 tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance RDS(on) (Ω) 0.10 VGS=10V 0.095 0.090 0.085 0.080 0.075 0 6/16 DocID023239 Rev 2 5 10 15 20 ID(A) STL38N65M5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature RDS(on) (norm) 2.1 AM05460v2 AM10399v1 V(BR)DSS (norm.) VGS = 10 V 1.08 ID = 1mA 1.9 1.06 1.7 1.04 1.5 1.02 1.3 1.00 1.1 0.98 0.9 0.96 0.7 0.94 0.5 -50 -25 0.92 -50 -25 0 25 50 75 100 TJ(°C) Figure 12: Output capacitance stored energy DocID023239 Rev 2 0 25 50 75 100 TJ(°C) Figure 13: Source-drain diode forward characteristics 7/16 Electrical characteristics STL38N65M5 Figure 14: Switching losses vs gate resistance E (µJ) 600 500 Eon ID=20A VDD=400V L=50µH 400 300 Eoff 200 100 0 0 10 20 30 40 RG(Ω) The previous figure Eon includes reverse recovery of a SiC diode. 8/16 DocID023239 Rev 2 STL38N65M5 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF Figure 16: Gate charge test circuit VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 17: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 18: Unclamped inductive load test circuit A D G S 3.3 µF B 25Ω L L=100µH D + 1000 µF VD 2200 µF VDD 3.3 µF VDD + G RG ID S D.U.T. Vi GND1 D.U.T. GND2 Pw GND1 Figure 19: Unclamped inductive waveform GND2 AM15858v1 Figure 20: Switching time waveform Concept waveform for Inductive Load Turn-o ff Id 90%Vds 90%Id Tdelay-off -off Vgs 90%Vgs on Vgs(I(t)) )) 10%Vds 10%Id Vds Trise Tfall Tcross --over DocID023239 Rev 2 AM05540v2 9/16 Package information 4 STL38N65M5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID023239 Rev 2 STL38N65M5 4.1 Package information PowerFLAT™ 8x8 HV package information Figure 21: PowerFLAT™ 8x8 HV drawing 8222871_Rev_3_ A DocID023239 Rev 2 11/16 Package information STL38N65M5 Table 8: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 Figure 22: PowerFLAT™ 8x8 HV drawing All the dimensions are in millimeters. 12/16 DocID023239 Rev 2 0.60 STL38N65M5 4.2 Package information PowerFLAT™ 8x8 HV packing information Figure 23: PowerFLAT™ 8x8 HV tape Figure 24: PowerFLAT™ 8x8 HV package orientation in carrier tape DocID023239 Rev 2 13/16 Package information STL38N65M5 Figure 25: PowerFLAT™ 8x8 HV reel 14/16 DocID023239 Rev 2 STL38N65M5 5 Revision history Revision history Table 9: Document revision history Date Revision 17-Jan-2013 1 First release. 2 Updated title, features, internal schematic and description on cover page. Document status promoted from preliminary to production data. Updated package information. Minor text changes. 27-Aug-2015 Changes DocID023239 Rev 2 15/16 STL38N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID023239 Rev 2