STL3N65M2

STL3N65M2 N-channel 650 V, 1.6 Ω typ., 2.3 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 3.3x3.3 HV package Datasheet - production data Features 12 87 6 3 4 56 5 7     8 Order code VDS RDS(on) max. ID STL3N65M2 650 V 1.8 Ω 2.3 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Application PowerFLAT™ 3.3x3.3 HV  Switching applications Figure 1: Internal schematic diagram Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary April 2016 Order code Marking Package Packing STL3N65M2 3N65M2 PowerFLAT™ 3.3x3.3 HV Tape and reel DocID027894 Rev 3 This is information on a product in full production. 1/12 www.st.com Contents STL3N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 Power FLAT™ 3.3x3.3 HV package information ............................... 9 Revision history ............................................................................ 11 DocID027894 Rev 3 STL3N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C 2.3 A ID (1) Drain current (continuous) at TC= 100 °C 1.45 A ID (2) Drain current (continuous) at Tamb = 25 °C 0.7 A ID (2) Drain current (continuous) at Tamb = 100 °C 0.43 A Drain current (pulsed) 2.8 A 2 W IDM(2)(3) PTOT (2) Total dissipation at Tamb = 25 °C PTOT (1) Total dissipation at TC = 25 °C 22 W Avalanche current, repetitive or not-repetitive(3) 0.3 A 70 mJ 15 V/ns -55 to 150 °C IAS Single pulse avalanche energy EAS dv/dt (5) (4) Peak diode recovery voltage slope TJ Tstg Operating junction temperature range Storage temperature range Notes: (1)The value is rated according Rthj-case. (2) When mounted on FR-4 board of 1 inch², 2 oz Cu, t < 10 s. (3)Pulse width limited by Tjmax. (4)Starting (5)I SD Tj = 25 °C, ID = IAS, VDD = 50 V. ≤ 2.3 A, dv/dt ≤ 400 A/µs,VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS. Table 3: Thermal resistance Symbol Rthj-case Rthj-amb (1) Parameter Value Unit Thermal resistance junction-case max. 5.6 °C/W Thermal resistance junction-amb max. 62.5 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2 oz Cu, t < 10 s. DocID027894 Rev 3 3/12 Electrical characteristics 2 STL3N65M2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4: On/off-states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage (VGS = 0 V) ID = 1 mA IDSS Zero-gate voltage drain current (VGS = 0 V) VDS = 650 V 1 µA IGSS Gate body leakage current (VDS = 0 V) VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1 A 1.6 1.8 Ω Min. Typ. Max. Unit - 155 - pF - 8 - pF - 0.2 - pF V(BR)DSS 650 2 V Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. VDS = 100 V, f = 1 MHz, VGS= 0 V Output equivalent capacitance VGS = 0, VDS = 0 V to 520 V - 18 - pF Rg Gate input resistance f = 1 MHz gate DC bias = 0 test signal level = 20 mV open drain - 8.5 - Ω Qg Total gate charge - 5 - nC Qgs Gate-source charge - 1 - nC Qgd Gate-drain charge - 1.7 - nC (1) VDD = 520 V, ID = 2.3 A VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. Table 6: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Test conditions VDD = 325 V, ID = 1.15 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times") Fall time DocID027894 Rev 3 Min. Typ. Max. Unit - 6 - ns - 3.4 - ns - 17 - ns - 21.5 - ns STL3N65M2 Electrical characteristics Table 7: Source-drain diode Symbol Parameter Test conditions Min Typ. Max Unit Source-drain current - 2.3 A ISDM (1) Source-drain current (pulsed) - 9.2 A VSD(2) Forward on voltage ISD = 2.3 A, VGS = 0 - 1.6 V ISD = 2.3 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 184 ns - 0.7 µC - 7.6 A ISD = 2.3 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 300 ns - 1.1 µC - 7.4 A ISD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID027894 Rev 3 5/12 Electrical characteristics 2.1 STL3N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/12 DocID027894 Rev 3 STL3N65M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Output capacitance stored energy DocID027894 Rev 3 7/12 Test circuits 3 STL3N65M2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/12 DocID027894 Rev 3 Figure 19: Switching time waveform STL3N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 Power FLAT™ 3.3x3.3 HV package information Figure 20: PowerFLAT™ 3.3x3.3 HV package outline . DocID027894 Rev 3 9/12 Package information STL3N65M2 Table 8: PowerFLAT™ 3.3x3.3 HV package mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 b 0.25 0.30 0.40 D D2 3.30 2.50 2.65 e 0.65 E 3.30 2.75 E2 1.15 1.30 1.40 L 0.20 0.30 0.40 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 Figure 21: PowerFLAT™ 3.3x3.3 HV recommended footprint (dimensions are in mm) 8374983_footprint 10/12 DocID027894 Rev 3 STL3N65M2 5 Revision history Revision history Table 9: Document revision history Date Revision 19-May-2015 1 First release. 2 Updated title in cover page. Updated electrical characteristic section. Added electrical characteristic curves. Minor text changes. 3 Updated Section "Features". Updated Table 2: "Absolute maximum ratings" and Table 5: "Dynamic". Changed Figure 6: "Gate charge vs gate-source voltage". Document status promoted from preliminary to production data. 17-Dec-2015 12-Apr-2016 Changes DocID027894 Rev 3 11/12 STL3N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID027894 Rev 3