STL3NK40

STL3NK40 N-channel 400 V, 4.5 Ω typ., 0.43 A, SuperMESH™ Power MOSFET in a PowerFLAT™ 5x5 package Datasheet - production data Features Figure 1: Internal schematic diagram PTOT Order code VDS RDS(on) max. ID STL3NK40 400 V 5.5 Ω 0.43 A    2.5 W Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Applications  Switching applications Description This high voltage device is an N-channel Power MOSFET developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. Table 1: Device summary Order code Marking Package Packing STL3NK40 3NK40 PowerFLAT™ 5x5 Tape and reel February 2017 DocID16246 Rev 3 This is information on a product in full production. 1/13 www.st.com Contents STL3NK40 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/13 PowerFLAT™ 5x5 package information .......................................... 10 Revision history ............................................................................ 12 DocID16246 Rev 3 STL3NK40 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 400 V VDGR Drain-gate voltage (RGS = 20 kΩ) 400 V VGS Gate-source voltage ± 20 V Drain current (continuous) at Tpcb = 25 °C 0.43 A Drain current (continuous) at Tpcb = 100 °C 0.27 A Drain current (pulsed) 1.72 A Total dissipation at Tpcb = 25 °C 2.5 W Peak diode recovery voltage slope 4.5 V/ns - 55 to 150 °C Value Unit 50 °C/W ID(1) IDM(2) PTOT (1) dv/dt (3) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)When mounted on FR-4 board of 1 inch², 2 oz Cu (t < 100 s). (2)Pulse width limited by safe operating area. (3)I SD ≤ 0.43 A, di/dt ≤ 200 A/μs; VDD< 320 V. Table 3: Thermal data Symbol Rthj-pcb (1) Parameter Thermal resistance junction-pcb Notes: (1)When mounted on 1 inch² FR-4 board, 2 oz Cu (t < 100 s). Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or non-repetitive (pulse width limited by Tjmax.) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) DocID16246 Rev 3 Value Unit 0.43 A 60 mJ 3/13 Electrical characteristics 2 STL3NK40 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 400 Typ. Max. Unit V VGS = 0 V, VDS = 400 V 1 µA IDSS Zero-gate voltage drain current VGS = 0 V, VDS = 400 V TC = 125 °C(1) 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 1.6 2 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 0.22 A 4.5 5.5 Ω Min. Typ. Max. Unit - 128 200 pF - 16 30 pF - 4 6 pF - 12 - 8.7 13 nC - 0.9 - nC - 3.8 - nC Min. Typ. Max. Unit - 3 - ns - 4 - ns - 18 - ns - 16 - ns 0.8 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance RG Gate input resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge f = 1 MHz gate DC bias = 0 test signal level = 20 mV opendrain VDD = 320 V, ID = 1.4 A VGS = 0 to 10 V (see Figure 13: "Test circuit for gate charge behavior") pF Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 200 V, ID = 0.7 A, RG = 4.7 Ω VGS = 10 V (see Figure 12: "Test circuit for resistive load switching times" and Figure 17: "Switching time waveform") DocID16246 Rev 3 STL3NK40 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 0.43 A ISDM(1) Source-drain current (pulsed) - 1.72 A VSD(2) Forward on voltage - 1.2 V ISD Reverse recovery time trr Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 0.43 A, VGS = 0 V ISD = 1.4 A, di/dt = 100 A/µs,VDD = 20 V (see Figure 14: "Test circuit for inductive load switching and diode recovery times") ISD = 1.4 A, di/dt = 100 A/µs VDD = 20 V, Tj = 150 °C (see Figure 14: "Test circuit for inductive load switching and diode recovery times") - 166 ns - 300 nC - 3.6 A - 176 ns - 340 nC - 3.8 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID16246 Rev 3 5/13 Electrical characteristics 2.1 6/13 STL3NK40 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Static drain-source on-resistance Figure 7: Gate charge vs. gate-source voltage DocID16246 Rev 3 STL3NK40 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized V(BR)DSS vs. temperature Figure 10: Normalized gate threshold voltage vs. temperature Figure 11: Normalized on-resistance vs. temperature DocID16246 Rev 3 7/13 Test circuits 3 STL3NK40 Test circuits Figure 12: Test circuit for resistive load switching times Figure 13: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 Figure 14: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive waveform 8/13 DocID16246 Rev 3 Figure 15: Unclamped inductive load test circuit Figure 17: Switching time waveform STL3NK40 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID16246 Rev 3 9/13 Package information 4.1 STL3NK40 PowerFLAT™ 5x5 package information Figure 18: PowerFLAT™ 5x5 package outline 7 10 4 10 1 9 8 7 11 6 12 5 1 2 3 4 Pin 1 identification 10/13 DocID16246 Rev 3 8365434_A_type_S STL3NK40 Package information Table 9: PowerFLAT 5x5 package mechanical data mm Dim. Min. Typ. Max. A 0.80 1.0 A1 0.02 0.05 A2 b 0.25 0.30 D 0.50 5.00 D1 4.05 E 4.25 5.00 E1 0.64 0.79 E2 2.25 2.45 e L 1.27 0.45 0.75 Figure 19: PowerFLAT™ 5x5 recommended footprint (dimensions are in mm) 8365434_ A DocID16246 Rev 3 11/13 Revision history 5 STL3NK40 Revision history Table 10: Document revision history Date Revision 18-Sep-2009 1 First release. 29-Aug-2013 2 Updated: Section 4: Package mechanical data Minor text changes 3 Removed PowerFLAT™ 5x5 type C package information and cover image. Updated Table 6: "Dynamic" and Table 8: "Source-drain diode". Updated Section 2.1: "Electrical characteristics (curves)". Minor text changes. 20-Feb-2017 12/13 Changes DocID16246 Rev 3 STL3NK40 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID16246 Rev 3 13/13