STL40N10F7

STL40N10F7 Datasheet N-channel 100 V, 20 mΩ typ., 10 A STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Features PowerFLAT 5x6 D(5, 6, 7, 8) 8 7 5 6 Order code VDS RDS(on) max. ID PTOT STL40N10F7 100 V 24 mΩ 10 A 5W • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. AM15540v2 Product status link STL40N10F7 Product summary Order code STL40N10F7 Marking 40N10F7 Package PowerFLAT 5x6 Packing Tape and reel DS9684 - Rev 5 - February 2020 For further information contact your local STMicroelectronics sales office. www.st.com STL40N10F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 40 A Drain current (continuous) at TC = 100 °C 28 A Drain current (continuous) at Tpcb = 25 °C 10 A Drain current (continuous) at Tpcb = 100 °C 7 A IDM(2)(3) Drain current (pulsed) 40 A PTOT(1) Total power dissipation at TC = 25 °C 70 W PTOT(2) Total power dissipation at Tpcb = 25 °C 5 W ID(1) ID(2) Tstg TJ Storage temperature range Operating junction temperature range - 55 to 175 °C °C 1. This value is rated according to Rthj-c. 2. This value is rated according to Rthj-pcb. 3. Pulse width is limited by safe operating area. Table 2. Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case max. 2.08 Rthj-pcb(1) Thermal resistance junction-pcb max. 30 Unit °C/W 1. When mounted on a 1-inch² FR-4 board, 2oz Cu, t < 10 s. DS9684 - Rev 5 page 2/17 STL40N10F7 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On/Off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 250 μA, VGS = 0 V Min. Typ. Max. 100 Unit V VGS = 0 V, VDS = 100 V 10 µA VGS = 0 V, VDS = 100 V, TC = 125° C 100 μA Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 4.5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A 20 24 mΩ Min. Typ. Max. Unit - 1270 - pF - 290 - pF - 24 - pF - 19 - nC - 9 - nC - 4.5 - nC Min. Typ. Max. Unit - 12 - ns IDSS Zero gate voltage drain current IGSS 3 Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 32 A, VGS = 10 V (see Figure 13. Test circuit for gate charge behavior) Table 5. Switching times Symbol td(on) tr td(off) tf DS9684 - Rev 5 Parameter Turn-on delay time Test conditions VDD = 50 V, ID = 16 A, Rise time RG = 4.7 Ω, VGS = 10 V - 17.5 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times) - 22 - ns - 5.6 - ns Fall time page 3/17 STL40N10F7 Electrical characteristics Table 6. Source-drain diode Symbol ISD Parameter Test conditions Source-drain curren ISDM (1) Source-drain current (pulsed) VSD (2) Forward on voltage Min. Typ. ISD = 32 A, VGS = 0 V Max. Unit 32 A 128 A 1.1 V trr Reverse recovery time ISD = 32 A, di/dt = 100 A/µs, - 41 ns Qrr Reverse recovery charge VDD = 80 V, TJ = 150° C - 47 nC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times - 2.3 A IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS9684 - Rev 5 page 4/17 STL40N10F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GIPG270320141147SA ID (A) K GIPG270320141356SA d=0.5 0.2 10 is 1 0.05 0.02 10ms 100ms 1s 0.1 Tj=175°C Tpcb=25°C Single pulse 0.01 0.1 1 10 pcb 0.01 -2 Single pulse VDS(V) 10 10 -3 10 -5 Figure 3. Output characteristics AM16174v1 ID (A) 0.1 10 -1 ea ar (on) his DS nt xR i a on ati by m er Op ited m i L 9V VGS=10V 100 10 -4 10 -3 10 -2 10 -1 10 1 t p (s) 10 0 Figure 4. Transfer characteristics AM16175v1 ID (A) VDS= 4V 100 8V 80 7V 60 80 60 40 40 6V 20 20 0 5V 0 2 4 6 8 VDS(V) Figure 5. Gate charge vs gate-source voltage VGS (V) AM16176v1 VDD=30V ID=20A 12 0 0 4 2 6 8 10 VGS(V) Figure 6. Static drain-source on-resistance AM16177v1 RDS(on) (mΩ) 21.50 VGS=10V 21.00 10 20.50 8 20.00 6 19.50 4 19.00 2 0 DS9684 - Rev 5 18.50 0 5 10 15 20 Qg (nC) 18.00 0 10 20 30 ID(A) page 5/17 STL40N10F7 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations AM16178v1 C (pF) 1400 VGS(th) ID=250µA 1.2 Ciss 1200 1 1000 0.8 800 600 0.6 400 0.4 200 0 AM16179v1 (norm) 0 10 20 30 40 50 60 70 80 0.2 Coss Crss VDS(V) 0 -55 -30 -5 45 70 95 120 145 TJ(°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature AM16180v1 RDS(on) 20 AM16181v1 V(BR)DSS (norm) (norm) VGS=10V 1.04 2.0 ID=250µA 1.03 1.02 1.5 1.01 1.00 1.0 0.99 0.98 0.5 0.97 0.0 -55 -30 -5 20 45 70 95 120 0.96 -55 -30 -5 TJ(°C) 20 45 70 95 120 TJ(°C) Figure 11. Source-drain diode forward characteristics AM16182v1 VSD (V) TJ=-55°C 1.0 TJ=25°C 0.9 0.8 TJ=150°C 0.7 0.6 0.5 DS9684 - Rev 5 0 5 10 15 20 25 30 ISD(A) page 6/17 STL40N10F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9684 - Rev 5 page 7/17 STL40N10F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 type R package information Figure 18. PowerFLAT 5x6 type R package outline A0ER_8231817_Rev20 DS9684 - Rev 5 page 8/17 STL40N10F7 PowerFLAT 5x6 type R package information Table 7. PowerFLAT 5x6 type R mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS9684 - Rev 5 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.275 1.575 L 0.60 0.80 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 9/17 STL40N10F7 PowerFLAT 5x6 type R SUBCON package information 4.2 PowerFLAT 5x6 type R SUBCON package information Figure 19. PowerFLAT 5x6 type R SUBCON package outline 8472137_SUBCON_998G_REV4 8472137_SUBCON_998G_Type_R_REV4 DS9684 - Rev 5 page 10/17 STL40N10F7 PowerFLAT 5x6 type R SUBCON package information Table 8. PowerFLAT 5x6 type R SUBCON package mechanical data Dim. A mm Min. Typ. Max. 0.90 0.95 1.00 A1 b 0.02 0.35 b1 c 0.40 0.30 0.21 0.25 D 0.34 5.10 D1 4.80 4.90 5.00 D2 3.91 4.01 4.11 e 1.17 1.27 1.37 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.34 3.44 3.54 E4 0.15 0.25 0.35 E5 0.06 0.16 0.26 H 0.51 0.61 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 L2 DS9684 - Rev 5 0.45 0.10 P 1.00 1.10 1.20 θ 8° 10° 12° page 11/17 STL40N10F7 PowerFLAT 5x6 type R SUBCON package information Figure 20. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_20 DS9684 - Rev 5 page 12/17 STL40N10F7 PowerFLAT 5x6 packing information 4.3 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS9684 - Rev 5 page 13/17 STL40N10F7 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS9684 - Rev 5 page 14/17 STL40N10F7 Revision history Table 9. Document revision history Date Revision 20-May-2015 1 Changes First release. Document status promoted from preliminary to production data. Modified: VGS(th) values in tab 4. 02-Nov-2015 2 Updated the entire typical values in tab 5, tab 6 and tab7 Added Electrical characteristics (curves) Updated Figure 13, 14, 15 and 16 Minor text changes. Updated title, features and description. 18-Dec-2015 3 Updated Table 2: "Absolute maximum ratings" and Table 4: "On/Off states". Minor text changes. DS9684 - Rev 5 01-Feb 2016 4 21-Feb-2020 5 Updated Table 5: "Dynamic". Minor text changes. Updated Section 4 Package information. Minor text changes. page 15/17 STL40N10F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 type R package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 type R SUBCON package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DS9684 - Rev 5 page 16/17 STL40N10F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS9684 - Rev 5 page 17/17