STL42P6LLF6

STL42P6LLF6 Datasheet P-channel -60 V, 23 mΩ typ., -42 A STripFET F6 Power MOSFET in a PowerFLAT 5x6 package Features • • • • Order code V DS RDS(on) max ID STL42P6LLF6 -60 V 26 mΩ -42 A Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications D(5, 6, 7, 8) • Switching applications Description G(4) This device is a P-channel Power MOSFET developed using the STripFET F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. S(1, 2, 3) AM01475v4 Product status STL42P6LLF6 Product summary Order code STL42P6LLF6 Marking 42P6LLF6 Package PowerFLAT 5x6 Packing Tape and reel DS10014 - Rev 5 - November 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL42P6LLF6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage -60 V VGS Gate-source voltage ± 20 V ID (1) Drain current (continuous) at TC = 25 °C -42 A Drain current (continuous) at TC = 100 °C -30 A Drain current (pulsed) -168 A Drain current (continuous) at Tpcb= 25 °C -9 A Drain current (continuous) at Tpcb= 100 °C -6.6 A Drain current (pulsed) -36 A Total power dissipation at TC = 25 °C 100 W Total power dissipation at Tpcb= 25 °C 4.8 W -55 to 175 °C Value Unit Thermal resistance junction-case 1.5 °C/W Thermal resistance junction-pcb 31.3 °C/W ID (1) ID (1) (3) ID (2) ID (2) IDM (3) (2) PTOT (1) PTOT (2) Tstg Storage temperature range Tj Operating junction temperature range 1. The value is rated by Rthj-case. 2. The value is rated by Rthj-pcb. 3. Pulse width is limited by safe operating area. Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on FR-4 board of 1 inch², 2 Oz Cu, t < 10 s. DS10014 - Rev 5 page 2/17 STL42P6LLF6 Electrical characteristics 2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 3. Static Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = -250 µA Typ. -60 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = -250 µA RDS(on) Static drain-source onresistance VGS = 0 V, VDS = -60 V, TC = 125 Unit V VGS = 0 V, VDS = -60 V IDSS Max. °C(1) -1 -1 µA -10 µA ±100 nA -2.5 V VGS = -10 V, ID = -4.5 A 23 26 VGS = -4.5 V, ID= -4.5 A 28 34 Min. Typ. Max. Unit - 3780 - pF - 262 - pF - 170 - pF - 30 - nC - 10.8 - nC - 10.5 - nC - 1.7 - Ω Min. Typ. Max. Unit - 51.4 - ns - 39 - ns - 171 - ns - 21 - ns mΩ 1. Defined by design, not subject to production testing Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge RG Gate input resistance Test conditions VDS = -25 V, f = 1 MHz, VGS = 0 V VDD = -30 V, ID = -9 A, VGS = -4.5 V (see Figure 13. Gate charge test circuit) ID = 0 A, f = 1 MHz Table 5. Switching times Symbol td(on) tr td(off) tf DS10014 - Rev 5 Parameter Test conditions Turn-on delay time Rise time Turn-off-delay time Fall time VDD = -30 V, ID = -4.5 A, RG = 4.7 Ω, VGS = -10 V (see Figure 12. Switching times test circuit for resistive load) page 3/17 STL42P6LLF6 Electrical characteristics Table 6. Source-drain diode Symbol Min. Typ. Source-drain current - -42 A ISDM (1) Source-drain current (pulsed) - -168 A VSD (2) Forward on voltage VGS = 0 V, ISD = -9 A - trr Reverse recovery time - 34 ns Qrr Reverse recovery charge - 48 nC IRRM Reverse recovery current ISD = -9 A, di/dt = 100 A/µs, VDD = -4.8 V, Tj = 150 °C (see Figure 14. Test circuit for inductive load switching and diode recovery times) - -2.8 A ISD Parameter Test conditions Max. -1.1 Unit V 1. Pulse width limited by safe operating area 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5% DS10014 - Rev 5 page 4/17 STL42P6LLF6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Note: For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance K GIPG170220151600ALS GIPG170220151538ALS δ =0.5 102 101 δ =0.2 s ai re ) s a S(on D thi in x. R n a o ati by m er Op ited lim δ =0.1 100 μs 10-1 δ =0.05 1 ms Zth =K*Rthj-c δ=tp /Ƭ δ =0.02 10 ms δ =0.01 100 10-1 10-1 100 VDS (V) 101 Figure 3. Output characteristics ID (A) tp Single pulse Tj ≤ 175 °C Tc = 25 °C single pulse GIPG170220151647ALS 10-2 10-5 10-4 10-3 Ƭ tp (s) 10-2 Figure 4. Transfer characteristics ID (A) GIPG170220151710ALS VGS = 10, 9, 8, 7 V 120 120 VGS = 6 V 100 VDS = 8 V 100 VGS = 5 V 80 80 60 60 VGS = 4 V 40 40 20 20 VGS = 3 V 0 0 2 4 6 8 VDS (V) Figure 5. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GIPG180220151521ALS 0 0 2 4 6 8 10 VGS (V) Figure 6. Normalized V(BR)DSS vs temperature V (BR)DS S (norm.) GIPG180220151458ALS 1.10 1.1 ID = 250 μA 1.0 1.05 I D = 250 μA 0.9 1.00 0.8 0.95 0.7 0.6 -75 DS10014 - Rev 5 -25 25 75 125 TJ (°C) 0.90 -75 -25 25 75 125 T J (°C) page 5/17 STL42P6LLF6 Electrical characteristics (curves) Figure 7. Static drain-source on-resistance RDS(on) (mΩ) Figure 8. Normalized on-resistance vs. temperature RDS(ON) (norm.) GIPG180220150914ALS 25 GIPG180220151321ALS 2.0 24 VGS = 10 V 1.5 VGS = 10 V 23 1.0 22 0.5 21 20 0 2 4 6 8 0 -75 ID (A) Figure 9. Gate charge vs gate-source voltage VGS (V) -25 25 75 125 Tj (°C) Figure 10. Capacitance variations voltage GIPG180220151401ALS GIPG180220150932ALS C(pF) 12 Ciss 10 VDD = 30 V ID = 35 A 8 f = 1 MHz 103 6 4 2 0 Coss 0 10 20 30 40 50 60 70 102 Qg (nC ) Crss 0 10 20 30 40 50 VDS(V) Figure 11. Source-drain diode forward characteristics VSD (V) GIPG180220151604ALS 1.2 Tj = -55°C 1.1 Tj = 25°C 1.0 0.9 Tj = 175°C 0.8 0.7 0.6 0.5 0.4 0.3 0 DS10014 - Rev 5 5 10 15 20 25 30 35 ISD (A) page 6/17 STL42P6LLF6 Test circuits 3 Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load switching and diode recovery times DS10014 - Rev 5 page 7/17 STL42P6LLF6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS10014 - Rev 5 page 8/17 STL42P6LLF6 PowerFLAT 5x6 type C SUBCON package information 4.1 PowerFLAT 5x6 type C SUBCON package information Figure 15. PowerFLAT 5x6 type C SUBCON package outline 8472137_SUBCON_998G_REV4 8472137_SUBCON_998G_REV4 DS10014 - Rev 5 page 9/17 STL42P6LLF6 PowerFLAT 5x6 type C SUBCON package information Table 7. PowerFLAT 5x6 type C SUBCON package mechanical data Dim. A mm Min. Typ. Max. 0.90 0.95 1.00 A1 b 0.02 0.35 b1 c 0.40 0.30 0.21 0.25 D 0.34 5.10 D1 4.80 4.90 5.00 D2 4.01 4.21 4.31 e 1.17 1.27 1.37 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.54 3.64 3.74 E4 0.15 0.25 0.35 E5 0.26 0.36 0.46 H 0.51 0.61 0.71 K 0.95 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 L2 DS10014 - Rev 5 0.45 0.10 P 1.00 1.10 1.20 θ 8° 10° 12° page 10/17 STL42P6LLF6 PowerFLAT 5x6 type R package information 4.2 PowerFLAT 5x6 type R package information Figure 16. PowerFLAT 5x6 type R package outline A0ER_8231817_Rev15 DS10014 - Rev 5 page 11/17 STL42P6LLF6 PowerFLAT 5x6 type R package information Table 8. PowerFLAT 5x6 type R mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS10014 - Rev 5 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.275 1.575 L 0.60 0.80 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 12/17 STL42P6LLF6 PowerFLAT 5x6 type R package information Figure 17. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_18 DS10014 - Rev 5 page 13/17 STL42P6LLF6 PowerFLAT 5x6 packing information 4.3 PowerFLAT 5x6 packing information Figure 18. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 19. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS10014 - Rev 5 page 14/17 STL42P6LLF6 PowerFLAT 5x6 packing information Figure 20. PowerFLAT 5x6 reel DS10014 - Rev 5 page 15/17 STL42P6LLF6 Revision history Table 9. Document revision history Date Revision 28-Oct-2013 1 Changes First release. Modified: Figure 1: "Internal schematic diagram" 25-Aug-2014 2 Updated: Section 10: "Package mechanical data" Minor text changes In title description on cover page, changed 0.02 Ω to 0.023 Ω In features table on cover page, changed 0.028 Ω to 0.026 Ω Updated Table 2: Absolute maximum ratings Updated Table 4: Static – renamed table and updated Static drain-source onresistance values 24-Feb-2015 3 Updated Table 5: Dynamic – test conditions and all typical values Updated Table 6: Switching times – test conditions and all typical values Updated Table 7: Source-drain diode – test conditions and all typical values Added Section 2.2: Electrical characteristics (curves) Updated Section 4: Package mechanical data Minor text changes Updated title, features table and description on cover page Updated Table 2: "Absolute maximum ratings" 15-Nov-2016 4 Updated Table 4: "Static", Table 5: "Dynamic", Table 6: "Switchingtimes" and Table 7: "Source drain diode" Updated Figure 9: "Normalized on-resistance vs. temperature" Updated Section 4.1: "PowerFLAT™ 5x6 type R package information" Minor text changes 19-Nov-2019 DS10014 - Rev 5 5 Added: Section 4.1 PowerFLAT 5x6 type C SUBCON package information. Minor text changes. page 16/17 STL42P6LLF6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS10014 - Rev 5 page 17/17