STL45N65M5

STL45N65M5 N-channel 650 V, 0.075 Ω typ., 22.5 A MDmesh™ M5 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2 Order code VDS @ TJmax. RDS(on) max. ID PTOT STL45N65M5 710 V 0.086 Ω 22.5 A 160 W     1 Extremely low RDS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested PowerFLAT™ 8x8 HV Applications Figure 1: Internal schematic diagram  Switching applications Description This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Table 1: Device summary Order code Marking Package Packing STL45N65M5 45N65M5 PowerFLAT™ 8x8 HV Tape and reel October 2015 DocID023354 Rev 2 This is information on a product in full production. 1/16 www.st.com Contents STL45N65M5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 PowerFLAT 8x8 HV package information ....................................... 11 4.2 PowerFLAT 8x8 HV packing information ........................................ 13 Revision history ............................................................................ 15 DocID023354 Rev 2 STL45N65M5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 22.5 Drain current (continuous) at Tcase = 100 °C 18 Drain current (pulsed) 90 A Total dissipation at Tcase = 25 °C 160 W Drain current (continuous) at Tamb = 25 °C 3.8 Drain current (continuous) at Tamb = 100 °C 2.4 PTOT(3) Total dissipation at Tamb = 25 °C 2.8 W dv/dt(4) Peak diode recovery voltage slope 15 V/ns -55 to 150 °C Value Unit ID(1) IDM(1)(2) PTOT (1) ID(3) Tstg Storage temperature Tj Operating junction temperature A A Notes: (1) The value is rated according to Rthj-case and limited by package. (2) Pulse width limited by safe operating area. (3) When mounted on a 1-inch² FR-4, 2oz Cu board. (4) ISD ≤ 22.5 A, di/dt ≤ 400 A/μs, VDD = 400 V, VDS(peak) < V(BR)DSS. Table 3: Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case Thermal resistance junction-ambient 0.78 °C/W 45 Notes: (1) When mounted on a 1-inch² FR-4, 2oz Cu board. Table 4: Avalanche characteristics Symbol Parameter IAR(1) Avalanche current, repetitive or not repetitive EAS(2) Single pulse avalanche energy Value Unit 8 A 810 mJ Notes: (1) Pulse width limited by Tjmax. (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID023354 Rev 2 3/16 Electrical characteristics 2 STL45N65M5 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 650 V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, Tcase = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 14.5 A 0.075 0.086 Ω Min. Typ. Max. Unit - 3470 - - 82 - - 7 - - 79 - IDSS Zero gate voltage drain current IGSS 3 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance energy related pF VGS = 0 V, VDS = 0 to 520 V Co(tr)(2) Equivalent output capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge f = 1 MHz, ID = 0 A VDD = 520 V, ID = 17.5 A, VGS = 10 V (see Figure 16: "Gate charge test circuit") pF - 280 - - 2 - - 82 - - 18.5 - - 35 - Ω nC Notes: (1) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2) Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(v) Voltage delay time tr(v) Voltage rise time tf(i) Current fall time tc(off) 4/16 Parameter Crossing time Test conditions VDD = 400 V, ID = 22.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 20: "Switching time waveform") DocID023354 Rev 2 Min. Typ. Max. - 79.5 - - 11 - - 9.3 - - 16 - Unit ns STL45N65M5 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD(1) Source-drain current - 22.5 A ISDM(1)(2) Source-drain current (pulsed) - 90 A VSD(3) Forward on voltage VGS = 0 V, ISD = 22.5 A - 1.5 V trr Reverse recovery time - 346 ns Qrr Reverse recovery charge - 6 µC IRRM Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 17: " Test circuit for inductive load switching and diode recovery times") - 35 A ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V, TJ = 150 °C (see Figure 17: " Test circuit for inductive load switching and diode recovery times") - 432 ns - 8.4 µC - 39 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) The value is rated according to Rthj-case and limited by package. (2) Pulse width is limited by safe operating area. (3) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID023354 Rev 2 5/16 Electrical characteristics 2.1 STL45N65M5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 6/16 10 -4 10 -3 10 -2 Ƭ tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID023354 Rev 2 STL45N65M5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs. temperature Figure 12: Drain-source diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID023354 Rev 2 7/16 Electrical characteristics STL45N65M5 Figure 14: Switching loss vs. gate resistance(1) Notes: (1)E on 8/16 including reverse recovery of a SiC diode DocID023354 Rev 2 STL45N65M5 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF Figure 16: Gate charge test circuit VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 17: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 18: Unclamped inductive load test circuit A L D G S VD 3.3 µF B B B L=100µH 25Ω D + 1000 µF 2200 µF 3.3 µF VDD + VDD ID G RG S D.U.T. Vi GND1 D.U.T. Pw GND2 GND1 Figure 19: Unclamped inductive waveform GND2 AM15858v1 Figure 20: Switching time waveform Concept waveform for Inductive Load Turn-o ff Id 90%Vds 90%Id Tdelay-off -off Vgs 90%Vgs on Vgs(I(t)) )) 10%Vds 10%Id Vds Trise Tfall Tcross --over DocID023354 Rev 2 AM05540v2 9/16 Package information 4 STL45N65M5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID023354 Rev 2 STL45N65M5 4.1 Package information PowerFLAT 8x8 HV package information Figure 21: PowerFLAT™ 8x8 HV package outline 8222871_Rev_3_ A DocID023354 Rev 2 11/16 Package information STL45N65M5 Table 9: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 Figure 22: PowerFLAT™ 8x8 HV footprint All dimensions are in millimeters. 12/16 DocID023354 Rev 2 0.60 STL45N65M5 4.2 Package information PowerFLAT 8x8 HV packing information Figure 23: PowerFLAT™ 8x8 HV tape Figure 24: PowerFLAT™ 8x8 HV package orientation in carrier tape DocID023354 Rev 2 13/16 Package information STL45N65M5 Figure 25: PowerFLAT™ 8x8 HV reel 14/16 DocID023354 Rev 2 STL45N65M5 5 Revision history Revision history Table 10: Document revision history Date Revision 20-Sep-2012 1 First release. 2 Text and formatting changes throughout document Datasheet status changed from preliminary to production data In section Electrical ratings: - added table Avalanche characteristics In section Electrical characteristics: - renamed table Static (was On /off states) Updated section Test circuits Updated and renamed section Package information (was Package mechanical data) 09-Oct-2015 Changes DocID023354 Rev 2 15/16 STL45N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID023354 Rev 2