STL45P3LLH6

STL45P3LLH6 P-channel -30 V, 11 mΩ typ., -45 A STripFET™ H6 Power MOSFET in a PowerFLAT™ 5x6 package Datasheet - production data Features     Order code VDS RDS(on) max ID STL45P3LLH6 -30 V 13 mΩ -45 A Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Figure 1: Internal schematic diagram Switching applications Description This device is a P-channel Power MOSFET developed using the STripFET™ H6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Table 1: Device summary Order code Marking Package Packing STL45P3LLH6 45P3LLH6 PowerFLAT™ 5x6 Tape and reel April 2016 DocID025822 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STL45P3LLH6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 5x6 package information .......................................... 10 4.2 PowerFLAT™ 5x6 packaging information ....................................... 12 Revision history ............................................................................ 14 DocID025822 Rev 1 STL45P3LLH6 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage -30 V VGS Gate-source voltage ± 20 V (1) ID Drain current (continuous) at TC = 25 °C -45 A ID (1) Drain current (continuous) at TC = 100 °C -34 A ID (2) Drain current (continuous) at Tpcb = 25 °C -12 A ID (2) Drain current (continuous) at Tpcb = 100 °C -8.7 A IDM (1)(3) Drain current (pulsed) -180 A IDM (2)(3) Drain current (pulsed) -48 A PTOT (1) Total dissipation at Tc= 25 °C 75 W PTOT (2) Total dissipation at Tpcb= 25 °C 4.8 W - 55 to 175 °C Tstg Storage temperature range Tj Operating junction temperature range Notes: (1) (2) (3) The value is rated according to Rthj-c. This value is rated according to Rthj-pcb Pulse width is limited by safe operating area Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.00 °C/W Thermal resistance junction-pcb 31.3 °C/W Notes: (1) When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec DocID025822 Rev 1 3/15 Electrical characteristics 2 STL45P3LLH6 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0, ID = - 1 mA -30 Typ. Max. Unit V VGS = 0, VDS = -30 V -1 µA VGS = 0, VDS = -30 V, (1) TC = 125 °C -10 µA Gate-body leakage current VDS = 0, VGS = ± 20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = -250 µA RDS(on) Static drain-source on- resistance IDSS Zero gate voltage drain current IGSS -1 V VGS = -10 V, ID =-6 A 11 13 mΩ VGS = -4.5 V, ID = -6 A 16 19.5 mΩ Min. Typ. Max. Unit - 2615 - pF - 340 - pF - 235 - pF - 24 - nC - 9 - nC - 8 - nC Min. Typ. Max. Unit - 13.2 - ns - 93 - ns - 50 - ns - 18 - ns Notes: (1) Defined by design, not subject to production test. Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = -25 V, f = 1 MHz, VGS = 0 Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = -15 V, ID = -12 A, VGS = -4.5 V Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = -15 V, ID = -6 A, RG = 4.7 Ω, VGS = -10 V Fall time DocID025822 Rev 1 STL45P3LLH6 Electrical characteristics Table 7: Source drain diode Symbol (1) VSD trr Parameter Test conditions Forward on voltage ISD = -6 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = -6 A, di/dt = 100 A/µs VDD = -16 V, Tj=150 °C Min. Typ. - Max. Unit -1.1 V - 20 ns - 16 nC - -1.6 A Notes: (1) Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID025822 Rev 1 5/15 Electrical characteristics 2.2 STL45P3LLH6 Electrical characteristics (curves) Note: For the P-channel Power MOSFET, current and voltage polarities are reversed. 6/15 Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID025822 Rev 1 STL45P3LLH6 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID025822 Rev 1 7/15 Test circuits 3 STL45P3LLH6 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Test circuit for inductive load switching and diode recovery times 8/15 DocID025822 Rev 1 STL45P3LLH6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025822 Rev 1 9/15 Package information 4.1 STL45P3LLH6 PowerFLAT™ 5x6 package information Figure 16: PowerFLAT™ 5x6 type R package outline A0ER_8231817_Rev14 10/15 DocID025822 Rev 1 STL45P3LLH6 Package information Table 8: PowerFLAT™ 5x6 type R mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 C 5.80 6.00 6.20 5.20 5.40 D 5.00 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 4.45 1.27 E 5.95 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.275 1.575 L 0.60 0.80 L1 0.05 θ 6.15 6.35 0.15 0.25 0° 12° Figure 17: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_14 DocID025822 Rev 1 11/15 Package information 4.2 STL45P3LLH6 PowerFLAT™ 5x6 packaging information Figure 18: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 19: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID025822 Rev 1 STL45P3LLH6 Package information Figure 20: PowerFLAT™ 5x6 reel DocID025822 Rev 1 13/15 Revision history 5 STL45P3LLH6 Revision history Table 9: Document revision history 14/15 Date Revision 01-Apr-2016 1 Changes First release. DocID025822 Rev 1 STL45P3LLH6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID025822 Rev 1 15/15