STL4N80K5

STL4N80K5 N-channel 800 V, 2.1 Ω typ., 2.5 A MDMesh™ K5 Power MOSFET in a PowerFLAT™ 5x6 VHV package Datasheet − production data Features Order code VDS RDS(on)max. ID STL4N80K5 800 V 2.5 Ω 2.5 A • Industry’s lowest RDS(on) x area 1 • Industry’s best figure of merit (FoM) 2 • Ultra low gate charge 3 4 • 100% avalanche tested PowerFLAT™ 5x6 VHV • Zener protected Applications • Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 7 5 6 Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in onresistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(4) 1 S(1, 2, 3) 2 3 4 Top View AM15540v1 Table 1. Device summary Order code Marking Package Packaging STL4N80K5 4N80K5 PowerFLAT™ 5x6 VHV Tape and reel May 2015 This is information on a product in full production. DocID025574 Rev 2 1/17 www.st.com Contents STL4N80K5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 .............................................. 9 DocID025574 Rev 2 STL4N80K5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ± 30 V ID (1) Drain current (continuous) at TC = 25 °C 2.5 A ID (1) Drain current (continuous) at TC = 100 °C 1.55 A VGS IDM (2) Drain current (pulsed) 10 A PTOT(1) Total dissipation at TC = 25 °C 38 W IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 1 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 74.5 mJ Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns dv/dt (3) dv/dt (4) Tstg Tj Storage temperature °C - 55 to 150 Operating junction temperature °C 1. The value is limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 2.5 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS 4. VDS ≤ 640 V Table 3. Thermal data Symbol Value Unit Thermal resistance junction-case max 3.3 °C/W Rthj-amb(1) Thermal resistance junction-amb max 59 °C/W Rthj-case Parameter 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DocID025574 Rev 2 3/17 17 Electrical characteristics 2 STL4N80K5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage (VGS = 0) Test conditions ID = 1 mA IDSS Zero gate voltage VDS = 800 V drain current (VGS = 0) VDS = 800 V, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Min. Typ. Max. Unit 800 V 1 50 µA µA ± 10 µA 4 5 V 2.1 2.5 Ω Min. Typ. Max. Unit - 175 - pF - 20 - pF - 1 - pF - 26 - pF - 11 - pF f = 1 MHz, ID=0 - 15 - Ω VDD = 640 V, ID = 3 A, VGS = 10 V (see Figure 16) - 10.5 - nC - 2 - nC - 7.5 - nC VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onVGS = 10 V, ID = 1.5 A resistance 3 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VDS = 0 to 640 V, VGS = 0 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/17 DocID025574 Rev 2 STL4N80K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 400 V, ID = 1.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15), (see Figure 20) Rise time Turn-off delay time Fall time Min. Typ. Max Unit - 16.5 - ns - 15 - ns - 36 - ns - 21 - ns Min. Typ. Table 7. Source drain diode Symbol ISD ISDM VSD(1) trr Parameter Test conditions Max. Unit Source-drain current - 2.5 A Source-drain current (pulsed) - 10 A - 1.5 V ISD = 3 A, VGS = 0 Forward on voltage Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 3 A, di/dt = 100 A/µs VDD = 60 V (see Figure 17) ISD = 3 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 17) - 242 ns - 1.42 µC - 12 A - 373 ns - 1.98 µC - 10.5 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID=0 Min Typ. Max Unit 30 - - V The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and cost-effective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DocID025574 Rev 2 5/17 17 Electrical characteristics 2.1 STL4N80K5 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM17903v1 ID (A) ZthPowerFlat_5x6_27 K δ=0.5 0.2 n) 0.1 10 -1 100µs DS 1 (o Op Lim era ite tion d by in th m is ax ar R e a is 10µs 0.05 0.02 1ms 10ms 0.1 0.01 Single pulse Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 10 -3 10 -5 VDS(V) 100 c 10 -2 Figure 4. Output characteristics 10 -4 10 -3 10 0 10 -2 10 -1 10 1 tp(s) Figure 5. Transfer characteristics AM15989v1 ID (A) AM15990v1 ID (A) VGS=10, 11 V 5 VDS=20V 5 9V 4 4 3 3 8V 2 2 7V 1 1 6V 0 4 0 12 8 16 0 VDS(V) Figure 6. Gate charge vs gate-source voltage AM15991v1 VDS (V) VGS (V) VDD=640V ID=3A VDS 12 600 10 500 8 400 6 300 4 200 2 100 5 6 7 8 9 10 VGS(V) Figure 7. Static drain-source on-resistance *,3'59 5'6RQ ȍ 9*6 9     0 0 6/17 2 4 6 8 10 0 Qg(nC)  DocID025574 Rev 2       ,'$ STL4N80K5 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy *,3'59 & S) AM17904v1 Eoss (µJ)  &LVV  2  &RVV &UVV  I 0+]      Figure 10. Normalized gate threshold voltage vs. temperature AM15639v1 VGS(th) (norm) 0 0 9'69 ID=100µA VDS=VGS 200 400 600 800 VDS(V) Figure 11. Normalized on-resistance vs. temperature AM15640v1 RDS(on) (norm) VGS=10V ID=1.5 A 2.4 1 2 1.6 0.8 1.2 0.6 0.8 0.4 -50 50 0 100 TJ(°C) Figure 12. Drain-source diode forward characteristics AM15994v1 VSD (V) 1 0.4 -50 0 0.9 100 TJ(°C) Figure 13. Normalized VDS vs. temperature AM15642v1 VDS (norm) 1.1 TJ=-50°C 50 ID = 1mA 1.06 TJ=25°C 0.8 1.02 0.7 0.98 TJ=150°C 0.6 0.94 0.5 0.9 0.5 1 1.5 2 2.5 ISD(A) DocID025574 Rev 2 -50 0 50 100 TJ(°C) 7/17 17 Electrical characteristics STL4N80K5 Figure 14. Maximum avalanche energy vs. starting TJ AM15995v1 EAS (mJ) 60 40 20 0 0 8/17 40 80 120 TJ(°C) DocID025574 Rev 2 STL4N80K5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit 9'' 9 μF VDD VD VGS ,* &2167 9L 9 9*0$; RG Nȍ Q) 3.3 μF 2200 RL Nȍ  —) D.U.T. ȍ '87 Nȍ 9* PW Nȍ Nȍ 3: $0Y AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A Figure 18. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B S VD L=100μH 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform 9%5'66 WRQ 9' WGRQ WRII WU WGRII   ,'0    ,' 9'' WI 9'' $0Y 9*6  DocID025574 Rev 2  9'6  $0Y 9/17 17 Package mechanical data 4 STL4N80K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/17 DocID025574 Rev 2 STL4N80K5 Package mechanical data Figure 21. PowerFLAT™ 5x6 VHV 1 2 3 4 6 5 Bottom view Pin 1 identification 8 7 Side view Pin 1 identification 8 7 6 5 1 2 3 4 Top view 8368144_REV_B DocID025574 Rev 2 11/17 17 Package mechanical data STL4N80K5 Table 9. PowerFLAT™ 5x6 VHV mechanical data mm. DIM min. max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 2.40 2.50 2.60 e 12/17 typ. 0.50 1.27 L 0.50 0.55 0.60 K 2.60 2.70 2.80 DocID025574 Rev 2 STL4N80K5 Package mechanical data Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm) 8368144_REV_B_footprint DocID025574 Rev 2 13/17 17 Packaging mechanical data 5 STL4N80K5 Packaging mechanical data Figure 23. PowerFLAT™ 5x6 tape P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification 14/17 DocID025574 Rev 2 STL4N80K5 Packaging mechanical data Figure 25. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C DocID025574 Rev 2 15/17 17 Revision history 6 STL4N80K5 Revision history Table 10. Document revision history Date Revision 22-Nov-2013 1 First release. 2 Updated title, features and description in cover page. Updated 3: Test circuits. Updated Figure 7.: Static drain-source on-resistance, Figure 8.: Capacitance variations and Figure 14.: Maximum avalanche energy vs. starting TJ. Minor text changes. 14-May-2015 16/17 Changes DocID025574 Rev 2 STL4N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025574 Rev 2 17/17 17