STL50DN6F7

STL50DN6F7 Dual N-channel 60 V, 9 mΩ typ., 57 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 double island package Datasheet - production data Features     Order code VDS RDS(on) max. ID STL50DN6F7 60 V 11 mΩ 57 A Among the lowest RDS(on) on the market Excellent figure of merit (FoM) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Applications  Figure 1: Internal schematic diagram Switching applications Description This dual N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packaging STL50DN6F7 50DN6F7 PowerFLAT™ 5x6 double island Tape and reel November 2015 DocID028132 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STL50DN6F7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics(curve)......................................................... 5 3 Test circuits ..................................................................................... 7 4 Package information ....................................................................... 8 5 2/15 4.1 PowerFLAT 5x6 double island type R package information .............. 9 4.2 PowerFLAT™ 5x6 packing information ........................................... 12 Revision history ............................................................................ 14 DocID028132 Rev 2 STL50DN6F7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate source voltage ±20 V Drain current (continuous) at TC = 25 °C 57 Drain current (continuous) at TC = 100 °C 41 Drain current (pulsed) 228 Drain current (continuous) at Tpcb = 25 °C 15 Drain current(continuous) at Tpcb =100 °C 11 Drain current (pulsed) 60 ID(1) IDM(1)(2) ID(3) IDM(2)(3) PTOT Total dissipation at TC = 25 °C 62.5 Total dissipation at Tpcb = 25 °C 4.8 TJ Operating junction temperature Tstg Storage temperature -55 to 175 A A A A W °C Notes: (1)This value is rated according to Rthj-c (2)Pulse (3)This width limited by safe operating area. value is rated according to Rthj-pcb Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.4 °C/W Thermal resistance junction-pcb 31.3 °C/W Notes: (1)When mounted on FR-4 board of 1inc2, 2oz Cu, t < 10 sec DocID028132 Rev 2 3/15 Electrical characteristics 2 STL50DN6F7 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID= 1 mA IDSS Zero gate voltage drain current VDS= 60 V,VGS= 0 V IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 7.5 A Min. Typ. Max. Unit V 60 1 µA 100 nA 4 V 9 11 mΩ Min. Typ. Max. Unit 2 Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance - 1035 - pF Coss Output capacitance - 450 - pF Crss Reverse transfer capacitance - 53 - pF Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 30V, f = 1 MHz,VGS= 0 V VDD = 30 V, ID = 15 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 17 - nC - 5.7 - nC - 5.7 - nC Test conditions Min. Typ. Max. Unit VDD = 30V, ID =7.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" - 14.5 - ns - 15.3 - ns - 19.4 - ns - 8 - ns Min. Typ. Max. Unit 1.2 V Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Table 7: Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 15 A, VGS = 0 V - trr Reverse recovery time - 26.8 ns Qrr Reverse recovery charge - 14.2 nC IRRM Reverse recovery current ISD = 15 A, di/dt = 100 A/µs, VDD = 48 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 1.06 A Notes: (1)Pulsed: 4/15 pulse duration = 300 µs, duty cycle 1.5% DocID028132 Rev 2 STL50DN6F7 2.1 Electrical characteristics Electrical characteristics(curve) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028132 Rev 2 5/15 Electrical characteristics STL50DN6F7 Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics 6/15 DocID028132 Rev 2 STL50DN6F7 3 Test circuits Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID028132 Rev 2 7/15 Package information 4 STL50DN6F7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 8/15 DocID028132 Rev 2 STL50DN6F7 4.1 Package information PowerFLAT 5x6 double island type R package information Figure 19: PowerFLAT™ 5x6 double island type R package outline 8256945_D.I._typeR_R14 DocID028132 Rev 2 9/15 Package information STL50DN6F7 Table 8: PowerFLAT™ 5x6 double island type R mechanical data mm Dim. Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 0.50 5.20 5.40 D 5.00 D2 1.68 D3 4.80 5.00 5.20 D4 4.05 4.20 4.35 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 10/15 Typ. 1.88 1.27 E 5.95 6.15 6.35 E2 3.50 E3 0.20 E4 0.55 0.75 E5 0.08 0.28 E6 2.35 2.55 E7 0.40 0.60 E8 0.75 L 0.60 3.70 0.325 0.90 0.45 1.05 0.80 L1 0.05 K 1.275 1.575 θ 0° 12° DocID028132 Rev 2 0.15 0.25 STL50DN6F7 Package information Figure 20: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm) DocID028132 Rev 2 11/15 Package information 4.2 STL50DN6F7 PowerFLAT™ 5x6 packing information Figure 21: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID028132 Rev 2 STL50DN6F7 Package information Figure 23: PowerFLAT™ 5x6 reel DocID028132 Rev 2 13/15 Revision history 5 STL50DN6F7 Revision history Table 9: Document revision history Date Revision 17-Jul-2015 1 First release. 2 Document status promoted from preliminary to production data. Updated title and features in cover page. Updated Table 2: "Absolute maximum ratings" and Section 4: "Electrical characteristics". Added Section 4.1: "Electrical characteristics(curve)" Minor text changes. 13-Nov-2015 14/15 Changes DocID028132 Rev 2 STL50DN6F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028132 Rev 2 15/15