STL57N65M5

STL57N65M5 N-channel 650 V, 0.061 Ω typ., 22.5 A MDmesh™ M5 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2 Order code VDS @ TJmax RDS(on) max. ID STL57N65M5 710 V 0.069Ω 22.5 A     1 PowerFLAT™ 8x8 HV Extremely low RDS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications  Switching applications Figure 1: Internal schematic diagram Description Drain(5) This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Gate(1) Driver source (2) Power source (3, 4) NG1DS2PS34D5 Table 1: Device summary Order code Marking Package Packing STL57N65M5 57N65M5 PowerFLAT™ 8x8 HV Tape and reel October 2015 DocID022996 Rev 3 This is information on a product in full production. 1/16 www.st.com Contents STL57N65M5 Contents 1 Electrical ratings ............................................................................... 3 2 Electrical characteristics ................................................................. 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ...................................................................................... 9 4 Package information ...................................................................... 10 5 2/16 4.1 PowerFLAT™ 8x8 HV package information .................................... 11 4.2 PowerFLAT™ 8x8 HV packing information ..................................... 13 Revision history .............................................................................. 15 DocID022996 Rev 3 STL57N65M5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C 22.5 A ID(1) Drain current (continuous) at TC = 100 °C 22 A IDM(1)(2) Drain current (pulsed) 90 A ID(3) Drain current (continuous) at Tpcb = 25 °C 4.3 A ID(3) Drain current (continuous) at Tpcb = 100 °C 2.7 A PTOT (3) Total dissipation at Tpcb = 25 °C 2.8 W PTOT (1) Total dissipation at TC = 25 °C 189 W 9 A IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tj max) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 960 mJ Peak diode recovery voltage slope 15 V/ns dv/dt(4) Tstg Storage temperature Tj - 55 to 150 Max. operating junction temperature 150 °C Notes: (1) The value is rated according to Rthj-case rated and limited by package. (2) Pulse width limited by safe operating area. (3) When mounted on FR-4 board of 1 inch² , 2oz Cu. (4) ISD ≤ 22.5 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case max 0.66 °C/W Thermal resistance junction-pcb max 45 °C/W Notes: (1) When mounted on FR-4 board of 1 inch², 2oz Cu. DocID022996 Rev 3 3/16 Electrical characteristics 2 STL57N65M5 Electrical characteristics TC = 25 °C unless otherwise specified Table 4: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC= 125 °C 100 µA Gate-body leakage current VGS = ± 25 V, VDS= 0 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 17.5 A 0.061 0.069 Ω Min. Typ. Max. Unit - 4200 - pF - 100 - pF - 6 - pF - 97 - pF - 344 - pF f = 1 MHz, ID= 0 A - 1.4 - Ω VDD = 520 V, ID = 17.5 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") - 96 - nC - 24 - nC - 40 - nC 3 Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS= 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Equivalent output capacitance energy related Co(tr)(2) Equivalent output capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 V , VDS= 0 to 80% V(BR)DSS Notes: (1) Co(er) is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2) Co(tr) is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID022996 Rev 3 STL57N65M5 Electrical characteristics Table 6: Switching times Symbol Parameter td(V) Voltage delay time tr(V) Voltage rise time tf(i) Crossing fall time tC(off) Test conditions VDD = 400 V, ID = 22.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times"and Figure 19: "Switching time waveform") Crossing time Min. Typ. Max. Unit - 84 - ns - 10.8 - ns - 11 - ns - 16.5 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol Parameter Test conditions ISD(1) Source-drain current - 22.5 A ISDM(1),(2) Source-drain current (pulsed) - 90 A - 1.5 V VSD (3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM VGS = 0 V, ISD = 22.5 A - 378 ns - 7 µC Reverse recovery current - 37 A trr Reverse recovery time - 454 ns Qrr Reverse recovery charge - 9.5 µC IRRM Reverse recovery current - 42 A ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 22.5 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) The value is rated according to Rthj-case and limited by package. (2) Pulse width is limited by safe operating area (3) Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID022996 Rev 3 5/16 Electrical characteristics 2.1 STL57N65M5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 6/16 10 -4 10 -3 10 -2 Ƭ tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID022996 Rev 3 STL57N65M5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature f =1MHz Figure 10: Normalized on-resistance vs temperature Figure 12: Output capacitance stored energy DocID022996 Rev 3 Figure 11: Normalized V(BR)DSS vs temperature Figure 13: Switching losses vs gate resistance 7/16 Electrical characteristics The previous figure Eon includes reverse recovery of a SiC diode. 8/16 DocID022996 Rev 3 STL57N65M5 STL57N65M5 3 Test circuits Test circuits Figure 14: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF Figure 15: Gate charge test circuit VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 17: Unclamped inductive load test circuit L A D G S 25Ω VD 3.3 µF B B B L=100µH D + 1000 µF 2200 µF 3.3 µF VDD + VDD ID G RG S D.U.T. Vi D.U.T. Pw GND1 GND2 GND1 Figure 18: Unclamped inductive waveform GND2 AM15858v1 Figure 19: Switching time waveform Concept waveform for Inductive Load Turn-o ff Id 90%Vds 90%Id Tdelay-off -off Vgs 90%Vgs on Vgs(I(t)) )) 10%Vds 10%Id Vds Trise Tfall Tcross --over DocID022996 Rev 3 AM05540v2 9/16 Package information 4 STL57N65M5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID022996 Rev 3 STL57N65M5 4.1 Package information PowerFLAT™ 8x8 HV package information Figure 20: PowerFLAT™ 8x8 HV drawing 8222871_Rev_3_ A DocID022996 Rev 3 11/16 Package information STL57N65M5 Table 8: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 Figure 21: PowerFLAT™ 8x8 HV drawing All dimensions are in millimeters. 12/16 DocID022996 Rev 3 0.60 STL57N65M5 4.2 Package information PowerFLAT™ 8x8 HV packing information Figure 22: PowerFLAT™ 8x8 HV tape Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape DocID022996 Rev 3 13/16 Package information STL57N65M5 Figure 24: PowerFLAT™ 8x8 HV reel 14/16 DocID022996 Rev 3 STL57N65M5 5 Revision history Revision history Table 9: Document revision history Date Revisi on 14-May-2012 1 First release. 2 -Modified ID value and note 1 on first page -Modified: ID, PTOT, IAR values, and note1, 4 on Table 2 -Modified: Rthj-case value on Table 3 -Modified: RDS(on) on Table 4 -Modified: typical values on Table 5 and 6 -Modified: typical and max values on Table 7 -Inserted: Section 2.1: Electrical characteristics (curves) -Document staus promoted from preliminary data to production data. 3 Updated title, features and description Text and formatting changes throughout document. Updated Section 1: "Electrical ratings"and Section 2: "Electrical characteristics" Changes according to PCN9187: Updated package silhouette and figure Figure 1: "Internal schematic diagram" on cover page. Updated Section 4.1: "PowerFLAT™ 8x8 HV package information". 25-Jan-2013 09-Oct-2015 Changes DocID022996 Rev 3 15/16 STL57N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID022996 Rev 3