STL62P3LLH6

STL62P3LLH6 P-channel -30 V, 9 mΩ typ., -62 A STripFET™ H6 Power MOSFET in a PowerFLAT 5x6 package Datasheet - production data Features     Order code VDS RDS(on) max ID STL62P3LLH6 -30 V 10.5 mΩ -62 A Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Figure 1: Internal schematic diagram Switching applications Description This device is a P-channel Power MOSFET developed using the STripFET™ H6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Table 1: Device summary Order code Marking Package Packing STL62P3LLH6 62P3LLH6 PowerFLATTM 5x6 Tape and reel . October 2016 DocID025836 Rev 6 This is information on a product in full production. 1/16 www.st.com Contents STL62P3LLH6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 PowerFLAT 5x6 type R package information .................................. 11 5 Packing information ...................................................................... 13 6 Revision history ............................................................................ 15 2/16 DocID025836 Rev 6 STL62P3LLH6 1 Electrical ratings Electrical ratings Table 3: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ± 20 V ID(1) Drain current (continuous) at TC = 25 °C -62 A ID (1) Drain current (continuous) at TC = 100 °C -44 A ID(2) Drain current (continuous) at Tpcb = 25 °C -14 A ID Drain current (continuous) at Tpcb = 100 °C -9.5 A Drain current (pulsed) -248 A (2) ID(1)(2) IDM Drain current (pulsed) -56 A PTOT (1) Total dissipation at TC = 25 °C 100 W PTOT (2) Total dissipation at Tpcb = 25 °C 4.8 W - 55 to 175 °C Value Unit (2)(3) Tstg Tj Storage temperature range Operating junction temperature range Notes: (1)The value is rated according to Rthj-c. (2)This value is rated according to Rthj-pcb. (3)Pulse width is limited by safe operating area. Table 4: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 1.5 °C/W Rthj-pcb(1) Thermal resistance junction-pcb, single operation 31.3 °C/W Notes: (1)When mounted on FR-4 board of 1inch², 2oz Cu DocID025836 Rev 6 3/16 Electrical characteristics 2 STL62P3LLH6 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = -250 µA Min. Typ. Max. -30 Unit V VGS = 0 V, VDS = -30 V -1 µA VGS = 0 V, VDS = -30 V, TC = 125 °C(1) -10 µA Gate-body leakage current VDS = 0 V, VGS = ± 20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = -250 µA RDS(on) Static drain-source onresistance VGS = -10 V, ID = -7 A 9 10.5 mΩ VGS = -4.5 V, ID = -7 A 13 16 mΩ Min. Typ. Max. Unit - 3350 - pF VDS = -25 V, f = 1 MHz, VGS = 0 V - 414 - pF - 287 - pF VDD = -15 V, ID = -14 A, VGS = -4.5 V (see Figure 14: "Gate charge test circuit" ) - 33 - nC - 14 - nC - 11 - nC Min. Typ. Max. Unit - 12.8 - ns - 112 - ns - 61 - ns - 45 - ns IDSS Zero gate voltage drain current IGSS -1 V Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions Table 7: Switching times Symbol td(on) tr td(off) tf 4/16 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = -15 V, ID = -7 A, RG = 4.7 Ω, VGS = -10 V (see Figure 13: "Switching times test circuit for resistive load" ) DocID025836 Rev 6 STL62P3LLH6 Electrical characteristics Table 8: Source drain diode Symbol VSD(1) Parameter Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions ISD = -7 A, VGS = 0 V ISD = -24 A, di/dt = 100 A/µs VDD = -16 V, Tj=150 °C (see Figure 15: "Source-drain diode forward characteristics") Min. Typ. - Max. Unit -1.1 V - 25.2 ns - 17.4 nC - 1.4 A Notes: (1)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID025836 Rev 6 5/16 Electrical characteristics 2.1 STL62P3LLH6 Electrical characteristics (curves) Note: For the P-channel Power MOSFET, current and voltage polarities are reversed. Figure 2: Safe operating area GIPG010920141456 RV ID (A) 10 0.2 100 µs 0.1 1ms 10 ms 1 0.05 0.02 0.01 0.1 Tj=175°C Tc=25°C Single pulse 0.01 0.1 1 VDS(V) 10 Figure 5: Transfer characteristics Figure 4: Output characteristics GIPG280820141409MT ID(A) 8V V GS = 9,10V 200 7V 6V 150 5V 100 4V 50 3V 0 6/16 GIPG030920141359MT δ s ai are (on) his DS nt xR i n tio ma era by Op ited m i L 100 Figure 3: Thermal impedance 0 2 4 6 8 V DS(V) DocID025836 Rev 6 STL62P3LLH6 Electrical characteristics Figure 7: Static drain-source on-resistance Figure 6: Gate charge vs gate-source voltage R DS(on) (mΩ) GIPG030920141408M T VGS (V) VDD=15V ID=14A 12 GIPG020920141051MT 9.40 V GS=10V 9.30 10 9.20 9.10 8 9.00 6 8.90 8.80 4 8.70 2 0 8.60 0 20 40 8.50 Qg(nC) 60 Figure 8: Capacitance variations 0 4 2 6 8 10 12 14 ID(A) Figure 9: Normalized gate threshold voltage vs temperature GIPG020920141145MT V GS(th) (norm) ID=250µ A 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 -75 Figure 10: Normalized on-resistance vs temperature 125 175 T J(°C) GIPG020920141202MT ID=1m A 1.06 1.4 1.04 1.2 1.02 1 1 0.98 0.8 0.96 0.6 0.94 0.4 -75 75 V (BR)DSS (norm) 1.08 V GS=10V 1.6 25 Figure 11: Normalized V(BR)DSS vs temperature GIPG020920141154MT R DS(on) (norm) -25 -25 25 75 125 175 T J(°C) DocID025836 Rev 6 0.92 -75 -25 25 75 125 175 7/16 T J(°C) Electrical characteristics STL62P3LLH6 Figure 12: Source-drain diode forward characteristics GIPG020920141229MT V SD(V) 1 T J=-55°C 0.9 0.8 0.7 T J=25°C T J=175°C 0.6 0.5 0.4 8/16 0 2 4 6 8 10 DocID025836 Rev 6 12 14 16 18 ISD(A) STL62P3LLH6 3 Test circuits Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Source-drain diode forward characteristics DocID025836 Rev 6 9/16 Package information 4 STL62P3LLH6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID025836 Rev 6 STL62P3LLH6 4.1 Package information PowerFLAT 5x6 type R package information Figure 16: PowerFLAT™ 5x6 type R package outline A0ER_8231817_Rev14 DocID025836 Rev 6 11/16 Package information STL62P3LLH6 Table 9: PowerFLAT™ 5x6 type R mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 C 5.80 6.00 6.20 5.20 5.40 D 5.00 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 4.45 1.27 E 5.95 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.275 1.575 L 0.60 0.80 L1 0.05 θ 6.15 6.35 0.15 0.25 0° 12° Figure 17: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_14 12/16 DocID025836 Rev 6 STL62P3LLH6 5 Packing information Packing information Figure 18: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 19: PowerFLAT™ 5x6 package orientation in carrier tape DocID025836 Rev 6 13/16 Packing information STL62P3LLH6 Figure 20: PowerFLAT™ 5x6 reel 14/16 DocID025836 Rev 6 STL62P3LLH6 6 Revision history Revision history Table 10: Document revision history Date Revision Changes 30-May-2014 1 First release. 05-Sep-2014 2 Updated the title, the features and the description in cover page. Updated Section 7: "Electrical characteristics". Minor text changes. 11-Sep-2014 3 Updated Figure 6: "Gate charge vs gate-source voltage". Minor text changes. 16-Dec-2014 4 Document status promoted from preliminary to production data. 07-Apr-2015 5 Updated Section 7.1: "Electrical characteristics (curves)" and Section 9.1: "PowerFLAT 5x6 type R package information" 20-Oct-2016 6 Updated Figure 2: "Safe operating area". Minor text changes. DocID025836 Rev 6 15/16 STL62P3LLH6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 16/16 DocID025836 Rev 6