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STL6N3LLH6

STL6N3LLH6

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    PowerWDFN6

  • 描述:

    MOSFET N-CH 30V PWRFLT2X2

  • 数据手册
  • 价格&库存
STL6N3LLH6 数据手册
STL6N3LLH6 N-channel 30 V, 0.021 Ω typ., 6 A STripFET™ H6 Power MOSFET in a PowerFLAT™ 2x2 package Datasheet - production data Features Order code VDS 1 2 3 STL6N3LLH6 30 V RDS(on) max ID PTOT 0.025Ω (VGS=10 V) 6 A 2.4 W 0.04Ω (VGS= 4.5 V) • Very low on-resistance 6 1 • Very low gate charge 5 2 • High avalanche ruggedness 4 3 • Low gate drive power loss PowerFLAT™ 2x2 Applications • Switching applications Figure 1. Internal schematic diagram 2(D) 1(D) D 6(D) Description 3(G) This device is an N-channel Power MOSFET developed using the STripFET™ H6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. S 5(D) 4(S) AM11269v1 Table 1. Device summary Order code Marking Package Packaging STL6N3LLH6 STG1 PowerFLAT™ 2x2 Tape and reel October 2015 This is information on a product in full production. DocID023231 Rev 3 1/13 www.st.com Contents STL6N3LLH6 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 DocID023231 Rev 3 STL6N3LLH6 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ± 20 V Drain current (continuous) at TC = 25 °C 13 A ID (1) ID(1) Drain current (continuous) at TC = 100 °C 8.2 A (1)(2) Drain current (pulsed) 52 A ID (3) Drain current (continuous) at Tpcb = 25 °C 6 A ID (3) Drain current (continuous) at Tpcb = 100 °C 3.75 A Drain current (pulsed) 24 A IDM IDM(2)(3) PTOT (1) Total dissipation at Tc = 25 °C 7.8 PTOT(3) Total dissipation at Tpcb = 25 °C 2.4 TJ Operating junction temperature Tstg Storage temperature W -55 to 150 °C Value Unit Thermal resistance junction-pcb 52 ºC/W Thermal resistance junction-case max 16 ºC/W 1. This value is rated according to Rthj-case 2. Pulse width limited by safe operating area 3. This value is rated according to Rthj-pcb Table 3. Thermal resistance Symbol Rthj-pcb (1) Rthj-case Parameter 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec DocID023231 Rev 3 3/13 13 Electrical characteristics 2 STL6N3LLH6 Electrical characteristics (TCASE = 25 °C unless otherwise specified). Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS = 0 V Min. Typ. Max. 30 Unit V VDS = 30 V, VGS = 0 1 µA VDS = 30 V, TC = 125°C (VGS = 0) 10 µA ±100 nA IDSS Zero gate voltage drain current IGSS Gate body leakage current VGS = ±20 V, (VDS = 0) VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source on-resistance VGS = 10 V, ID = 3 A 0.021 0.025 Ω RDS(on) VGS = 4.5 V, ID = 3 A 0.032 0.04 Ω Min. Typ. Max. Unit - 283 - - 61 - - 31 - - 3.6 - - 1.5 - - 1.1 - 1 V Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 24 V, f=1 MHz, (VGS= 0) VDD = 15 V, ID = 6 A VGS = 4.5 V (see Figure 14.: Gate charge test circuit) pF nC Table 6. Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD= 10 V, ID = 6 A, RG = 4.7 Ω, VGS = 4.5 V (see Figure 13.: Switching times test circuit for resistive load) - 4.8 - - 11.2 - - 9.4 - - 5.4 - DocID023231 Rev 3 Unit ns STL6N3LLH6 Electrical characteristics Table 7. Source drain diode Symbol VSD(1) Parameter Test conditions Min. Typ. Max. Unit 1.1 V Forward on voltage ISD = 6 A, VGS = 0 V - trr Reverse recovery time - 10.6 ns Qrr Reverse recovery charge - 2.8 nC IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs, VDD= 16 V, TJ = 150 °C - 0.5 A 1. Pulsed: pulse duration=300µs, duty cycle 1.5% DocID023231 Rev 3 5/13 13 Electrical characteristics 2.1 STL6N3LLH6 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM15374v1 ID (A) AM15375v1 on ) δ=0.5 D S( O Li per m at ite io d ni by n m this ax a R rea is K 10 0.2 0.1 1ms 1 0.05 Zthj-pcb=K*Rthj-c 0.02 10ms Tj=150°C Tc=25°C 0.01 1s Single pulse 0.1 0.1 10 -1 VDS(V) 10 1 Figure 4. Output characteristics 10 10 -5 10 -4 10-3 10 -2 10 -1 tp(s) Figure 5. Transfer characteristics AM15361v1 ID (A) Single pulse -2 VGS=6, 7, 8, 9, 10V AM15369v1 ID (A) 30 VDS=2V 5V 25 30 4V 20 20 15 10 10 3V 5 0 0 2V 1 2 4 3 Figure 6. Gate charge vs gate-source voltage AM15358v1 VGS (V) VDD=15V 10 0 0 VDS(V) 1 2 3 4 5 6 7 VGS(V) Figure 7. Static drain-source on-resistance RDS(on) (mΩ) ID=6A AM15372v1 VGS= 10 V 40 35 8 30 25 6 20 4 15 10 2 5 0 0 0 6/13 2 4 6 Qg(nC) DocID023231 Rev 3 0 2 4 6 8 10 ID(A) STL6N3LLH6 Electrical characteristics Figure 8. Capacitance variations Figure 9. Normalized on-resistance vs temperature AM15370v1 C (pF) f= 1 MHz Ciss 1.6 1.4 100 Coss AM15360v1 RDS(on) (norm) 1.8 ID= 3 A VGS= 10 V 1.2 Crss 1 0.8 10 0.6 0.4 0.2 1 0 20 10 VDS(V) 00 -55 -30 -5 20 45 70 95 120 145 TJ(°C) Figure 10. Normalized gate threshold voltage vs Figure 11. Normalized V(BR)DSS vs temperature temperature AM15368v1 VGS(th) (norm) 1.2 1.15 ID =250 µA AM15364v1 V(BR)DSS ID = 250 μA 1.1 1 1.05 0.8 1 0.6 0.95 0.4 0.9 0.2 0.85 0 -55 -30 -5 20 45 70 95 120 145 TJ(°C) 0.8 -55 -30 -5 20 45 70 95 120 TJ(°C) Figure 12. Source-drain diode forward characteristics AM15365v1 VSD (V) TJ=-55°C 1 0.9 0.8 TJ=25°C 0.7 0.6 TJ=150°C 0.5 0.4 0.3 0.2 0 2 4 6 8 10 ISD(A) DocID023231 Rev 3 7/13 13 Test circuits 3 STL6N3LLH6 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VDD VD VGS RG IG=CONST Vi=20V=VGMAX 2200 mF D.U.T. 100Ω D.U.T. 2.7kΩ VG PW 47kΩ 1kΩ PW AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A Figure 16. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform ton V(BR)DSS toff tr VD tdoff tf td(on) 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/13 0 DocID023231 Rev 3 10% AM01473v1 STL6N3LLH6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID023231 Rev 3 9/13 13 Package information STL6N3LLH6 Figure 19. PowerFLAT™ 2 x 2 package outline 8368575_REV_C 10/13 DocID023231 Rev 3 STL6N3LLH6 Package information Table 8. PowerFLAT™ 2 x 2 package mechanical data mm. Dim. Min. Typ. Max. A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 b 0.25 0.30 0.35 D 1.90 2.00 2.10 E 1.90 2.00 2.10 D2 0.90 1.00 1.10 E2 0.80 0.90 1.00 e 0.55 0.65 0.75 K 0.15 0.25 0.35 K1 0.20 0.30 0.40 K2 0.25 0.35 0.45 L 0.20 0.25 0.30 L1 0.65 0.75 0.85 Table 9. PowerFLAT™ 2 x 2 recommended footprint (dimensions in millimeters) Footprint DocID023231 Rev 3 11/13 13 Revision history 5 STL6N3LLH6 Revision history Table 10. Document revision history Date Revision 25-May-2012 1 First release 2 – – – – Added Section 2.1: Electrical characteristics (curves). RDS(on) values (typ. and max.) updated Typical values updated in Table 5, 6 and 7 Minor text changes. 3 – – – – – Updated title and description in cover page. Datasheet promoted from preliminary data to production data. Updated Table 2, Table 4, Table 5 and Table 7. Updated Figure 6 and Figure 7. Minor text changes. 11-Oct-2012 21-Oct-2015 12/13 Changes DocID023231 Rev 3 STL6N3LLH6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023231 Rev 3 13/13 13
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