STL75NH3LL
N-channel 30 V, 0.004 Ω, 20 A, PowerFLAT™ (6x5)
ultra low gate charge STripFET™ Power MOSFET
Features
Type
RDS(on)
max
VDSS
ID
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Description
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STL75NH3LL
30V
< 0.0057 Ω 20 A (1)
1. This value is according Rthj-pcb
■
Improved die-to-footprint ratio
■
Very low profile package (1mm max)
■
Very low thermal resistance
■
Very low gate charge
■
Low threshold device
■
Switching applications
PowerFLAT™(6x5)
Figure 1.
Internal schematic diagram
This application specific Power MOSFET is the
latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The chip-scaled PowerFLAT™
package allows a significant board space saving,
still boosting the performance.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL75NH3LL
L75NH3LL
PowerFLAT™ (6 x 5)
Tape and reel
June 2008
Rev 1
1/12
www.st.com
12
Contents
STL75NH3LL
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
3
Electrical characteristics (curves)
Test circuits
............................ 6
.............................................. 8
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4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STL75NH3LL
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
V
± 16
V
Drain current (continuous) at TC = 25 °C
75
A
ID (1)
Drain current (continuous) at TC = 100 °C
47
A
ID(2)
Drain current (continuous) at TC = 25 °C
20
Drain current (continuous) at TC = 100 °C
12.5
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID
ID
(1)
(2)
IDM
(3)
80
PTOT(1)
Total dissipation at TC = 25 °C
PTOT(2)
Total dissipation at TC = 25 °C
Derating factor
ro
Operating junction temperature
Storage temperature
Tj
Tstg
1. The value is rated according Rthj-C
2. This value is according Rthj-pcb
)
(s
3. Pulse width limited by safe operating area
Table 3.
od
Symbol
Pr
Rthj-case
Rthj-pcb
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Thermal resistance
(1)
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-
Parameter
(s)
Thermal resistance junction-case (drain) max
ct
Thermal resistance junction-pcb max
du
1. When mounted on FR-4 board of
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1inch2,
A
ct
du
Drain current (pulsed)
(s)
60
4
A
A
W
)
s
t(
W
uc
0.03
od
W/°C
-55 to 150
°C
Value
Unit
2.08
°C/W
31.3
°C/W
2 oz Cu, t < 10 sec
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3/12
Electrical characteristics
2
STL75NH3LL
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
Test conditions
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,@125 °C
IGSS
Gate body leakage current
(VDS = 0)
VDS = ± 16 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 10 A
VGS= 4.5 V, ID= 10 A
V(BR)DSS
Min.
Typ.
Max.
30
Unit
V
1
10
µA
µA
±100
nA
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Table 5.
Symbol
4/12
1
V
0.004
0.005
0.0057
0.0075
Typ.
Max.
Ω
Ω
Dynamic
Parameter
Test conditions
Min.
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f = 1 MHz,
VGS=0
1810
565
41
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15 V, ID = 20 A,
VGS = 4.5 V
(see Figure 14)
18
4.8
5.3
24
nC
nC
nC
RG
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
1.5
3
Ω
0.5
Unit
pF
pF
pF
STL75NH3LL
Electrical characteristics
Table 6.
Symbol
Switching times
Parameter
Test conditions
Min.
Typ.
Max. Unit
td(on)
tr
Turn-on delay time
Rise time
VDD = 15 V, ID = 10 A
RG= 4.7 Ω, VGS= 10 V
(see Figure 16)
8
65
ns
ns
td(off)
tf
Turn-off delay time
Fall time
VDD = 15 V, ID = 10 A
RG= 4.7 Ω, VGS= 10 V
(see Figure 16)
30
20
ns
ns
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Table 7.
Symbol
ISD
ISDM
VSD (1)
trr
Qrr
IRRM
Source drain diode
Parameter
Test conditions
Min
Typ.
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 20 A, VGS = 0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 20 A,
di/dt = 100 A/µs
VDD = 20 V
(see Figure 15)
22
32
1.9
Max
Unit
20
80
A
A
1.3
V
ns
nC
A
1. Pulsed: Pulse duration = 300µs, duty cycle 1.5%
5/12
Electrical characteristics
STL75NH3LL
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
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Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
6/12
STL75NH3LL
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
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Figure 10. Normalized gate threshold voltage
vs temperature
Figure 11. Normalized on resistance vs
temperature
Figure 12. Source-drain diode forward
characteristics
7/12
Test circuits
3
STL75NH3LL
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
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Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/12
Figure 18. Switching time waveform
STL75NH3LL
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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9/12
Package mechanical data
STL75NH3LL
PowerFLAT™ (6x5) MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
0.80
0.83
0.93
0.031
0.032
0.036
A1
0.02
0.05
0.0007
0.0019
A3
0.20
A
b
0.35
0.40
0.007
0.47
0.013
0.015
0.018
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D
5.00
0.196
D1
4.75
0.187
D2
4.15
E
4.25
5.75
3.48
3.53
E4
2.58
2.63
2.68
0.135
1.27
0.70
0.80
0.167
0.226
3.43
e
0.165
0.236
E2
L
0.163
6.00
E1
10/12
4.20
0.137
0.139
0.103
0.105
0.050
0.90
0.027
0.031
0.035
STL75NH3LL
5
Revision history
Revision history
Table 8.
Document revision history
Date
Revision
12-Jun-2008
1
Changes
First release
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11/12
STL75NH3LL
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