STL7DN6LF3

STL7DN6LF3 Automotive-grade dual N-channel 60 V, 35 mΩ typ., 6.5 A STripFET™ F3 Power MOSFET in PowerFLAT™ 5x6 double island Datasheet - production data Features Order code VDS RDS(on) max ID STL7DN6LF3 60 V 43 mΩ 6.5 A • Designed for automotive application and AEC-Q101 qualified 1 2 3 4 • Logic level VGS(th) PowerFLAT™ 5x6 double island • 175 °C junction temperature • 100% avalanche rated • Wettable flank package Figure 1. Internal schematic diagram Applications • Switching applications Description This device is a dual N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. Top view Table 1. Device summary Order code Marking Package Packaging STL7DN6LF3 7DN6LF3 PowerFLAT™ 5x6 double island(1) Tape and reel 1. For wettable flank option, please contact ST sale offices. February 2015 This is information on a product in full production. DocID023010 Rev 4 1/18 www.st.com Contents STL7DN6LF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 .............................................. 8 DocID023010 Rev 4 STL7DN6LF3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V (1),(2) Drain current (continuous) at TC = 25 °C 20 A ID (1) Drain current (continuous) at TC = 100 °C 16 A ID (4) Drain current (continuous) at Tpcb = 25 °C 6.5 A ID (4) Drain current (continuous) at Tpcb=100 °C 4.6 A Drain current (pulsed) 26 A Total dissipation at TC = 25°C 52 W Total dissipation at Tpcb = 25°C 4.3 W Not-repetitive avalanche current 6.5 A Single pulse avalanche energy 190 mJ Operating junction temperature Storage temperature -55 to 175 °C ID IDM (3),(4) PTOT PTOT (4) IAV EAS (5) TJ Tstg 1. Specified by design. Not subject to production test. 2. Current is limited by bonding, with an RthJC = 2.9 °C/W the chip is able to carry 22 A at 25 °C. 3. Pulse width limited by safe operating area 4. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 5. Starting TJ= 25 °C, ID= 8 A, VDD= 25 V Table 3. Thermal resistance Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.9 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 35 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec DocID023010 Rev 4 3/18 18 Electrical characteristics 2 STL7DN6LF3 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter Test conditions Drain-source breakdown voltage (VGS= 0) ID = 250 µA IDSS Zero gate voltage drain current (VGS = 0) VDS = 60 V IGSS Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS= 10 V, ID= 3 A VGS= 5 V, ID= 3 A V(BR)DSS Min. Typ. Max. 60 Unit V 1 µA ±100 nA 2.5 V 35 48 43 60 mΩ mΩ Min. Typ. Max. Unit - 432 - pF - 93 - pF - 10.5 - pF - 8.7 - nC - 1.9 - nC - 1.9 - nC - 6.3 - Ω 1 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Test conditions VDS =25 V, f=1 MHz, VGS=0 VDD=30 V, ID = 6.5 A VGS =10 V, Figure 13 Qgs Gate-source charge Qgd Gate-drain charge RG Intrinsic gate resistance f=1 MHz open drain Table 6. Switching times Symbol td(on) tr td(off) tf 4/18 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD=30 V, ID= 3 A, RG=4.7 Ω, VGS=10 V Figure 12 Fall time DocID023010 Rev 4 Min. Typ. Max. Unit - 6.7 - ns - 10.4 - ns - 32.4 - ns - 5.4 - ns STL7DN6LF3 Electrical characteristics Table 7. Source drain diode Symbol ISD ISDM (1) VSD(2) Parameter Test conditions Min Typ. Max Unit Source-drain current - 6.5 A Source-drain current (pulsed) - 26 A 1.3 V Forward on voltage ISD = 6.5 A, VGS=0 - trr Reverse recovery time - 24 - ns Qrr Reverse recovery charge - 23.3 - nC IRRM Reverse recovery current ISD = 6.5 A, di/dt = 100 A/µs, VDD=48 V, Tj=150 °C - 1.94 - A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration= 300 µs, duty cycle 1.5% DocID023010 Rev 4 5/18 18 Electrical characteristics 2.1 STL7DN6LF3 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM13023v1 ID (A) Zth_AM13007v1 K s hi Tj=175°C Tc=25°C Single pulse is a re a n) o S( 0.2 D 0.1 R t in ax n io y m t b ra pe ed O imit L 10 δ=0.5 -1 10 0.05 0.02 0.01 1 10ms -2 10 100ms Single pulse 1s 0.1 0.1 10 1 VDS(V) Figure 4. Output characteristics -3 10 -4 -2 -3 10 10 10 -1 0 10 10 1 10 tp (s) Figure 5. Transfer characteristics AM13024v1 ID (A) AM13025v1 ID (A) VDS=5V VGS=6, 7, 8, 9, 10V 25 25 5V 20 20 4V 15 15 10 10 5 5 0 0 1 2 3 4 Figure 6. Normalized V(BR)DSS vs temperature AM13010v1 V(BR)DSS (norm) ID=250µA 1.06 35.2 1.02 35.0 0.98 34.8 0.94 34.6 34.4 25 75 125 2 3 4 VGS(V) AM13026v1 RDS(on) (mΩ) 35.4 -25 1 Figure 7. Static drain-source on-resistance 1.10 0.90 -75 6/18 0 0 VDS(V) TJ(°C) DocID023010 Rev 4 2 VGS=10V 3 4 5 ID(A) STL7DN6LF3 Electrical characteristics Figure 8. Gate charge vs gate-source voltage AM13027v1 VGS (V) Figure 9. Capacitance variations AM13028v1 C (pF) VDD=30V ID=6.5A 10 Ciss 8 100 6 Coss 4 2 0 0 2 4 8 6 10 10 Figure 10. Normalized gate threshold voltage vs temperature AM13014v1 VGS(th) ID=250µA (norm) 0 Qg(nC) 10 20 30 40 50 Crss VDS(V) Figure 11. Normalized on-resistance vs temperature AM13015v1 RDS(on) (norm) VGS=10V 2.0 1.2 1.6 1.0 1.2 0.8 0.8 0.6 0.4 -75 0.4 0 -25 25 75 125 TJ(°C) DocID023010 Rev 4 -75 -25 25 75 125 TJ(°C) 7/18 18 Test circuits 3 STL7DN6LF3 Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 15. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/18 0 DocID023010 Rev 4 10% AM01473v1 STL7DN6LF3 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID023010 Rev 4 9/18 18 Package information STL7DN6LF3 Figure 18. PowerFLAT 5x6 double island type R outline %RWWRPYLHZ   3LQ LGHQWLILFDWLRQ   6LGHYLHZ 3LQ LGHQWLILFDWLRQ 7RSYLHZ     B5HYBW\SHB5 10/18 DocID023010 Rev 4 STL7DN6LF3 Package information Table 8. PowerFLAT 5x6 double island type R mechanical data Dimensions (mm) Ref. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 D2 1.68 E 5.95 E2 3.50 3.70 E4 0.55 0.75 E5 0.08 0.28 E6 2.35 2.55 E7 0.40 0.60 5.20 5.40 1.88 6.15 e 6.35 1.27 L 0.60 0.80 K 1.275 1.575 DocID023010 Rev 4 11/18 18 Package information STL7DN6LF3 Figure 19. PowerFLAT 5x6 double island WF type R outline %RWWRPYLHZ     3LQ LGHQWLILFDWLRQ 6LGHYLHZ 7RSYLHZ 3LQ LGHQWLILFDWLRQ      B5HYB7\SHB5:) 12/18 DocID023010 Rev 4 STL7DN6LF3 Package information Table 9. PowerFLAT 5x6 double island WF type R mechanical data Dimensions (mm) Ref. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 D2 1.68 E 6.20 E2 3.50 3.70 E4 0.55 0.75 E5 0.08 0.28 E6 2.35 2.55 E7 0.40 0.60 5.20 1.88 6.40 e L 6.60 1.27 0.70 0.90 L1 K 5.40 0.275 1.275 1.575 DocID023010 Rev 4 13/18 18 Package information STL7DN6LF3 Figure 20. PowerFLAT 5x6 double island recommended footprint (dimensions are in mm) B5HYB7\SHB5:)B)RRWSULQW 14/18 DocID023010 Rev 4 STL7DN6LF3 Packaging information Figure 21. PowerFLAT™ 5x6 tape(a) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) Do Ø1.55±0.05 E1 1.75±0.1 0. 20 Y W(12.00±0.3) F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 WF tape(a) Do P2 2.0 0.05(I) +0.1 1.50 0.0 Po 4.0 0.1(II) E1 1.75 0.1 F(5.50±0.0.05)(III) Y D1 1.50MIN R0.30 MAX W(12.00±0.1) T 0.30 0.05 Bo (5.35±0.05) 5 Packaging information Y Ko (1.20±0.1) P1(8.00±0.1) Ao(6.70±0.1) SECTION Y-Y (I) (II) (III) Measured from centreline of sprocket hole to centreline of pocket. Cumulative tolerance of 10 sprocket holes is ± 0.20 . Measured from centreline of sprocket hole to centreline of pocket. Base and bulk quantity 3000 pcs 8234350_TapeWF_rev_C a. All dimensions are in millimeters. DocID023010 Rev 4 15/18 18 Packaging information STL7DN6LF3 Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification Figure 24. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C 16/18 DocID023010 Rev 4 STL7DN6LF3 6 Revision history Revision history Table 10. Document revision history Date Revision 28-Mar-2012 1 First release. 19-Jun-2012 2 Section 2.1: Electrical characteristics (curves) has been added. Updated Section 4: Package information and tile on the coverpage. 26-Jun-2012 3 Document status promoted from preliminary to production data. 4 Updated title, features and description in cover page. Updated Table 5: Dynamic, Table 6: Switching times and Section 2.1: Electrical characteristics (curves). Updated Section 4: Package information. Added Section 5: Packaging information. Minor text changes. 23-Feb-2015 Changes DocID023010 Rev 4 17/18 18 STL7DN6LF3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 18/18 DocID023010 Rev 4