STL7LN80K5

STL7LN80K5 N-channel 800 V, 0.95 Ω typ., 5 A MDmesh™ K5 Power MOSFET in a PowerFLAT™ 5x6 VHV package Datasheet - production data Features 1 2 3      4 PowerFLAT™ 5x6 VHV Order code VDS RDS(on) max. ID STL7LN80K5 800 V 1.15 Ω 5A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(5, 6, 7, 8) 8 7 6  5 Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(4) 1 2 3 4 Top View S(1, 2, 3) Table 1: Device summary Order code Marking Package Packing STL7LN80K5 7LN80K5 PowerFLAT™ 5x6 VHV Tape and reel April 2017 DocID028831 Rev 3 This is information on a product in full production. 1/16 www.st.com Contents STL7LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/16 4.1 PowerFLAT™ 5x6 VHV package information ................................. 10 4.2 PowerFLAT™ 5x6 packing information ........................................... 13 Revision history ............................................................................ 15 DocID028831 Rev 3 STL7LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID(1) Drain current (continuous) at TC = 25 °C 5 A ID(1) Drain current (continuous) at TC = 100 °C 3.4 A ID(2) Drain current (pulsed) 20 A W PTOT Total dissipation at TC = 25 °C 42 dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range TJ Operating junction temperature range V/ns - 55 to 150 °C Value Unit Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area. ≤ 5 A, di/dt 100 A/μs; VDS peak < V(BR)DSS,VDD= 640 V. DS ≤ 640 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 3 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 59 °C/W Notes: (1)When mounted on 1inch² FR-4 board, 2 oz Cu. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 200 mJ DocID028831 Rev 3 3/16 Electrical characteristics 2 STL7LN80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 800 Unit V VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V, TC = 125 °C (1) 50 µA Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID =100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A 0.95 1.15 Ω Min. Typ. Max. Unit - 270 - pF - 22 - pF - 0.5 - pF - 17 - nC - 48 - nC IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance energy related Co(tr)(2) Equivalent capacitance time related RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 0 to 640 V, VGS = 0 V f = 1 MHz, ID=0 A VDD = 640 V, ID = 5 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior") 7.5 - Ω - 12 - nC - 2.6 - nC - 8.6 - nC - Notes: (1)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2)Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID028831 Rev 3 STL7LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off-delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 2.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 9.3 - ns - 6.7 - ns - 23.6 - ns - 17.4 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 5 A ISDM(1) Source-drain current (pulsed) - 20 A VSD (2) Forward on voltage ISD= 5 A, VGS = 0 V - 1.6 V ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 276 ns - 2.13 µC - 15.4 A ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 402 ns - 2.79 µC - 13.9 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width is limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. 30 Typ. Max. - Unit V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID028831 Rev 3 5/16 Electrical characteristics 2.1 STL7LN80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/16 DocID028831 Rev 3 STL7LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized V(BR)DSS vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID028831 Rev 3 7/16 Test circuits 3 8/16 STL7LN80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID028831 Rev 3 STL7LN80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID028831 Rev 3 9/16 Package information 4.1 STL7LN80K5 PowerFLAT™ 5x6 VHV package information Figure 20: PowerFLAT™ 5x6 VHV package outline 1 2 3 4 6 5 Bottom view Pin 1 identification 8 7 Side view Pin 1 identification 10/16 8 7 6 5 1 2 3 4 DocID028831 Rev 3 Top view STL7LN80K5 Package information Table 10: PowerFLAT™ 5x6 VHV package mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 2.40 2.50 2.60 e 1.27 L 0.50 0.55 0.60 K 2.60 2.70 2.80 DocID028831 Rev 3 11/16 Package information STL7LN80K5 Figure 21: PowerFLAT™ 5x6 VHV recommended footprint (dimensions are in mm) 8368144_REV_3_footprint 12/16 DocID028831 Rev 3 STL7LN80K5 4.2 Package information PowerFLAT™ 5x6 packing information Figure 22: PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_ Tape_rev_C Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape DocID028831 Rev 3 13/16 Package information STL7LN80K5 Figure 24: PowerFLAT™ 5x6 reel 14/16 DocID028831 Rev 3 STL7LN80K5 5 Revision history Revision history Table 11: Document revision history Date Revision Changes 07-Jan-2016 1 First release. 26-Jan-2016 2 Modified: Table 2: "Absolute maximum ratings" Minor text changes 24-Apr-2017 3 Updated silhouette on cover page. Updated Section 4.1: "PowerFLAT™ 5x6 VHV package information". Minor text changes. DocID028831 Rev 3 15/16 STL7LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 16/16 DocID028831 Rev 3