STL7N60M2

STL7N60M2 N-channel 600 V, 0.92 Ω typ., 5 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 5x5 package Datasheet - production data Features 6 7 Order code VDS @ Tjmax RDS(on) max ID STL7N60M2 650 V 1.05 Ω 5A 5 • • • • 10 4 11 12 1 Applications PowerFLAT™ 5x5 • Figure 1: Internal schematic diagram G 10 D(5, 6, 11, 12) S 9 S 8 S 7 D 11 6D D 12 5D Pin 1 identification 1 NC 2 S 3 S Switching applications Description G(10) S(2, 3, 4, 7, 8, 9) Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. 4 S Top View GIPG260120150916ALS Table 1: Device summary Order code Marking Package Packaging STL7N60M2 7N60M2 PowerFLAT 5x5 Tape and reel January 2015 DocID027417 Rev 1 This is information on a product in full production. 1/13 www.st.com Contents STL7N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.2 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/13 Package mechanical data ............................................................... 10 Revision history ............................................................................ 12 DocID027417 Rev 1 STL7N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3.2 A (1) IDM Drain current (pulsed) 20 A (2) ID Drain current (continuous) at Tpcb = 25 °C 1.2 A (2) ID Drain current (continuous) at Tpcb = 100 °C 0.8 A Drain current (pulsed) 4.8 A (1)(2) IDM PTOT Total dissipation at TC = 25 °C 67 W (2) Total dissipation at Tpcb = 25 °C 4 W dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C 150 °C Value Unit PTOT Tstg Tj Storage temperature Max. operating junction temperature Notes: (1) Pulse width limited by safe operating area. (2) When mounted on FR-4 Board of 1 inch², 2 oz Cu (t < 10 s) (3) ISD ≤ 5 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V. (4) VDS ≤ 480 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 0.83 °C/W Rthj-pcb Thermal resistance junction-pcb max 31.3 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 80 mJ DocID027417 Rev 1 3/13 Electrical characteristics 2 STL7N60M2 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 2 A 0.92 1.05 Ω Min. Typ. Max. Unit - 271 - pF - 15.7 - pF - 0.68 - pF 2 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 75.5 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7.2 - Ω Qg Total gate charge - 8.8 - nC Qgs Gate-source charge - 1.8 - nC Qgd Gate-drain charge - 4.3 - nC Coss eq. (1) VDD = 480 V, ID = 5 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 2.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 7.6 - ns - 7.2 - ns - 19.3 - ns - 15.9 - ns DocID027417 Rev 1 STL7N60M2 Electrical characteristics Table 8: Source drain diode Symbol ISD Test conditions Min. Typ. Max. Unit Source-drain current - 5 A (1) Source-drain current (pulsed) - 20 A (2) Forward on voltage - 1.6 V ISDM VSD Parameter VGS = 0 V, ISD = 5 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 19: "Switching time waveform") Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 19: "Switching time waveform") - 275 ns - 1.55 µC - 11 A - 376 ns - 2.1 µC - 11 A Notes: (1) (2) Pulse width is limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027417 Rev 1 5/13 Electrical characteristics 2.2 STL7N60M2 Electrical characteristics (curves) Figure 2: Safe operating area ID (A) Figure 3: Thermal impedance GIPG260120151432ALS K GIPG270120151414ALS δ = 0.5 δ = 0.2 10 δ = 0.1 10 -1 ea ar (on) S is th x R D in a ion by m t a er ed Op imit l is 1 0.1 δ = 0.05 δ = 0.02 10µs 10-2 δ = 0.01 100µs Zthj-pcb = KRthj-pcb δ = tp / Ƭ 1ms 10-3 10ms 0.01 0.001 0.1 1 10 10 Figure 4: Output characteristics 6V 100 101 102 Tp(s) VDS = 19 V 6 4 4 5V 2 2 0 10 5 15 4V 3V VDS(V) 20 Figure 6: Gate charge vs gate-source voltage VGS (V) 12 10-1 AM15816v1 8 6 0 10-2 ID (A) VGS=7, 8, 9, 10, 11V 8 10-3 Figure 5: Transfer characteristics AM15815v1 ID (A) Ƭ -4 VDS(V) 100 SINGLE PULSE tp Tj=175°C Tpcb=25°C Single pulse 0 (V) VDS 500 10 4 6 8 10 VGS(V) Figure 7: Static drain-source on-resistance AM15824v1 VDS VDD =480V ID =5A 2 RDS(on) (Ω) GIPG260120151602ALS 0.960 400 VGS = 10 V 0.940 8 300 6 0.920 200 4 100 2 0 6/13 0 2 4 6 8 10 0 Qg(nC) DocID027417 Rev 1 0.900 0.880 0 1 2 3 4 5 ID(A) STL7N60M2 Electrical characteristics Figure 8: Capacitance variations C (pF) Figure 9: Output capacitance stored energy AM15818v1 EOSS (µJ) AM15819v1 2.5 1000 Ciss 2.0 100 1.5 f = 1 Mhz 10 Coss 1.0 1 Crss 0.1 0.1 1 10 100 VDS(V) Figure 10: Normalized gate threshold voltage vs temperature VGS(th) AM15718v1 (norm) 0.5 0 0 100 200 300 400 600 VDS(V) 500 Figure 11: Normalized on-resistance vs temperature RDS(on) (norm) 2.5 AM15821v1 1.1 2.1 ID = 250 µA 1.0 1.7 VGS = 10 V 0.9 1.3 0.8 0.9 0.7 0.6 -50 0 50 Tj(°C) 100 Figure 12: Source-drain diode forward characteristics VSD (V) AM15822v1 0.5 -50 0 50 100 Tj(°C) Figure 13: Normalized V(BR)DSS vs temperature V(BR)DSS (norm) AM15823v1 1.4 1.09 1.2 Tj = -50°C 1.0 1.05 Tj = 25°C 0.8 Tj = 150°C 0.6 0.4 ID = 1mA 1.01 0.97 0.2 0 0 1 2 3 4 5 ISD(A) DocID027417 Rev 1 0.93 -50 0 50 100 Tj (°C) 7/13 Test circuits 3 STL7N60M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. 2.7 k Ω 2200 μ F VG 47 k Ω PW 1 kΩ AM01469v 1 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform t on V(BR)DSS t d(on) VD toff tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/13 DocID027417 Rev 1 0 10% VDS 90% AM01473v 1 STL7N60M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID027417 Rev 1 9/13 Package mechanical data 4.1 STL7N60M2 Package mechanical data Figure 20: PowerFLAT™ 5x5 drawings 7 10 4 10 1 9 8 7 11 6 12 5 1 2 3 4 Pin 1 identification 10/13 DocID027417 Rev 1 8365434_A_type_S STL7N60M2 Package mechanical data Table 9: PowerFLAT 5x5 mechanical data mm Dim. Min. Typ. Max. A 0.80 1.0 A1 0.02 0.05 A2 b 0.25 0.30 D 0.50 5.00 D1 4.05 E 4.25 5.00 E1 0.64 0.79 E2 2.25 2.45 e L 1.27 0.45 0.75 Figure 21: PowerFLAT™ 5x5 recommended footprint (dimensions are in mm) 8365434_A DocID027417 Rev 1 11/13 Revision history 5 STL7N60M2 Revision history Table 10: Document revision history 12/13 Date Revision 26-Jan-2015 1 DocID027417 Rev 1 Changes First release. STL7N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027417 Rev 1 13/13