STL7N80K5
N-channel 800 V, 0.95 Ω typ., 3.6 A MDmesh™ K5
Power MOSFET in a PowerFLAT™ 5x6 VHV package
Datasheet - production data
Features
1
2
3
4
PowerFLAT™ 5x6 VHV
Order code
VDS
RDS(on) max.
ID
STL7N80K5
800 V
1.2 Ω
3.6 A
Industry’s lowest RDS(on) x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Figure 1: Internal schematic diagram
D(5, 6, 7, 8)
8
7
6
5
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
G(4)
1
2
3
4
Top View
S(1, 2, 3)
Table 1: Device summary
Order code
Marking
Package
Packing
STL7N80K5
7N80K5
PowerFLAT™ 5x6 VHV
Tape and reel
July 2017
DocID025551 Rev 2
This is information on a product in full production.
1/17
www.st.com
Contents
STL7N80K5
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 9
4
Package information ..................................................................... 10
5
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4.1
PowerFLAT™ 5x6 VHV package information ................................. 11
4.2
PowerFLAT™ 5x6 packing information ........................................... 14
Revision history ............................................................................ 16
DocID025551 Rev 2
STL7N80K5
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
VGS
Parameter
Value
Unit
Gate-source voltage
±30
V
ID
Drain current (continuous) at TC = 25 °C
3.6
A
ID
Drain current (continuous) at TC = 100 °C
2.3
A
IDM(1)
Drain current (pulsed)
14
A
PTOT
W
Total dissipation at TC = 25 °C
42
dv/dt
(2)
Peak diode recovery voltage slope
4.5
dv/dt
(3)
MOSFET dv/dt ruggedness
50
Tj
Operating junction temperature range
Tstg
Storage temperature range
V/ns
- 55 to 150
°C
Value
Unit
Notes:
(1)Pulse
(2)I
SD
(3)V
width limited by safe operating area
≤3.6 A, di/dt ≤100 A/μs, VDS(peak) ≤V(BR)DSS
DS
≤ 640 V
Table 3: Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
3
°C/W
Rthj-pcb
Thermal resistance junction-pcb
59
°C/W
Value
Unit
Table 4: Avalanche characteristics
Symbol
Parameter
IAR
Avalanche current, repetitive or not repetitive
(pulse width limited by Tjmax)
2
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
88
mJ
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Electrical characteristics
2
STL7N80K5
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current
IGSS
VGS = 0 V, ID = 1 mA
Min.
Typ.
Max.
Unit
800
V
VGS = 0 V, VDS = 800 V
1
µA
VGS = 0 V, VDS = 800 V
TC = 125 °C (1)
50
µA
Gate body leakage current
VDS = 0 V, VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 3 A
±10
µA
4
5
V
0.95
1.2
Ω
Min.
Typ.
Max.
Unit
-
360
-
pF
-
30
-
pF
-
1
-
pF
-
47
-
pf
-
20
-
pf
3
Notes:
(1)Defined
by design, not subject to production test.
Table 6: Dynamic
Symbol
Ciss
Parameter
Test conditions
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Coss
Output capacitance
Crss
Reverse transfer capacitance
Co(tr)(1)
Equivalent capacitance time
related
VDS = 0 to 640 V, VGS = 0 V
Co(er)(2)
Equivalent capacitance
energy related
Rg
Intrinsic gate resistance
f = 1 MHz, ID=0 A
-
6
-
Ω
Qg
Total gate charge
-
13.4
-
nC
Qgs
Gate-source charge
-
3.7
-
nC
Qgd
Gate-drain charge
VDD = 640 V, ID = 6 A
VGS= 0 to 10 V
(see Figure 16: "Test circuit
for gate charge behavior")
-
7.5
-
nC
Notes:
(1)C
o(tr)
is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to
80% VDSS.
(2)C
o(er)
is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to
80% VDSS.
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STL7N80K5
Electrical characteristics
Table 7: Switching times
Symbol
td(on)
Parameter
Turn-on delay time
tr
Rise time
td(off)
Turn-off delay time
tf
Fall time
Test conditions
Min.
Typ.
Max.
Unit
VDD= 400 V, ID = 3 A, RG = 4.7 Ω
VGS = 10 V
(see Figure 15: "Test circuit for
resistive load switching times"
and Figure 20: "Switching time
waveform")
-
11.3
-
ns
-
8.3
-
ns
-
23.7
-
ns
-
20.2
-
ns
Min.
Typ.
Max.
Unit
Table 8: Source-drain diode
Symbol
Parameter
Test conditions
ISD
Source-drain current
-
3.6
A
ISDM(1)
Source-drain current
(pulsed)
-
14
A
VSD(2)
Forward on voltage
-
1.5
V
ISD = 6 A, VGS = 0 V
trr
Reverse recovery time
Qrr
Reverrse recovery
charge
IRRM
Reverse recovery
current
trr
Reverse recovery time
Qrr
Reverse recovery
charge
IRRM
Reverse recovery
current
ISD = 6 A, di/dt = 100 A/µs,
VDD = 60 V
(see Figure 17: "Test circuit for
inductive load switching and
diode recovery times")
ISD = 6 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C
(see Figure 17: "Test circuit for
inductive load switching and
diode recovery times")
-
315
ns
-
2.8
µC
-
17.5
A
-
480
ns
-
3.8
µC
-
16
A
Min.
Typ.
Max.
Unit
±30
-
-
V
Notes:
(1)Pulse
width limited by safe operating area
(2)Pulsed:
pulse duration = 300 µs, duty cycle 1.5%
Table 9: Gate-source Zener diode
Symbol
Parameter
Test conditions
V(BR)GSO
Gate-source breakdown
voltage
IGS= ±1 mA, ID= 0 A
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection, thus eliminating the need for additional external componentry.
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Electrical characteristics
2.1
STL7N80K5
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
K
d=0.5
d=0.2
10 -1
d=0.1
0.05
0.02
0.01
c
10 -2
Single pulse
10 -3
10 -5
10 -4 10 -3
10 -2 10 -1
10 0
10 1 tp(s)
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
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STL7N80K5
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs
temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V(BR)DSS vs temperature
Figure 13: Maximum avalanche energy vs starting TJ
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Electrical characteristics
STL7N80K5
Figure 14: Source-drain diode forward characteristics
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STL7N80K5
3
Test circuits
Test circuits
Figure 15: Test circuit for resistive load
switching times
Figure 16: Test circuit for gate charge
behavior
Figure 17: Test circuit for inductive load
switching and diode recovery times
Figure 18: Unclamped inductive load test
circuit
Figure 19: Unclamped inductive waveform
Figure 20: Switching time waveform
DocID025551 Rev 2
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Package information
4
STL7N80K5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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STL7N80K5
4.1
Package information
PowerFLAT™ 5x6 VHV package information
Figure 21: PowerFLAT™ 5x6 VHV package outline
1
2
3
4
6
5
Bottom view
Pin 1
identification
8
7
Side view
Pin 1
identification
8
7
6
5
1
2
3
4
DocID025551 Rev 2
Top view
11/17
Package information
STL7N80K5
Table 10: PowerFLAT™ 5x6 VHV package mechanical data
mm
Dim.
Min.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
0.25
b
0.30
D
5.00
5.20
5.40
0.50
E
5.95
6.15
6.35
D2
4.30
4.40
4.50
E2
2.40
2.50
2.60
e
12/17
Typ.
1.27
L
0.50
0.55
0.60
K
2.60
2.70
2.80
DocID025551 Rev 2
STL7N80K5
Package information
Figure 22: PowerFLAT™ 5x6 VHV recommended footprint (dimensions are in mm)
8368144_REV_3_footprint
DocID025551 Rev 2
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Package information
4.2
STL7N80K5
PowerFLAT™ 5x6 packing information
Figure 23: PowerFLAT™ 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
(III) Measured from centreline of sprocket
hole to centreline of pocket
8234350_ Tape_rev_C
Figure 24: PowerFLAT™ 5x6 package orientation in carrier tape
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STL7N80K5
Package information
Figure 25: PowerFLAT™ 5x6 reel
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Revision history
5
STL7N80K5
Revision history
Table 11: Document revision history
Date
Revision
19-Nov-2013
1
First release.
2
Modified Table 9: "Gate-source Zener diode"
Modified Figure 3: "Thermal impedance".
Updated Section 4: "Package information".
Minor text changes.
07-Jul-2017
16/17
Changes
DocID025551 Rev 2
STL7N80K5
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