STL80N3LLH6

STL80N3LLH6 N-channel 30 V, 0.0046 Ω, 21 A PowerFLAT™ 5x6 STripFET™ VI DeepGATE™ Power MOSFET Features Order code VDSS RDS(on) max ID STL80N3LLH6 30 V 0.0052 Ω 21 A (1) ) s t( c u d 1. The value is rated according Rthj-pcb 1 ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ High avalanche ruggedness ■ Low gate drive power losses ■ Very low switching gate charge 2 4 PowerFLAT™ 5x6 e t le o s b Applications ■ o r P 3 O ) Figure 1. Switching applications Description t(s d o r uc This device is an N-channel Power MOSFET developed using the 6th generation of STripFET™ DeepGATE™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages. P e t e l o s b O Internal schematic diagram     $ $ $ $ ' 3 3 3     "OTTOM6IEW         4OP6IEW !-6 Table 1. Device summary Order code Marking Package Packaging STL80N3LLH6 80N3LLH6 PowerFLAT™ 5x6 Tape and reel December 2011 Doc ID 16773 Rev 4 1/13 www.st.com 13 Contents STL80N3LLH6 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits .............................................. 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 2/13 Doc ID 16773 Rev 4 o r P STL80N3LLH6 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ± 20 V ID(1) Drain current (continuous) at TC = 25 °C 80 A ID (1) ) s ( Drain current (continuous) at TC = 70 °C 60 (1) Drain current (continuous) at TC = 100 °C 51 ID(2) Drain current (continuous) at Tpcb = 25 °C 21 ID ID (2) od Drain current (continuous) at Tpcb=70 °C A A 13.1 A 84 A 60 W 4 W 0.03 W/°C -55 to 150 °C Value Unit Thermal resistance junction-case (drain, steady state) 2.08 °C/W Thermal resistance junction-ambient 31.3 °C/W Drain current (continuous) at Tpcb=100 °C IDM(3) Drain current (pulsed) PTOT (1) Total dissipation at TC = 25 °C PTOT (2) Total dissipation at Tpcb = 25 °C Derating factor e t le so Ob Operating junction temperature Storage temperature )- Tstg A 15.7 ID (2) TJ t c u A Pr s ( t c 1. The value is rated according to Rthj-c. 2. The value is rated according to Rthj-pcb. u d o 3. Pulse width limited by safe operating area. r P e Table 3. Thermal resistance let Symbol Ob so Rthj-case Rthj-pcb (1) Parameter 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec. Doc ID 16773 Rev 4 3/13 Electrical characteristics 2 STL80N3LLH6 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter Drain-source breakdown voltage ID = 250 µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 30 V, VDS = 30 V at TC =125 °C IGSS Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 10.5 A VGS= 4.5 V, ID= 10.5 A V(BR)DSS Table 5. o s b Parameter Test conditions O ) Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=15 V, ID = 21 A VGS =4.5 V (see Figure 14) Gate input resistance f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain s ( t c u d o r P e t e l o 4/13 e t le Dynamic Symbol s b O Test conditions RG VDS = 25 V, f=1 MHz, VGS=0 Doc ID 16773 Rev 4 Min. Typ. Max. 30 V 1 10 1 Unit 1.7 ) s t( uc od µA µA ±100 nA 2.5 V Ω Ω Pr 0.0046 0.0067 0.0052 0.0076 Min. Typ. Max. Unit 1350 230 140 1690 290 176 2030 350 210 pF pF pF 17 8 6 1.25 1.7 nC nC nC 2 Ω STL80N3LLH6 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Table 7. Min. Typ. Max. Unit VDD=15 V, ID= 10.5 A, RG=4.7 Ω, VGS=10 V (see Figure 13) - 9.5 30 37 12 - ns ns ns ns Test conditions Min Typ. Max Source drain diode Symbol Parameter Source-drain current - (1) Source-drain current (pulsed) - (2) Forward on voltage ISD = 21 A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 10.5 A, di/dt = 100 A/µs, VDD=25 V ISD ISDM VSD Test conditions trr Qrr IRRM 1. Pulse width limited by safe operating area - 24 16.8 1.4 21 A 84 A 1.1 V ns nC A s b O 2. Pulsed: pulse duration=300µs, duty cycle 1.5% ) (s eP t e l o uc d o r - ) s t( Unit t c u d o r P e t e l o s b O Doc ID 16773 Rev 4 5/13 Electrical characteristics STL80N3LLH6 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM08914v1 ID (A) 100 PCB for PowerFLAT K Tj=150°C Tc=25°C Single pulse δ=0.5 0.2 a is are n) S(o this in x RD a on rati by m e Op ited Lim -1 10 10ms 10 0.1 0.05 0.02 100ms 1 10 1s ) s t( 0.01 -2 Zth-pcb=k*Rthj-pcb, Rthj-pcb=63.5°C/W 0.1 c u d Single pulse -3 0.01 0.1 Figure 4. ID (A) 10 1 10 -3 10 VDS(V) Output characteristics l o s 6V 5V ) s ( ct 150 b O - 4V 100 u d o 50 0 0 t e l o r P e Figure 6. bs 1 2 3 4 3V 5 AM08917v1 (norm) O 1.06 6/13 50 0 0 Figure 7. 1 2 3 4 5 VGS(V) Static drain-source on resistance AM08918v1 RDS(on) (mΩ) 5.5 VGS=10V 1.02 4.5 1.00 4.0 0.98 3.5 0.96 3.0 0.94 2.5 2.0 50 AM08916v1 100 5.0 25 tp (s) VDS=3V ID=1mA 0 2 10 150 1.04 0.92 -50 -25 1 10 200 VDS(V) Normalized BVDSS vs temperature BVDSS 10 Transfer characteristics ID (A) VGS=10V 200 ro 0 -1 10 P e et Figure 5. AM08915v1 250 -2 10 75 100 TJ(°C) Doc ID 16773 Rev 4 0 10 20 30 ID(A) STL80N3LLH6 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM08919v1 VGS (V) AM08920v1 C (pF) VDD=15V ID=17A 12 Capacitance variations 2500 10 2000 8 Ciss 1500 6 1000 4 ) s t( 500 2 Coss Crss 0 0 20 10 30 40 50 0 0 Qg(nC) Figure 10. Normalized gate threshold voltage vs temperature (norm) l o s ID=250µA 1.8 1.2 1.6 )- 0.8 Ob s ( t c 0.6 0.4 0 25 50 o r P VDS(V) AM08922v1 ID=10.5A VGS=10V 1.4 1.2 1.0 0.8 0.6 du ro P e 0.2 -50 -25 e t e RDS(on) (norm) 1.0 20 Figure 11. Normalized on resistance vs temperature AM08921v1 VGS(th) c u d 10 0.4 0.2 75 100 TJ(°C) t e l o 0 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Source-drain diode forward characteristics O bs AM08923v1 VSD (V) 1.0 TJ=-55°C 0.9 0.8 TJ=25°C TJ=150°C 0.7 0.6 0.5 0.4 0 10 20 30 40 50 60 70 ISD(A) Doc ID 16773 Rev 4 7/13 Test circuits 3 STL80N3LLH6 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD RG 2200 μF D.U.T. 2.7kΩ 47kΩ 1kΩ AM01468v1 e t le D.U.T. VG c u d PW PW ) s t( 100Ω Vi=20V=VGMAX VD o r P AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B o s b A D G S t c u 3.3 μF B 25 Ω D 1000 μF RG S 2200 μF let 3.3 μF VDD ID Vi P e D.U.T. Pw AM01470v1 Figure 17. Unclamped inductive waveform O L VD VDD d o r G o s b (s) L=100μH -O AM01471v1 Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/13 0 Doc ID 16773 Rev 4 10% AM01473v1 STL80N3LLH6 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O Doc ID 16773 Rev 4 9/13 Package mechanical data Table 8. STL80N3LLH6 PowerFLAT 5x6 type S-R mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.20 E 6.15 D2 4.11 E2 3.50 ) s t( c u d 4.31 e 1.27 L 0.50 K 1.275 e t le o r P 3.70 0.80 1.575 o s b Figure 19. PowerFLAT 5x6 type S-R drawing Bottom View O ) s ( t c Top View u d o r P e t e l o s b O Side View 8231817_Rev_D 10/13 Doc ID 16773 Rev 4 STL80N3LLH6 Package mechanical data Figure 20. PowerFLAT™ 5x6 recommended footprint (dimensions in mm) 5.35 4.41 4.33 3.86 O ) s ( t c 1.27 du e t e ol 6.26 o r P 0.95 o s b c u d 0.98 e t le ) s t( 0.62 Footprint o r P s b O Doc ID 16773 Rev 4 11/13 Revision history 5 STL80N3LLH6 Revision history Table 9. Document revision history Date Revision Changes 12-Nov-2009 1 First release. 30-Mar-2010 2 RDS(on) values changed in Table 4: On/off states 26-Sep-2011 3 – Document status promoted from preliminary data to datasheet; – Inserted ID value @ 70 °C, in Table 2: Absolute maximum ratings. 02-Dec-2011 4 Section 4: Package mechanical data has been updated. Minor text changes. c u d ) s t( e t le o s b O ) s ( t c u d o r P e t e l o s b O 12/13 Doc ID 16773 Rev 4 o r P STL80N3LLH6 ) s t( Please Read Carefully: c u d Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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