STL80N75F6

STL80N75F6 N-channel 75 V, 4.5 mΩ typ., 18 A STripFET™ F6 Power MOSFET in PowerFLAT™ 5x6 package Datasheet - production data Features Order code VDS RDS(on) max ID STL80N75F6 75 V 5.5 mΩ 18 A • Very low on-resistance 1 2 • Very low gate charge 3 4 • High avalanche ruggedness PowerFLAT™ 5x6 • Low gate drive power loss Applications • Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 7 5 6 Description This device is an N-channel Power MOSFET developed using the STripFET™ F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. G(4) 1 S(1, 2, 3) 2 3 4 Top View AM15540v2 Table 1. Device summary Order code Marking Package Packaging STL80N75F6 80N75F6 PowerFLAT™ 5x6 Tape and reel August 2014 This is information on a product in full production. DocID018785 Rev 4 1/15 www.st.com 15 Contents STL80N75F6 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 .............................................. 8 DocID018785 Rev 4 STL80N75F6 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 75 V VGS Gate-source voltage ± 20 V ID(1) Drain current (continuous) at TC = 25 °C 80 A ID (2) Drain current (continuous) at Tpcb = 25 °C 18 A (2) Drain current (continuous) at Tpcb=100 °C 11 A Drain current (pulsed) 72 A Total dissipation at TC = 25 °C 80 W Total dissipation at Tpcb = 25 °C 4 W - 55 to 175 °C Value Unit Thermal resistance junction-pcb max 31.3 °C/W Thermal resistance junction-case max. 1.56 °C/W Max value Unit ID IDM (2),(3) PTOT (1) PTOT (2) Tstg Tj Storage temperature Operating junction temperature 1. The value is rated according to Rthj-c 2. The value is rated according to Rthj-pcb 3. Pulse width limited by safe operating area Table 3. Thermal data Symbol Rthj-pcb (1) Rthj-case Parameter 1. When mounted on FR-4 board of 1 inch², 2 oz Cu, t < 10 sec Table 4. Avalanche characteristics Symbol Parameter IAS Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 18 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAS, VDD = 50 V) 730 mJ DocID018785 Rev 4 3/15 Electrical characteristics 2 STL80N75F6 Electrical characteristics (TJ = 25 °C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 75 V, VDS = 75 V, TC = 125 °C IGSS Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS= 10 V, ID= 9 A V(BR)DSS Min. Typ. Max. 75 Unit V 1 10 µA µA ±100 nA 4 V 4.5 5.5 mΩ Min. Typ. Max. Unit - 6100 - pF - 530 - pF - 185 - pF 2 Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Rg Gate input resistance VDS =25 V, f = 1 MHz, VGS = 0 VDD = 37.5 V, ID = 18 A VGS =10 V (see Figure 14) - 78 - nC - 24 - nC - 15 - nC f=1 MHz Gate DC Bias=0 test signal level=20 mV open drain - 1.47 - Ω Min. Typ. Max. Unit - 28 - ns - 17 - ns - 66 - ns - 12 - ns Table 7. Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD= 37.5 V, ID= 9 A, RG=4.7 Ω, VGS=10 V (see Figure 13) Fall time DocID018785 Rev 4 STL80N75F6 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max Unit Source-drain current - 18 A ISDM(1) Source-drain current (pulsed) - 72 A VSD(2) Forward on voltage ISD = 18 A, VGS = 0 - 1.5 V trr Reverse recovery time - 48 ns Qrr Reverse recovery charge - 96 nC IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD= 60 V, TJ = 150 °C (see Figure 15) - 4 A ISD 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 µs, duty cycle 1.5% DocID018785 Rev 4 5/15 Electrical characteristics 2.1 STL80N75F6 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance $0Y ,' $ $0Y .    2SHUDWLRQLQWKLVDUHDLV /LPLWHGE\PD[5'6RQ PV  QDC PV 7M ƒ&  V 7SFE ƒ& 6LQJOH SXOVH     9'69 Figure 4. Output characteristics 6LQJOHSXOVH        WSV Figure 5. Transfer characteristics $0Y ,' $  $0Y ,' $ 9'6 9 9*6 9   9   9         9     Figure 6. Gate charge vs gate-source voltage $0Y 9*6 9 9'' 9   9'69      9*69 Figure 7. Static drain-source on-resistance $0Y 5'6RQ Pȍ 9*6 9 ,' $           6/15      4JQ&   DocID018785 Rev 4     ,'$ STL80N75F6 Electrical characteristics Figure 8. Capacitance variations Figure 9. Normalized gate threshold voltage vs temperature $0Y & S) &LVV $0Y 9*6WK QRUP  ,' —$      &RVV &UVV      9'69 Figure 10. Normalized on-resistance vs temperature $0Y 5'6RQ QRUP         7-ƒ& Figure 11. Source-drain diode forward characteristics $0Y 96' 9 ,' $ 7- ƒ& 9*6 9    7- ƒ&           7-ƒ&  7- ƒ&      ,6'$ Figure 12. Normalized V(BR)DSS vs temperature $0Y 9%5'66 QRUP ,' P$            7-ƒ& DocID018785 Rev 4 7/15 Test circuits 3 STL80N75F6 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 16. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/15 0 DocID018785 Rev 4 10% AM01473v1 STL80N75F6 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID018785 Rev 4 9/15 Package mechanical data STL80N75F6 Figure 19. PowerFLAT™ 5x6 type S-C mechanical data %RWWRPYLHZ   3LQ LGHQWLILFDWLRQ   6LGHYLHZ 3LQ LGHQWLILFDWLRQ      7RSYLHZ 10/15 DocID018785 Rev 4 B,B& STL80N75F6 Package mechanical data Table 9. PowerFLAT™ 5x6 type S-C mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 b 0.25 0.30 0.50 D D2 5.20 4.11 4.31 E 6.15 e 1.27 e1 0.65 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 K 1.05 1.35 L 0.715 1.015 Figure 20. PowerFLAT™ 5x6 recommended footprint (dimensions in mm) Footprint DocID018785 Rev 4 11/15 Packaging mechanical data 5 STL80N75F6 Packaging mechanical data Figure 21. PowerFLAT™ 5x6 tape(a) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 22. PowerFLAT™ 5x6 package orientation in carrier tape. Pin 1 identification a. All dimensions are in millimeters. 12/15 DocID018785 Rev 4 STL80N75F6 Packaging mechanical data Figure 23. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C DocID018785 Rev 4 13/15 Revision history 6 STL80N75F6 Revision history Table 10. Document revision history Date Revision 27-Apr-2011 1 First release. 10-Nov-2011 2 Section 4: Package mechanical data has been updated. Minor text changes. 3 – Modified: Table 2 (IDM value), Table 4 (IAS, EAS values) Table 5 (RDS(on) typ. and max values), Table 6 (typ. and test conditions), Table 7 (test conditions and typ. values) Table 8 (test conditions, typ. and max values) – Added: Section 2.1: Electrical characteristics (curves). – Updated: Section 4: Package mechanical data – Minor text changes 4 – Updated title, features and description in cover page. – Updated unit for RDS(on) in Table 5: On/off states and in Figure 7: Static drain-source on-resistance. – Updated Section 4: Package mechanical data. 11-Mar-2014 21-Aug-2014 14/15 Changes DocID018785 Rev 4 STL80N75F6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID018785 Rev 4 15/15