STL8DN6LF3
Datasheet
Automotive-grade dual N-channel 60 V, 22.5 mΩ typ., 7.8 A STripFET F3
Power MOSFET in a PowerFLAT 5x6 double island package
Features
VDS
RDS(on) max.
ID
STL8DN6LF3
60 V
30 mΩ
7.8 A
•
•
AEC-Q101 qualified
Logic level VGS(th)
•
•
•
175 °C maximum junction temperature
100% avalanche rated
Wettable flank package
Applications
Drain on rear side
•
1
Order code
Switching applications
8
S2
D2
2
G2
7
3
S1
6
4
G1
D1
Description
This device is an N-channel Power MOSFET developed using STripFET F3
technology. It is designed to minimize on-resistance and gate charge to provide
superior switching performance.
5
NG14G22D1D2RSS13S21
Product status link
STL8DN6LF3
Product summary
Order code
STL8DN6LF3
Marking
8DN6LF3
Package
PowerFLAT 5x6
double island
Packing
Tape and reel
DS8667 - Rev 7 - March 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STL8DN6LF3
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VGS
Gate-source voltage
±20
V
VDS
Drain-source voltage
60
V
ID(1)
Drain current (continuous) at TC = 25 °C
20
A
ID
Drain current (continuous) at TC = 100 °C
20
A
Drain current (continuous) at Tpcb = 25 °C
7.8
A
Drain current (continuous) at Tpcb = 100 °C
5.5
A
Drain current (pulsed)
31.2
A
Total power dissipation at TC = 25 °C
65
W
Total power dissipation at Tpcb = 25 °C
4.3
W
Non-repetitive avalanche current
7.8
A
Single pulse avalanche energy
190
mJ
ID(2)
(2)(3)
IDM
PTOT
PTOT(2)
IAV
EAS(4)
Tstg
TJ
Storage temperature range
Operating junction temperature range
-55 to 175
°C
°C
1. Current is limited by bonding, with RthJC = 2.3 °C/W; the chip is able to carry 30 A at 25 °C.
2. When mounted on an 1 inch² 2 Oz. Cu board, t < 10 s.
3. Pulse width is limited by safe operating area.
4. Starting TJ = 25 °C, ID = IAS, VDD = 25 V.
Table 2. Thermal data
Symbol
Parameter
Value
Rthj-case
Thermal resistance junction-case
2.3
Rthj-pcb(1)
Thermal resistance junction-pcb
35
Unit
°C/W
1. When mounted on an 1 inch² 2 Oz. Cu board, t < 10 s.
DS8667 - Rev 7
page 2/15
STL8DN6LF3
Electrical characteristics
2
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 3. On/off states
Symbol
V(BR)DSS
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Drain-source breakdown voltage
VGS = 0 V, ID = 250 µA
IDSS
Zero gate voltage drain current
VGS = 0 V, VDS = 60 V
1
µA
IGSS
Gate-body leakage current
VDS = 0 V, VGS = ±20 V
±100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
2.5
V
RDS(on)
Static drain-source on-resistance
60
V
1
VGS = 10 V, ID = 4 A
22.5
30
mΩ
VGS = 5 V, ID = 4 A
30
44
mΩ
Min.
Typ.
Max.
Unit
-
668
-
pF
-
144
-
pF
-
14
-
pF
-
13
-
nC
-
2.4
-
nC
-
3
-
nC
-
4
-
Ω
Min.
Typ.
Max.
Unit
VDD = 30 V, ID = 4 A,
-
9
-
ns
Rise time
RG = 4.7 Ω, VGS = 10 V
-
7.7
-
ns
Turn-off delay time
(see Figure 12. Test circuit for resistive
load switching times and
Figure 17. Switching time waveform)
-
32.5
-
ns
-
5
-
ns
Table 4. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
RG
Intrinsic gate resistance
Test conditions
VDS = 25 V, f = 1 MHz, VGS = 0 V
VDD = 30 V, ID = 7.8 A, VGS = 0 to 10 V
(see Figure 13. Test circuit for gate
charge behavior)
f = 1 MHz open drain
Table 5. Switching times
Symbol
td(on)
tr
td(off)
tf
DS8667 - Rev 7
Parameter
Turn-on delay time
Fall time
Test conditions
page 3/15
STL8DN6LF3
Electrical characteristics
Table 6. Source drain diode
Symbol
ISD
ISDM
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
7.8
A
Source-drain current (pulsed)
-
31.2
A
1.3
V
Forward on voltage
VGS = 0 V, ISD = 7.8 A
-
trr
Reverse recovery time
ISD = 7.8 A, di/dt = 100 A/µs,
-
30
ns
Qrr
Reverse recovery charge
VDD = 48 V, TJ = 150 °C
-
35
nC
Reverse recovery current
(see Figure 14. Test circuit for inductive
load switching and diode recovery times)
-
2.35
A
VSD
IRRM
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DS8667 - Rev 7
page 4/15
STL8DN6LF3
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 2. Thermal impedance
Figure 1. Safe operating area
AM13006v1
ID
(A)
d=0.5
Tj=175°C
Tpcb=25°C
Single pulse
s
ai
re on)
si a DS(
th R
in ax
n
it o by m
ra
pe ed
O imit
L
10
Zth_AM13007v1
K
0.2
0.1
10
-1
0.05
0.02
0.01
10ms
1
10
-2
10
-3
pcb
100ms
1s
0.1
10
1
0.1
VDS(V)
10
Figure 3. Output characteristics
VGS=10V
4V
25
-4
15
15
10
10
3V
5
1
2
3
4
VDS(V)
Figure 5. Normalized V(BR)DSS vs. temperature
AM13010v1
V(BR)DSS
(norm)
ID=250 µA
-1
10
0
10
1
t p (s)
5
0
0
1.02
22.6
0.98
22.4
0.94
22.2
22
75
125
TJ(°C)
2
4
3
VGS(V)
AM13011v1
RDS(on)
(mΩ)
22.8
25
1
Figure 6. Static drain-source on-resistance
1.06
DS8667 - Rev 7
10
AM13009v1
1.10
-25
-2
VDS=3V
23
0.90
-75
10
25
20
0
-3
ID
(A)
20
0
10
Figure 4. Transfer characteristics
AM13008v1
ID
(A)
Single pulse
2
VGS = 10 V
3
4
5
6
7
ID(A)
page 5/15
STL8DN6LF3
Electrical characteristics (curves)
Figure 7. Gate charge vs. gate-source voltage
Figure 8. Capacitance variations
AM13012v1
VGS
(V)
AM13013v1
C
(pF)
VDD=30V
ID=7.8A
10
1000
8
Ciss
6
4
Coss
100
2
0
0
4
2
6
8
10
14
12
10
Qg (nC)
Figure 9. Normalized gate threshold voltage vs. temperature
10
20
30
40
50
VDS(V)
AM13015v1
RDS(on)
ID=250µA
(norm)
0
Figure 10. Normalized on-resistance vs. temperature
AM13014v1
VGS(th)
Crss
(norm)
VGS=10V
2.0
1.2
1.6
1.0
1.2
0.8
0.8
0.6
0.4
-75
0.4
-25
25
75
0
TJ(°C)
125
-75
-25
25
75
125
TJ(°C)
Figure 11. Source-drain diode forward characteristics
AM13016v1
VSD
(V)
TJ=-55°C
0.9
TJ=25°C
0.8
0.7
TJ=175°C
0.6
0.5
0.4
DS8667 - Rev 7
2
3
4
5
6
7
ISD(A)
page 6/15
STL8DN6LF3
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
Figure 13. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 14. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 15. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 17. Switching time waveform
Figure 16. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS8667 - Rev 7
page 7/15
STL8DN6LF3
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
4.1
PowerFLAT 5x6 double island WF type R package information
Figure 18. PowerFLAT 5x6 double island WF type R package outline
8256945_typeR-WF_R18
DS8667 - Rev 7
page 8/15
STL8DN6LF3
PowerFLAT 5x6 double island WF type R package information
Table 7. PowerFLAT 5x6 double island WF type R mechanical data
Dim.
mm
Min.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
0.25
b
0.30
C
5.80
6.00
6.10
D
5.00
5.20
5.40
D2
4.15
D3
4.05
4.20
4.35
D4
4.80
5.00
5.10
D5
0.25
0.40
0.55
D6
0.15
0.30
0.45
D7
1.68
e
DS8667 - Rev 7
Typ.
0.50
4.45
1.98
1.27
E
6.20
6.40
6.60
E2
3.50
3.70
E3
2.35
2.55
E4
0.40
0.60
E5
0.08
0.28
E6
0.20
0.325
0.45
E7
0.85
1.00
1.15
E8
0.55
E9
4.00
4.20
4.40
E10
3.55
3.70
3.85
K
1.275
L
0.725
0.825
0.925
L1
0.175
0.275
0.375
θ
0°
0.75
1.575
12°
page 9/15
STL8DN6LF3
PowerFLAT 5x6 double island WF type R package information
Figure 19. PowerFLAT 5x6 double island recommended footprint (dimensions are in mm)
8256945_DI_FP_smp_R18
DS8667 - Rev 7
page 10/15
STL8DN6LF3
PowerFLAT 5x6 WF packing information
4.2
PowerFLAT 5x6 WF packing information
Figure 20. PowerFLAT 5x6 WF tape (dimensions are in mm)
1.50
+0.1
0.0
Po
4.0 0.1(II)
P2
2.0 0.05(I)
E1
1.75 0.1
Y
F(5.50±0.0.05)(III)
Do
Bo (5.35±0.05)
D1
1.50 MIN
R0.30
MAX
Ko (1.20±0.1)
W(12.00±0.1)
T
0.30 0.05
Y
P1(8.00±0.1)
Ao(6.70±0.1)
SECTION Y-Y
(I)
(II)
(III)
Measured from centreline of sprocket hole
to centreline of pocket.
Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
Measured from centreline of sprocket
hole to centreline of pocket.
Base and bulk qua ntity 3000 pcs
8234350_TapeWF_rev_C
Figure 21. PowerFLAT 5x6 package orientation in carrier tape
Pin 1
identification
DS8667 - Rev 7
page 11/15
STL8DN6LF3
PowerFLAT 5x6 WF packing information
Figure 22. PowerFLAT 5x6 reel (dimensions are in mm)
R0.60
W3
11.9/15.4
PART NO.
1.90
2.50
R25.00
ØN
178(±2.0)
∅4.00
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING ELECTROSTATIC
SENSITIVE DEVICES
W2
18.4 (max)
A
330 (+0/-4.0)
∅2.50
77
ESD LOGO
W1
12.4 (+2/-0)
06
PS
ØA
128
2.20
R1.10
Ø21.2
All dimensions are in millimeters
∅13.00
CORE DETAIL
DS8667 - Rev 7
8234350_Reel_rev_C
page 12/15
STL8DN6LF3
Revision history
Table 8. Document revision history
Date
Revision
11-Oct-2011
1
First release.
19-Jun-2012
2
Added Section 2.1: Electrical characteristics (curves). Updated Section 4: Package
mechanical data and title on the cover page.
26-Jun-2012
3
Document status promoted from preliminary to production data.
24-Oct-2013
20-Feb-2014
4
5
Changes
•
Updated title and features in cover page
•
Modified: VGS(th) value in Table 4
•
Updated: Section 4: Package mechanical data and Section 5: Packaging mechanical
data
•
Minor text changes
•
Added: Features in cover page
•
Added: note 1 in Table 1
•
Added: Table 20 and Table 9
•
Added: Figure 23
•
Minor text changes
Updated title and description on cover page.
11-May-2017
6
Updated Figure 6: "Normalized V(BR)DSS vs. temperature" and Figure 11: "Normalized onresistance vs. temperature".
Updated Section 4: "Package information"
Minor text changes
04-Mar-2020
DS8667 - Rev 7
7
Updated Section 4 Package information.
Minor text changes.
page 13/15
STL8DN6LF3
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT 5x6 double island WF type R package information . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS8667 - Rev 7
page 14/15
STL8DN6LF3
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS8667 - Rev 7
page 15/15
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