STL8DN6LF6AG

STL8DN6LF6AG Datasheet Automotive-grade dual N-channel 60 V, 21 mΩ typ., 32 A STripFET F6 Power MOSFET in a PowerFLAT 5x6 DI package Features 1 2 3 VDS RDS(on) max. ID PTOT STL8DN6LF6AG 60 V 27 mΩ 32 A 55 W 4 PowerFLAT 5x6 double island D1(7, 8) Order code D2(5, 6) • • • • • • AEC-Q101 qualified Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Wettable flank package Applications G1(2) • G2(4) Switching applications Description S1(1) S2(3) SC12820 This device is a dual N-channel Power MOSFET developed using the STripFET F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Product status link STL8DN6LF6AG Product summary Order code STL8DN6LF6AG Marking 8DN6LF6 Package PowerFLAT 5x6 double island Packing Tape and reel DS11120 - Rev 5 - July 2021 For further information contact your local STMicroelectronics sales office. www.st.com STL8DN6LF6AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 32 Drain current (continuous) at TC = 100 °C 23 Drain current (continuous) at TB = 25 °C 9.6 Drain current (continuous) at TB = 100 °C 6.8 IDM(1)(2) Drain current (pulsed) 38 A IDM(2) Drain current (pulsed) 128 A Total dissipation at TC = 25 °C (one channel active) 55 Total power dissipation at TB = 25 °C (one channel active) 4.8 ID ID(1) PTOT Tstg TJ Storage temperature range Operating junction temperature range -55 to 175 A A W °C °C 1. When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. 2. Pulse width is limited by safe operating area. Table 2. Thermal data Symbol Parameter Value RthJC Thermal resistance, junction-to-case 2.7 RthJB(1) Thermal resistance, junction-to-board 31.3 Unit °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. Table 3. Avalanche characteristics Symbol DS11120 - Rev 5 Parameter Value Unit IAV Avalanche current, not repetitive 32 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = 38 A, VDD = 43.5 V) 120 mJ page 2/15 STL8DN6LF6AG Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. Static Symbol V(BR)DSS Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage VGS = 0 V, ID = 250 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V 1 µA IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 V RDS(on) Static drain-source on-resistance 60 V 1 VGS = 10 V, ID = 9.6 A 21 27 VGS = 4.5 V, ID = 9.6 A 25 31 Min. Typ. Max. Unit - 1340 - pF - 90 - pF - 60 - pF - 27 - nC - 4.6 - nC - 4.3 - nC Min. Typ. Max. Unit mΩ Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 30 V, ID = 9.6 A, VGS = 10 V (see Figure 13. Test circuit for gate charge behavior) Table 6. Switching times Symbol td(on) tr td(off) tf DS11120 - Rev 5 Parameter Test conditions Turn-on delay time VDD = 30 V, ID = 12.5 A, - 9.6 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 20 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 56 - ns - 7 - ns Fall time page 3/15 STL8DN6LF6AG Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) VSD(2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 9.6 A Source-drain current (pulsed) - 38 A 1.3 V Forward on voltage VGS = 0 V, ISD = 9.6 A - trr Reverse recovery time ISD = 25 A, di/dt = 100 A/µs, - 22.5 ns Qrr Reverse recovery charge VDD = 48 V, TJ = 25 °C - 22.2 nC IRRM Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 2.0 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS11120 - Rev 5 page 4/15 STL8DN6LF6AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) 102 101 GADG210620211108SOA K IDM GADG210620211108ZTH δ = 0.5 ea ar his S(on) t in R D on y ati b er ited p O lim is tp =10µs tp =100µs 10 -1 0.01 tp =10ms TJ ≤ 175 °C TC = 25 °C Single pulse VGS = 10 V 100 101 10-1 10-1 Rth = K*RthJC Single pulse V(BR)DSS VDS (V) 10 -2 10 -5 Figure 3. Output characteristics ID (A) GIPG2206157L62A1LOCH 35 ID (A) V GS = 4 V 20 15 15 10 10 5 5 3 4 5 6 7 V DS (V) Figure 5. Gate charge vs gate-source voltage V GS (V) GIPG2206157L62A1LQVG V DD = 30 V I D = 9.6 A 12 10 -1 tp (s) V DS = 1 V 25 20 2 10 -2 30 V GS = 3 V 1 10 -3 GIPG2206157L62A1LTCH 35 25 0 0 10 -4 Figure 4. Transfer characteristics V GS = 5, 6, 7, 8, 9, 10 V 30 0.05 0.02 tp =1ms RDS(on) max. 100 0.2 0.1 0 0 1 2 3 4 5 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (mΩ) GIPG2206157L62A1LRID V GS = 10 V 21.5 21.0 10 20.5 8 20.0 6 19.5 4 19.0 2 0 0 DS11120 - Rev 5 18.5 5 10 15 20 25 Q g (nC) 18.0 0 2 4 6 8 10 I D (A) page 5/15 STL8DN6LF6AG Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG2206157L62A1LCVR V GS(th) (norm.) GIPG2206157L62A1LVTH I D = 250 µA 1.2 C ISS 10 3 1.0 0.8 10 2 C OSS C RSS 0.6 f = 1 MHz 10 1 0 10 20 30 40 50 60 0.4 -75 V DS (V) 25 75 125 175 T j (°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) 2.2 -25 V (BR)DSS (norm.) GIPG2206157L62A1LRON V GS = 10 V 2.0 GIPG2206157L62A1LBDV I D = 250 µA 1.10 1.8 1.6 1.05 1.4 1.2 1.00 1.0 0.8 0.95 0.6 0.4 -75 -25 25 75 125 175 0.90 -75 T j (°C) -25 25 75 125 175 T j (°C) Figure 11. Source-drain diode forward characteristics V SD (V) 1.0 0.9 GIPG2206157L62A1LSDF T j = -55 °C T j = 25 °C 0.8 0.7 T j = 175 °C 0.6 0.5 5 DS11120 - Rev 5 10 15 20 25 30 I SD (A) page 6/15 STL8DN6LF6AG Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD VGS AM01472v1 0 VDS 10% 90% 10% AM01473v1 DS11120 - Rev 5 page 7/15 STL8DN6LF6AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 double island WF type R package information Figure 18. PowerFLAT 5x6 double island WF type R package outline 8256945_typeR-WF_R18 DS11120 - Rev 5 page 8/15 STL8DN6LF6AG PowerFLAT 5x6 double island WF type R package information Table 8. PowerFLAT 5x6 double island WF type R mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.10 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.10 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 D7 1.68 e DS11120 - Rev 5 Typ. 0.50 4.45 1.98 1.27 E 6.20 6.40 6.60 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.85 1.00 1.15 E8 0.55 E9 4.00 4.20 4.40 E10 3.55 3.70 3.85 K 1.275 L 0.725 0.825 0.925 L1 0.175 0.275 0.375 θ 0° 0.75 1.575 12° page 9/15 STL8DN6LF6AG PowerFLAT 5x6 double island WF type R package information Figure 19. PowerFLAT 5x6 double island recommended footprint (dimensions are in mm) 8256945_DI_FP_smp_R18 DS11120 - Rev 5 page 10/15 STL8DN6LF6AG PowerFLAT 5x6 WF packing information 4.2 PowerFLAT 5x6 WF packing information Figure 20. PowerFLAT 5x6 WF tape (dimensions are in mm) 1.50 +0.1 0.0 Po 4.0 0.1(II) P2 2.0 0.05(I) E1 1.75 0.1 Y F(5.50±0.0.05)(III) Do Bo (5.35±0.05) D1 1.50 MIN R0.30 MAX Ko (1.20±0.1) W(12.00±0.1) T 0.30 0.05 Y P1(8.00±0.1) Ao(6.70±0.1) SECTION Y-Y (I) (II) (III) Measured from centreline of sprocket hole to centreline of pocket. Cumulative tolerance of 10 sprocket holes is ± 0.20 . Measured from centreline of sprocket hole to centreline of pocket. Base and bulk qua ntity 3000 pcs 8234350_TapeWF_rev_C Figure 21. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS11120 - Rev 5 page 11/15 STL8DN6LF6AG PowerFLAT 5x6 WF packing information Figure 22. PowerFLAT 5x6 reel (dimensions are in mm) R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ∅4.00 ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) ∅2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters ∅13.00 CORE DETAIL DS11120 - Rev 5 8234350_Reel_rev_C page 12/15 STL8DN6LF6AG Revision history Table 9. Document revision history Date Revision Changes 24-Jun-2015 1 First release. 07-Jul-2015 2 Minor text edits throughout document. Updated title. 19-Jan-2016 3 Updated Table 2: "Absolute maximum ratings", Table 3: "Thermal data" and Table 4: "Avalanche characteristics". Updated Figure 2: "Safe operating area" and Figure 3: "Thermal impedance". Minor text changes. Updated Table 2: "Absolute maximum ratings". 21-Sep-2016 4 Updated Section 4.1: "PowerFLAT™ 5x6 double island WF type R package information". Minor text changes. Updated Internal schematic for dual N-channel in cover page. 01-Jul-2021 5 Updated Figure 1. Safe operating area and Figure 2. Thermal impedance. Minor text changes. DS11120 - Rev 5 page 13/15 STL8DN6LF6AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 double island WF type R package information . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS11120 - Rev 5 page 14/15 STL8DN6LF6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS11120 - Rev 5 page 15/15