STL8N65M5

STL8N65M5 N-channel 650 V, 0.56 Ω, 7 A MDmesh™ V Power MOSFET in PowerFLAT™ 5x5 Features Order code STL8N65M5 VDSS @ TJmax 710 V RDS(on) max ID 7 8 6 < 0.6 Ω 7A 9 (1) 5 10 11 1. The value is rated according to Rthj-case 4 3 12 ■ Worldwide best RDS(on) * area ■ Higher VDSS rating ■ High dv/dt capability ■ Excellent switching performance ■ Easy to drive ■ 100% avalanche tested 14 1 PowerFLAT™ 5x5 Applications ■ 2 13 Figure 1. Internal schematic diagram Switching applications D D D 14 13 12 11 G Pin 1 Description (not connected) This device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Table 1. S 2 10 S S 3 9 S Drain S 4 5 6 7 D D D 8 S Device summary Order code Marking Package Packaging STL8N65M5 8N65M5 PowerFLAT™ 5x5 Tape and reel August 2011 Doc ID 019013 Rev 3 1/13 www.st.com 13 Contents STL8N65M5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 Doc ID 019013 Rev 3 STL8N65M5 1 Electrical ratings Electrical ratings Table 2. Symbol Absolute maximum ratings Parameter Value Unit VDS Drain-source voltage (VGS = 0) 650 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 7 A ID (1) ID (1) Drain current (continuous) at TC = 100 °C 4.4 A ID (2) Drain current (continuous) at Tamb = 25 °C 1.4 A ID (2) Drain current (continuous) at Tamb = 100 °C 0.6 A Drain current (pulsed) 5.6 A PTOT (2) Total dissipation at Tamb = 25 °C 2.5 W PTOT(1) Total dissipation at TC = 25 °C 70 W IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 2 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 120 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit IDM (2),(3) dv/dt (4) Tstg Tj Storage temperature Max. operating junction temperature 1. The value is rated according to Rthj-case 2. When mounted on FR-4 board of inch², 2oz Cu 3. Pulse with limited by safe operating area. 4. ISD ≤ 7 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 400 V. Table 3. Symbol Thermal data Parameter Rthj-case Thermal resistance junction-case max 1.78 °C/W Rthj-pcb(1) Thermal resistance junction-pcb max 60 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 019013 Rev 3 3/13 Electrical characteristics 2 STL8N65M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS On /off states Parameter Test conditions Drain-source breakdown voltage (VGS = 0) ID = 1 mA Min. Typ. Max. Unit 650 V IDSS VDS = 650 V Zero gate voltage drain current (VGS = 0) VDS = 650 V, TC=125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) 100 nA 4 5 V 0.56 0.6 Ω Min. Typ. Max. Unit - 690 18 2 - pF pF pF - 17 - pF - 52 - pF VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance Table 5. Symbol Ciss Coss Crss 3 VGS = 10 V, ID = 3.5 A Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VDS = 0 to 520 V, VGS = 0 RG Intrinsic gate resistance f = 1 MHz open drain - 2.4 - Ω Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 520 V, ID = 3.5 A, VGS = 10 V (see Figure 15) - 15 3.6 6 - nC nC nC 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/13 Doc ID 019013 Rev 3 STL8N65M5 Electrical characteristics Table 6. Symbol td(off) tr (V) tc(off) tf (i) Table 7. Switching times Parameter Test conditions Turn-off delay time Rise time Cross time Fall time VDD = 400 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V (see Figure 16), (see Figure 19) Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage IRRM trr Qrr IRRM Typ. - 50 14 20 11 Min. Typ. Max Unit - ns ns ns ns Source drain diode Symbol trr Qrr Min. Test conditions Max. Unit - 7 28 A A ISD = 7 A, VGS = 0 - 1.5 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 7A, di/dt = 100 A/µs VDD = 100 V (see Figure 16) - 200 1.6 16 ns µC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 7 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 16) - 263 1.9 15 ns µC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 019013 Rev 3 5/13 Electrical characteristics STL8N65M5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 5. Transfer characteristics AM07211v1 ID (A) Tj=150°C Tc=25°C Single pulse 10 is ea ar (on) DS R x is 1 th 10µs in a ion y m at er d b Op ite Lim 100µs 0.1 1ms 10ms 0.01 0.001 0.1 Figure 4. 10 1 VDS(V) 100 Output characteristics AM08197v1 ID (A) 12 VGS=10V 7.5V AM08198v1 ID (A) 12 VDS=20V 7V 10 10 6.5V 8 8 6 6 6V 4 4 2 2 5.5V 0 0 Figure 6. 5 10 5V VDS(V) 15 0 3 Gate charge vs gate-source voltage Figure 7. AM03195v1 VGS (V) 12 VGS VDD=520V ID=3.5A VDS 5 7 6 8 9 VGS(V) Static drain-source on resistance AM08200v1 RDS(on) (Ohm) VGS=10V 500 10 4 0.58 400 0.56 8 300 6 0.54 200 4 100 2 0 0 6/13 5 10 15 0 Qg(nC) 0.52 0.50 Doc ID 019013 Rev 3 0 2 4 6 ID(A) STL8N65M5 Figure 8. Electrical characteristics Capacitance variations Figure 9. AM08202v1 C (pF) Output capacitance stored energy AM08201v1 Eoss (µJ) 3.5 1000 Ciss 3.0 2.5 100 2.0 1.5 Coss 10 Crss 1 0.1 1 100 10 1.0 0.5 0 0 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature AM08204v1 VGS(th) (norm) 100 400 500 600 200 300 VDS(V) Figure 11. Normalized on resistance vs temperature AM08205v1 RDS(on) (norm) VGS=10V ID=3.5A 1.10 2.0 1.00 1.5 0.90 1.0 0.80 0.70 -50 -25 0 25 50 TJ(°C) 75 100 0.5 -50 -25 0 25 75 100 50 TJ(°C) Figure 12. Switching losses vs gate resistance Figure 13. Normalized BVDSS vs temperature (1) AM08206v1 E (µJ) AM08203v1 BVDSS (norm) ID=4A VCL=400V VGS=10V ID=1mA 1.07 Eoff 1.05 100 Eon 1.03 1.01 0.99 10 0.97 0.95 1 0 10 20 30 40 RG(Ω) 0.93 -50 -25 0 25 50 75 100 TJ(°C) 1. Eon including reverse recovery of a SiC diode Doc ID 019013 Rev 3 7/13 Test circuits 3 STL8N65M5 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 µF 2200 RL µF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 µF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100µH S 3.3 µF B 25 Ω 1000 µF D VDD 2200 µF 3.3 µF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 18. Unclamped inductive waveform V(BR)DSS AM01471v1 Figure 19. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD 10%Id 10%Vds Vds Trise AM01472v1 8/13 Doc ID 019013 Rev 3 Tfall Tcross --over AM05540v1 STL8N65M5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 019013 Rev 3 9/13 Package mechanical data Table 8. STL8N65M5 PowerFLAT™ 5x5 mechanical dimensions mm Dim. Min. Typ. Max. A 0.80 0.90 1.0 A1 0 0.02 0.05 A3 0.24 D 4.90 5.0 5.10 E 4.90 5.0 5.10 E2 2.49 2.57 2.64 e 1.22 1.27 1.32 b 0.43 0.51 0.58 c 0.64 0.71 0.79 Figure 20. PowerFLAT™ 5x5 mechanical drawing 7267096_Rev_F 10/13 Doc ID 019013 Rev 3 STL8N65M5 Package mechanical data Figure 21. PowerFLAT™(5x5) recommended footprint (mm) Doc ID 019013 Rev 3 11/13 Revision history 5 STL8N65M5 Revision history Table 9. 12/13 Document revision history Date Revision Changes 05-Jul-2011 1 First release 07-Jul-2011 2 Updated Figure 1. 08-Aug-2011 3 Updated Figure 3: Thermal impedance. and Rthj-pcb value in Table 3: Thermal data. Minor text changes. Doc ID 019013 Rev 3 STL8N65M5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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