STL8N6F7

STL8N6F7 N-channel 60 V, 0.019 Ω typ., 8 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 3.3x3.3 package Datasheet - production data Features 1 2 3     4 PowerFLAT™ 3.3x3.3 Order code VDS RDS(on) max ID STL8N6F7 60 V 0.023 Ω 8A Among the lowest RDS(on) on the market Excellent figure of merit (FoM) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Applications  Switching applications Figure 1: Internal schematic diagram Description D(5, 6, 7, 8) 8 7 6 5 1 2 3 4 G(4) S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. AM15810v1 Table 1: Device summary Order code Marking Package Packing STL8N6F7 8N6F7 PowerFLAT™ 3.3x3.3 Tape and reel October 2015 DocID028258 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STL8N6F7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 5 3 Test circuits ..................................................................................... 7 4 Package information ....................................................................... 8 4.1 5 2/13 PowerFLAT 3.3x3.3 package information ......................................... 9 Revision history ............................................................................ 12 DocID028258 Rev 2 STL8N6F7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ± 20 V ID(1) Drain current (continuous) at TC = 25 °C 36 A ID(1) Drain current (continuous) at TC = 100 °C 22 A Drain current (pulsed) 144 A IDM(1)(2) ID(3) Drain current (continuous) at Tpcb = 25 °C 8 A ID(3) Drain current (continuous) at Tpcb = 100 °C 5 A IDM(2)(3) Drain current (pulsed) 32 A PTOT(1) Total dissipation at TC = 25 °C 60 W PTOT(3) Total dissipation at Tpcb = 25 °C 3 W -55 to 150 °C Tstg Tj Storage temperature Operating junction temperature Notes: (1)This value is rated according to Rthj-c. (2)Pulse (3)This width limited by safe operating area. value is rated according to Rthj-pcb. Table 3: Thermal data Symbol Parameter Value Unit Rthj-pcb(1) Thermal resistance junction-pcb max. 42.8 °C/W Rthj-case Thermal resistance junction-case max. 2.1 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec. DocID028258 Rev 2 3/13 Electrical characteristics 2 STL8N6F7 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current VGS = 0 V VDS = 60 V IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A Min. Typ. Max. 60 Unit V 2 0.019 1 µA 100 nA 4 V 0.023 Ω Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 30 V, f = 1 MHz, VGS = 0 V VDD = 30 V, ID = 8 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") Min. Typ. Max. Unit - 420 - pF - 215 - pF - 16 - pF - 8 - nC - 2.3 - nC - 2.1 - nC Min. Typ. Max. Unit - 7.85 - ns - 3.25 - ns - 12.1 - ns - 3.95 - ns Min. Typ. Max. Unit 1.2 V Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 30 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times") Rise time Turn-off delay time Fall time Table 7: Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 8 A, VGS = 0 V - trr Reverse recovery time - 17.1 ns Qrr Reverse recovery charge - 6.67 nC IRRM Reverse recovery current ID = 8 A, di/dt = 100 A/µs VDD = 48 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times" - 0.8 A Notes: (1)Pulsed: 4/13 pulse duration = 300 µs, duty cycle 1.5% DocID028258 Rev 2 STL8N6F7 2.1 Electrical characteristics Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028258 Rev 2 5/13 Electrical characteristics STL8N6F7 Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics 6/13 DocID028258 Rev 2 STL8N6F7 3 Test circuits Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID028258 Rev 2 7/13 Package information 4 STL8N6F7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 8/13 DocID028258 Rev 2 STL8N6F7 4.1 Package information PowerFLAT 3.3x3.3 package information Figure 19: PowerFLAT™ 3.3x3.3 package outline BOTTOM VIEW SIDE VIEW TOP VIEW 8465286_ A DocID028258 Rev 2 9/13 Package information STL8N6F7 Table 8: PowerFLAT™ 3.3x3.3 package mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 030 0.45 0.60 L1 0.05 0.15 0.25 L2 θ 10/13 0.15 8° DocID028258 Rev 2 10° 12° STL8N6F7 Package information Figure 20: PowerFLAT™ 3.3x3.3 recommended footprint 8465286_footprint DocID028258 Rev 2 11/13 Revision history 5 STL8N6F7 Revision history Table 9: Document revision history Date Revision 20-Aug-2015 1 First release. 2 Updated title and features in cover page. Updated Table 4: "On /off states", Table 5: "Dynamic", Table 6: "Switching times" and Table 7: "Source-drain diode". Added Section 3.1: "Electrical characteristics (curves)". Document status promoted from preliminary di production data. 22-Oct-2015 12/13 Changes DocID028258 Rev 2 STL8N6F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028258 Rev 2 13/13