STL8N6LF3
Automotive-grade N-channel 60 V, 22.5 mΩ typ., 7.8 A
STripFET™ F3 Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - production data
Features
Order code
VDS
RDS(on) max.
ID
STL8N6LF3
60 V
30 mΩ
7.8 A
AEC-Q101 qualified
Logic level VGS(th)
175 °C maximum junction temperature
100% avalanche rated
Wettable flank package
Applications
Figure 1: Internal schematic diagram
Switching applications
Description
This device is an N-channel Power MOSFET
developed using STripFET™ F3 technology. It is
designed to minimize on-resistance and gate
charge to provide superior switching
performance.
Table 1: Device summary
Order code
Marking
Package
Packing
STL8N6LF3
8N6LF3
PowerFLAT™ 5x6
Tape and reel
May 2017
DocID027037 Rev 3
This is information on a product in full production.
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www.st.com
Contents
STL8N6LF3
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
5
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4.1
PowerFLAT 5x6 WF type R package information ............................. 9
4.2
Packing information ......................................................................... 12
Revision history ............................................................................ 14
DocID027037 Rev 3
STL8N6LF3
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
60
V
VGS
Gate-source voltage
±20
V
ID(1)
Drain current (continuous) at TC = 25 °C
20
A
ID
Drain current (continuous) at TC = 100 °C
20
A
ID(3)
Drain current (continuous) at Tpcb = 25 °C
7.8
A
ID(3)
Drain current (continuous) at Tpcb = 100 °C
5.5
A
Drain current (pulsed)
31.2
A
IDM(2)(3)
PTOT
Total dissipation at TC = 25 °C
65
W
PTOT(3)
Total dissipation at Tpcb = 25°C
4.3
W
IAS
Not-repetitive avalanche current
7.8
A
EAS(4)
Single pulse avalanche energy
190
mJ
-55 to 175
°C
Tj
Operating junction temperature range
Tstg
Storage temperature range
Notes:
(1)Current
is limited by bonding, with an RthJC = 2.3 °C/W the chip is able to carry 30 A at 25 °C.
(2)Pulse
width limited by safe operating area.
(3)When
mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s.
(4)Starting
TJ= 25 °C, ID=IAS, VDD= 25 V.
Table 3: Thermal resitance
Symbol
Parameter
Rthj-case
Rthj-pcb
(1)
Value
Unit
Thermal resistance junction-case
2.3
°C/W
Thermal resistance junction-pcb
35
°C/W
Notes:
(1)When
mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
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Electrical characteristics
2
STL8N6LF3
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: On/Off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Drain-source breakdown
voltage
VGS = 0 V, ID = 250 μA
IDSS
Zero gate voltage
drain current
VGS = 0 V, VDS = 60 V
1
µA
IGSS
Gate-body leakage
current
VDS = 0 V, VGS = ±20 V
±100
nA
VGS(th)
Gate threshold voltage
VDS = VGS , ID = 250 μA
2.5
V
RDS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 4 A
22.5
30
mΩ
VGS = 5 V, ID = 4 A
30
44
mΩ
Min.
Typ.
Max.
Unit
-
668
-
-
144
-
-
14
-
-
13
-
-
2.4
-
-
3
-
-
4
-
Ω
Test conditions
Min.
Typ.
Max.
Unit
VDD = 30 V, ID = 4 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13: "Test circuit for
resistive load switching times"
and Figure 18: "Switching time
waveform")
-
9
-
-
7.7
-
-
32.5
-
-
5
-
V(BR)DSS
60
V
1
Table 5: Dynamic
Symbol
Test conditions
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
VDD = 30 V, ID = 7.8 A,
VGS = 0 to 10 V
(see Figure 14: "Test circuit for
gate charge behavior")
RG
Intrinsic gate resistance
f =1 MHz, ID=0 A
VDS = 25 V, f = 1 MHz,
VGS = 0 V
pF
nC
Table 6: Switching times
Symbol
td(on)
tr
td(off)
tf
4/15
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
DocID027037 Rev 3
ns
STL8N6LF3
Electrical characteristics
Table 7: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain current
-
7.8
A
ISDM(1)
Source-drain current
(pulsed)
-
31.2
A
VSD(2)
Forward on voltage
IDS = 7.8 A, VGS = 0 V
-
1.3
V
trr
Reverse recovery time
-
30
ns
Qrr
Reverse recovery charge
-
35
nC
IRRM
Reverse recovery current
ISD = 7.8 A, di/dt = 100 A/µs
VDD = 48 V, Tj = 150 °C (see
Figure 15: "Test circuit for
inductive load switching and
diode recovery times")
-
2.35
A
Notes:
(1)Pulse
width limited by safe operating area.
(2)Pulsed:
pulse duration = 300 μs, duty cycle 1.5 %.
DocID027037 Rev 3
5/15
Electrical characteristics
2.1
STL8N6LF3
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
d
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Normalized V(BR)DSS vs temperature
Figure 7: Static drain-source on-resistance
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DocID027037 Rev 3
STL8N6LF3
Electrical characteristics
Figure 8: Gate charge vs gate-source voltage
Figure 9: Capacitance variation
Figure 10: Normalized gate threshold voltage vs
temperature
Figure 11: Normalized on-resistance vs
temperature
Figure 12: Source-drain diode forward characteristics
DocID027037 Rev 3
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Test circuits
3
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STL8N6LF3
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID027037 Rev 3
STL8N6LF3
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
PowerFLAT 5x6 WF type R package information
Figure 19: PowerFLAT™ 5x6 WF type R package outline
8231817_R_WF_Rev_15
DocID027037 Rev 3
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Package information
STL8N6LF3
Table 8: PowerFLAT™ 5x6 WF type R mechanical data
mm
Dim.
Min.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
0.25
b
0.30
C
5.80
6.00
6.10
0.50
5.20
5.40
D
5.00
D2
4.15
D3
4.05
4.20
4.35
D4
4.80
5.00
5.10
D5
0.25
0.4
0.55
D6
0.15
0.3
0.45
e
10/15
Typ.
4.45
1.27
E
6.20
E2
3.50
3.70
E3
2.35
2.55
E4
0.40
0.60
E5
0.08
0.28
E6
0.20
0.325
0.45
E7
0.85
1.00
1.15
E9
4.00
4.20
4.40
E10
3.55
3.70
3.85
K
1.275
L
0.725
0.825
0.925
L1
0.175
0.275
0.375
ϴ
0°
DocID027037 Rev 3
6.40
6.60
1.575
12°
STL8N6LF3
Package information
Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev15
DocID027037 Rev 3
11/15
Package information
4.2
STL8N6LF3
Packing information
Figure 21: PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape
12/15
DocID027037 Rev 3
STL8N6LF3
Package information
Figure 23: PowerFLAT™ 5x6 reel (dimensions are in mm)
DocID027037 Rev 3
13/15
Revision history
5
STL8N6LF3
Revision history
Table 9: Document revision history
Date
Revision
13-Oct-2014
1
First release.
2
Updated title.
Datasheet promoted from preliminary data to production data.
Updated Section 4: Package information.
Minor text changes.
3
Modified Figure 6: "Normalized V(BR)DSS vs temperature" and Figure
11: "Normalized on-resistance vs temperature".
Updated Section 4: "Package information"
Minor text changes.
23-Nov-2015
11-May-2017
14/15
Changes
DocID027037 Rev 3
STL8N6LF3
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DocID027037 Rev 3
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