STL9P2UH7

STL9P2UH7 P-channel 20 V, 0.0195 Ω typ., 9 A STripFET™ H7 Power MOSFET in a PowerFLAT™ 3.3x3.3 package Datasheet - production data    Very low on-resistance Very low capacitance and gate charge High avalanche ruggedness Applications  1 Switching applications Description 2 3 This P-channel Power MOSFET utilizes the STripFET H7 technology with a trench gate structure combined with extremely low onresistance. The device also offers ultra-low capacitances for higher switching frequency operations. 4 PowerFLAT™ 3.3x3.3 Figure 1: Internal schematic diagram Table 1: Device summary D(5, 6, 7, 8) 8 7 6 5 Order code STL9P2UH7 Marking Package Packaging 9P2H7 PowerFLAT™ 3.3x3.3 Tape and reel G(4) For the P-channel Power MOSFET the actual polarity of the voltages and the current must be reversed. S(1, 2, 3) 1 2 3 4 Features Order code VDS RDS(on)max ID STL9P2UH7 20 V 0.0225 Ω @ 4.5 V 9A October 2014 DocID025141 Rev 3 This is information on a product in full production. 1/14 www.st.com Contents STL9P2UH7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/14 PowerFLAT™ 3.3 x 3.3 package mechanical data ......................... 10 Revision history ............................................................................ 13 DocID025141 Rev 3 STL9P2UH7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 20 V VGS Gate-source voltage ±8 V Drain current (continuous) at Tpcb= 25 °C 9 A Drain current (continuous) at Tpcb= 100 °C 5.9 A Drain current (pulsed) 36 A Total dissipation at Tpcb= 25 °C 2.9 W - 55 to 150 °C 150 °C (1) ID ID (1) IDM (2) PTOT (1) Tstg Storage temperature Tj Max. operating junction temperature Notes: (1) (2) The value is rated according to R thj-pcb Pulse width limited by safe operating area Table 3: Thermal resistance Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.5 °C/W Thermal resistance junction-pcb 42 °C/W Notes: (1) When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec. For the P-channel Power MOSFET the actual polarity of the voltages and the current must be reversed. DocID025141 Rev 3 3/14 Electrical characteristics 2 STL9P2UH7 Electrical characteristics (T C= 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage VGS = 0, ID = 250 µA IDSS Zero gate voltage drain current VG S= 0, VDS = 20 V 1 µA IGSS Gate-body leakage current VDS = 0, VGS = ± 5 V ±5 µA Gate threshold voltage VDS = VGS, ID = 250 µA 1 V V(BR)DSS VGS(th) RDS(on) Static drain-source on-resistance 20 V 0.4 VGS= 4.5 V, ID= 4.5 A 0.0195 0.0225 Ω VGS = 2.5 V, ID = 4.5 A 0.02 0.025 Ω VGS = 1.8 V, ID = 4.5 A 0.036 0.043 Ω VGS = 1.5 V, ID = 4.5 A 0.05 0.085 Ω Min. Typ. Max. Unit - 2390 - pF - 220 - pF - 188 - pF - 22 - nC - 4.2 - nC - 3.6 - nC Min. Typ. Max. Unit - 12.5 - ns - 30.5 - ns - 128 - ns - 84.5 - ns Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Test conditions VGS = 0, VDS = 16 V, f = 1 MHz Qgs Gate-source charge Qgd Gate-drain charge VDD = 15 V, ID = 9 A, VGS = 4.5 V Table 6: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 16 V, ID = 9 A, RG = 1 Ω, VGS = 4.5 V Fall time DocID025141 Rev 3 STL9P2UH7 Electrical characteristics Table 7: Source drain diode Symbol (1) VSD Parameter Test conditions Forward on voltage VGS= 0, ISD= 1 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current VDD= 16 V di/dt = 100 A/µs, ISD= 1 A Min. Typ. Max. Unit - - 1 V - 15.8 ns - 5.9 nC - 0.7 A Notes: (1) Pulsed: pulse duration = 300 µs, duty cycle 1.5% For the P-channel Power MOSFET the actual polarity of the voltages and the current must be reversed. DocID025141 Rev 3 5/14 Electrical characteristics 2.1 STL9P2UH7 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area GIPG210520141011SA ID (A) δ 0.2 100µs is ) ea ar S(on D hi s nt xR i on ma i t y a er d b Op ite m Li 10 0.1 1ms 0.05 10ms 0.02 1 0.01 pcb 0.1 Tj=150°C Tpcb=25°C Single pulse 0.01 0.1 1 V DS(V) 10 Figure 5: Transfer characteristics Figure 4: Output characteristics GIPG210520141044SA ID(A) GIPG210520141055SA ID (A) V GS=2.5, 3, 3.5, 4, 4.5, 5V V DS=2V 20 12.00 2V 15 8.00 10 1.5V 4.00 5 0 0 2 6 4 8 0.00 V DS(V) Figure 6: Gate charge vs gate-source voltage 1 2 1.5 V GS(V) Figure 7: Static drain-source on-resistance GIPG210520141043SA V GS (V) 0.5 0 GIPG210520141102SA R DS(on) (mΩ) V GS=4.5V V DD=16V ID=9A 4 20.5 20.0 3 19.5 2 19.0 1 0 0 6/14 18.5 18.0 5 10 15 20 Q g(nC) DocID025141 Rev 3 0 1 2 3 4 5 6 ID(A) STL9P2UH7 Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 8: Capacitance variations GIPG210520141108SA C (pF) GIPG210520141114SA V GS(th) (norm) ID=250µ A 1.4 1.2 Ciss 1 1000 0.8 0.6 Coss Crss 0.4 100 0 4 8 12 16 V DS(V) 0.2 -75 125 T J(°C) GIPG210520141132SA V (BR)DSS (norm) GIPG210520141119SA ID=4.5 A V GS=4.5V 1.4 75 25 Figure 11: Normalized V(BR)DSS vs temperature Figure 10: Normalized on-resistance vs temperature R DS(on) (norm) 1.6 -25 ID=1m A 1.04 1.2 1.0 1 0.8 0.6 0.96 0.4 0.2 0.0 -75 -25 25 75 0.92 -75 125 T J(°C) -25 25 75 125 T J(°C) Figure 12: Source-drain diode forward characteristics GIPG210520141134SA V SD(V) T J=-55°C 0.9 TJ=25°C 0.8 T J=75°C 0.7 0.6 0.5 1 2 3 4 5 DocID025141 Rev 3 6 7 8 ISD(A) 7/14 Test circuits 3 STL9P2UH7 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Test circuit for inductive load switching and diode recovery times 8/14 DocID025141 Rev 3 STL9P2UH7 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025141 Rev 3 9/14 Package mechanical data 4.1 STL9P2UH7 PowerFLAT™ 3.3 x 3.3 package mechanical data Figure 16: PowerFLAT™ 3.3 x 3.3 drawing BOTTOM VIEW SIDE VIEW TOP VIEW 8465286_A 10/14 DocID025141 Rev 3 STL9P2UH7 Package mechanical data Table 8: PowerFLAT™ 3.3 x 3.3 mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 0.30 0.45 0.60 L1 0.05 0.15 0.25 L2 J 0.15 8° DocID025141 Rev 3 10° 12° 11/14 Package mechanical data STL9P2UH7 Figure 17: PowerFLAT™ 3.3 x 3.3 recommended footprint 8465286_footprint 12/14 DocID025141 Rev 3 STL9P2UH7 5 Revision history Revision history Table 9: Document revision history Date Revision Changes 26-Aug-2013 1 First release. 04-Jun-2014 2 Document status promoted from preliminary data to production data Modified: title Modified: RDS(on) max value in cover page Modified: RDS(on) (typical and maximum) values in Table 4: "On /off states" Modified: the entire typical values in Table 5: "Dynamic", Table 6: "Switching times" and Table 7: "Source drain diode" Added: Section 8.1: "Electrical characteristics (curves)" Minor text changes 21-Oct-2014 3 Updated the title, the features and the description in cover page. Updated Figure 1: "Internal schematic diagram". Minor text changes. DocID025141 Rev 3 13/14 STL9P2UH7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 14/14 DocID025141 Rev 3