STLC1511

STLC1511 NorthenLite™ G.lite BiCMOS Analog Front-End Circuit PRODUCT PREVIEW s Wide transmit (~80dB) and receive (~69dB) dynamic range to limit the external filtering requirements for extended loop reach operation Programmable tx gain: 0 ÷ -32dB in 2dB steps 14-bit D/A converter in transmit path Programmable rx gain: 0 ÷40dB in 0.5dB steps 12-bit A/D converter in receive path Integrated phase-locked loop with an externall LC or crystal oscillator Low power: 300mW @ 5.0V 64-pin TQFP package The STLC1511 transmit path consists of a 14-bit Nyquist rate D/A converter, followed by a programmable gain amplifier (TxPGA). The transmit gain is programmable from 0 to -32dB in 2dB steps. The STLC1511 receive path contains a buffer amplifier followed by a programmable gain amplifier (RxPGA), a low pass anti-aliasing filter, and a 12-bit Nyquist rate A/D converter. The RxPGA is digitally programmable from 0 to 40dB in 0.5dB steps. 2.0 PACKAGING AND PIN INFORMATION 2.1 STLC1511 Pin Allocation The pinout for the STLC1511 is depicted in Figure 1. TQFP64 ORDERING NUMBER: STLC1511 s s s s s s s 1.0 GENERAL DESCRIPTION The STLC1511 G.lite Analog Front End (AFE) chip implements the analog transceiver functions required in both a central office modem and a customer premise modem. It connects the digital modem chip with the loop driver and hybrid balance circuits. The STLC1511 has been designed with excellent dynamic range in order to greatly reduce the external filtering requirements at the front end. The AFE chip and its companion digital chip along with a loop driver, implement the complete G.992.2 DMT modem solution. Figure 1. STLC1511 pinout VSSDIG1 FRMCLK VCCTXPGA VEETXPGA QVEEDAC VDDESD2 TXDADC1 VSSESD2 VCCDAC VEEDAC TXSIN[1] TXSIN[0] RESETN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDDIG1 CK35M DIGREF RXSOUT[0] RXSOUT[1] VSSDIGE1 VSSDIG2 VDDDIGE1 VDDDIG2 DTX DIGCLK ENB DRX VEEADC VCCADC QVEEADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RXDCINP RXDCINN RXDCON RXDCOP RXINN RXINP RXOPIINN RXOPINP VCCRXPGA VEERXPGA VSSESD1 VDDESD1 QVEERX ADCDC3 ADCDC2 ADCDC1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 QVEEBIAS VEEBIAS VCCBIAS IREF50m V3P75V VCCPLL VEEPLL FREQ OSCNE OSCNB OSCPB OSCPE VCAP VDDPLL VSSPLL QVEEPLL QVEETX TQFP64 TXON November 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. TXOP 1/31 STLC1511 2.2 Pin Description Table 1. details the pinout assignment for the STLC1511. The following list gives the different pin types for the STLC1511. s s s s VDD/VCC - 5V power supply VEE/VSS - Ground supply DO/DI - Digital Output/ Digital Input AO/AI/AIO - Analog Output/ Analog Input/ Analog Input-Output Table 1. Pin Assignement Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Name VDDDIG1 CK35M DIGREF RXSOUT[0] RXSOUT[1] VSSDIGE1 VSSDIG2 VDDDIGE1 VDDDIG2 DTX DIGCLK ENB DRX VEEADC VCCADC QVEEADC ADCDC3 ADCDC2 ADCDC1 VSSESD1 VDDESD1 RXDCINP RXDCINN RXDCON RXDCOP RXINN RXINP Pin Type VDD DI DO DO DO VSS VSS VDD VDD DO DI DI DI VEE VCC VEE AIO AIO AIO VSS VDD AI AI AO AO AI AI Pad Type VDDCO TLCHT BT4CR BT4CR BT4CR VSSE VSSCO VDDE VDDCO BT4CR TLCHT TLCHT TLCHT VSSCO VDDCO VSSCO ANA ANA ANA VSSA VDDA ANA ANA ANA ANA ANA ANA Description 5V supply (digital) for ADC and DAC 35.328MHz serial interface clock input (also used in Test Mode to test PFD. See Table on page 21) 35.328/17.644MHz reference for Digital ASIC PLL Rx serial data (lsb) output Rx serial data (msb) output Ground for digital output drivers Ground supply for digital interface, serial interface 5 V supply for digital output drivers1 5 V supply for digital interface, serial interface Data Output for digital interface 35.328MHz clock input for digital interface Enable input for digital interface Data Input for digital interface Ground for ADC 5 V supply for ADC Quiet ground for ADC circuitry ADC reference decoupling (3.75 V) 0.1uF ADC reference decoupling (2.5 V) 0.1uF ADC reference decoupling (1.25 V) 0.1uF Ground for ESD ring 5 V supply for ESD ring RxPGA positive input from DC blocking capacitor RxPGA negative input from DC blocking capacitor RxPGA negative output to DC blocking capacitor RxPGA positive output to DC blocking capacitor Rx negative input (AC coupled) Rx positive input (AC coupled) 2/31 STLC1511 Table 1. Pin Assignement Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pin Name RXOPINN RXOPINP VCCRXPGA VEERXPGA QVEERX QVEEPLL VSSPLL VDDPLL VCAP OSCPE OSCPB OSCNB OSCNE FREF VEEPLL VCCPLL V3P75V IREF50m VCCBIAS VEEBIAS QVEEBIAS QVEETX TXOP TXON VCCTXPGA VEETXPGA VDDESD2 VSSESD2 VCCDAC VEEDAC TXDADC1 Pin Type AI AI VCC VEE VEE VEE VSS VDD AO AIO AIO AIO AIO AI VEE VCC AIO AIO VCC VEE VEE VEE AO AO VCC VEE VDD VSS VCC VEE AIO Pad Type ANA ANA VDDCO VSSCO VSSCO VSSCO VSSCO VDDCO ANA ANA ANA ANA ANA ANA VSSCO VDDCO ANA ANA VDDCO VSSCO VSSCO VSSCO ANA ANA VDDCO VSSCO VDDA VSSA VDDCO VSSCO ANA Description Rx opamp negative input (must be DC coupled) Rx opamp positive input (must be DC coupled) 5V supply for RxPGA Ground for RxPGA Quiet ground for Rx circuitry Quiet ground for PLL circuitry Ground for Oscillator2 5 V supply for Oscillator2 Charge pump output to varactor Oscillator I/O (emitter) Oscillator I/O (base) Oscillator I/O (base) Oscillator I/O (emitter) 2.56 MHz PLL input reference/ 35.328 MHz clock input Ground for oscillator2 5 V supply for oscillator2 3.75V output from Bandgap to 0.22mF capacitor External resistor for bias current R=2.5V/ 50mA=50kohm 5V supply for biasing Ground for biasing Quiet ground for bias circuitry Quiet ground for Tx circuitry Tx positive output Tx negative output 5V supply for TxPGA Ground for TxPGA 5V supply for ESD ring Ground for ESD ring 5V supply for DAC Ground for DAC DAC reference (2.5V) 0.1uF 3/31 STLC1511 Table 1. Pin Assignement Pin # 59 60 61 62 63 64 Pin Name QVEEDAC RESETN TXSIN[0] TXSIN[1] FRMCLK VSSDIG1 Pin Type VEE DI DI DI DO VSS Pad Type VSSCO TLCHT TLCHT TLCHT BT4CR VSSCO Description Quiet ground for DAC circuitry ResetN for the AFE Tx serial data (lsb) input Tx serial data (msb) input Tx 4.416MHz frame clock reference output Ground (digital) for ADC and DAC HCMOS5 guidelines are for 1 pair of power/ground for 4 output drivers (4mA) Pins 35 and 43 are both connected to the analog VCC supplying the on chip oscillator. Similarly, Pins 34 and 42 are connected to analog VSS for the oscillator. Supply line inductance is reduced using two pads for VCC (and VSS) in this manner. At the board level, Pins 35 and 43 should be connected to analog VCC, and pins 34 and 42 should be connected to analog VSS. 3.0 FUNCTIONAL DESCRIPTION 3.1 General Functional Description The STLC1511 consists of the following functional blocks: s Transmit Signal Path s s Receive Signal Path Phase Lock Loop and Amplifier for an external oscillator. Bias Voltage and Current Generation Digital Interface Serial Interface struct a PLL that generates either a 17.644MHz/ 35.328 MHz clock from a 2.56 MHz reference clock when supplied with an external LC or crystal oscillator and tuning circuit. This clock is supplied to the both the transmit and receive converters, and the serial interface used to transfer the Rx/Tx data between the STLC1511 and digital chip. The STLC1511 also has the ability to be driven directly by an external 35.328MHz clock supplied to the FREF pin. The bias circuitry contains a bandgap voltage reference from which the converter references and analog ground voltage is generated. This block also generates an accurate current using an external resistor from which all of the STLC1511 circuits are biased. In addition, the bias circuitry also generates a 2.5V reference for the external Vco/Vcxo components and can be used for other external circuits if necessary. There is a 4 pin serial digital interface (DTX, DRX, DIGCLK, ENB) that loads a one of four 8-bit control register that controls all the programmable features on the STLC1511. Refer to “Digital Interface And Memory Map” on page 20 for more information on the programmability of the AFE. To facilitate data transfer between the STLC1511 and the digital ASIC (STLC1510), a 2-bit wide serial interface for the transmit path and a 2-bit wide serial interface for the receive path is incorporated into the AFE. This interface consists of two transmit pins (TXSIN[0:1]), two receive pins (RXSOUT[1:0]), and the necessary control signals (FRMCLK, CK35M) to transmit the required data. For more information See “Serial Interface” on page 18. s s s The transmit path contains the 14-bit digital to analog converter (DAC) necessary to generate the transmit signal from a 14-bit digital input word. This transmit signal is then scaled by the on chip programmable gain amplifier (TxPGA) from 0 to -32dB in 2dB steps. The scaled output signal is then driven off chip to the external filters and power amplifier (PA) which drives the DMT signal to the subscriber loop. The transmit path is fully differential but may be used single ended if both outputs from the TxPGA are terminated correctly. The receive path contains an optional unity gain buffer followed by a two stage programmable gain amplifier (RxPGA), a 1st order low pass anti-aliasing filter, and a 12-bit analog to digital converter (ADC). The RxPGA consists of two stages and the gain is digitally programmable from 0 to 40dB in 0.5dB steps. The receive path is fully differential but may be used single ended provided the other input to the RxPGA is grounded. The STLC1511 contains the circuits required to con- 4/31 STLC1511 Figure 2. The block diagram of the STLC1511 IR E F 5 0 U B and gap/ Bias Gen 14 -bit DAC V 3P 5V TXDADC1 0.22uF 50k 0.1uF fp=2M H z TXON TXOP dig I/F T X SIN [1:0] 2 14 4.416M FRM CLK 2.56M /35.328M 2.56M (O scillator Mode) FREF 35.328M (External Clock M ode) Serial I/F CK 35M 8/4 35.328M/ 17.622M 2 /3 /4 /8 PFD CP R X S O U T [1:0] 2 5 69 G D IG R E F 4.416M OSCPE OSCNE R X IN N G =1 + fp=2M H z R X IN P + + + R X O P IN P R X O P IN N D ig ital I/F D IG C L K ENB DRX DTX 12 12 -b it ADC + - ADCDC2 0.1uF ADCDC1 0.1uF ADCDC3 RXDCOP Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode. 3.2 Receive Path Specifications Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps. 0.1uF RXDCON R E SE T N R X D C IN R X D C IP 0.1uF 0.1uF Re 90 ° so Ex n a tern to al r VCAP OSCNB OSCPB 5/31 STLC1511 Table 2. Receive Path Specifications Unless otherwise noted, typical specifications apply for VCC=5.0Volts, temperature=27×C, nominal process and current. Maximum and minimum performance is with VCC±±5%, -40=