STLC1512

STLC1512 NorthenLite™ G.lite Loop Driver PRODUCT PREVIEW s s s s s s s s s s s Low power architecture -- Class AB, current drive, output stage through a centre tapped transformer to facilitate power supply switching between 5.0V and a lower voltage. (3.3V in the reference design) This gives a reduction in power consumption. 480mW power consumption with a typical G.lite signal. 600mA current driving capability Positive +5.0V and one lower supply. (3.3V in the reference design) Switching power supplies to save power Thermal overload shutdown Four programmable receive gains Opamp for a low pass filter in the receive path Undedicated opamp with separate power down control (used as a transmit path filter in the reference design) Separate power down control for Tx and Rx path 48-pin TQFP (7x7x1.4mm) package TQFP48 (7x7x1.40) ORDERING NUMBER: STLC1512 1.0 GENERAL DESCRIPTION The STLC1512 G.lite line driver chip contains the line driver as well as part of the receive path required in a central office G.lite modem. It provides an interface between the AFE chip (STLC1511) and the telephone line. The line driver chip has been designed with low power consumption, high signal to noise plus distortion ratio and high current driving capability. Figure 1. Block Diagram DCFBON PAIN DCFBOP AMPIN AMPIP AMPOUT PAIP TXANG RBIAS REF2P5 RXANG RX REF Buffer LPF AMP TX REF Buffer Thermal Shutdown Preamp Power Stage OPAMP DC Feedback DCFBIP DCFBIN FPP PWRVEEx Amp PAOPx BUFFP BUFFN FPN PAONx BIAS RXPD AMPPD TXPD PGA LPFIN LPFOUT PGAIN PGA1 PGA0 PGAOUT November 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/26 STLC1512 1.0 GENERAL DESCRIPTION The line driver transmit path contains a preamplifier followed by a power output stage. The power stage has current outputs that directly drive the primary side of a center tapped transformer. The receive path contains a programmable gain amplifier followed by an opamp which is used with off chip passive components in an active low pass filter. The Programmable Grain Amplifier (PGA) has four steps optimized for the recommended G.lite CO line interface. There is also an undedicated opamp which can be used for active filtering in either the transmit or reFigure 2. STLC1512 pinout ceive paths 2.0 PACKAGING AND PIN INFORMATION 2.1 Package Technology STLC1512 will be packaged in a TQFP 48 package, according to JEDEC Specification reference MS026-BBC. 2.2 STLC1512 Pin Allocation The pin out for the STLC1512 is depicted in the following Figure 2. AMPOUT QVEETX TXVCC3 TXVCC2 TXVCC1 TXVEE1 TXVEE2 TXVEE3 DCFBIN DCFBIP AMPIN AMPIP DCFBON DCFBOP TXANG FPP FPN PAIP PAIN RBIAS REF2P5 NC LPFOUT LPFIN 48 1 QVEERX RXVEE1 RXVEE2 PGA1 PGA0 RXVCC2 RXVCC1 RXANG AMPPD PGAIN TXPD NC PWRVEE1 PWRVEE2 PAOP1 PAOP2 BUFFP TQFP48 (7x7x1.4mm) BUFFN PAON1 PAON2 PWRVEE3 PWRVEE4 RXPD 2/26 PGAOUT STLC1512 2.3 Pin Description The pin description for the STLC1512 is given in the following Table 1. Table 1. Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin Name PGAOUT PGAIN RXANG RXVCC1 RXVCC2 QVEERX RXVEE1 RXVEE2 PGA0 PGA1 TXPD AMPPD2 RXPD PWRVEE4 PWRVEE3 PAON2 PAON1 BUFFN BUFFP PAOP2 PAOP1 PWRVEE2 PWRVEE1 NC DCFBIN DCFBIP QVEETX TXVEE3 TXVEE2 TXVEE1 TXVCC1 AI AI VEE VEE VEE VEE VCC Pin Type AO AI AO VCC VCC VEE VEE VEE DI DI DI DI DI VEE VEE AO AO AO AO AO AO VEE VEE Pin Description1 Rx PGA output (programmable gain amplifier) Rx PGA input 2.5V Rx buffered reference +5.0V supply for Rx path circuitry +5.0V supply for Rx path circuitry Quiet ground for the Rx circuitry Ground for Rx path circuitry Ground for Rx path circuitry PGA gain setting control bit 0 PGA gain setting control bit 1 Tx path power down control (Active low) Undedicated opamp power down control (Active low) Rx path power down control (Active low) Power stage ground. Power stage ground. Tx Power Amplifier Negative output Tx Power Amplifier Negative output Current generator buffer negative output Current generator buffer positive output Tx Power Amplifier Positive output Tx Power Amplifier Positive output Power stage ground. Power stage ground. Not connected Power amp DC feedback amplifier negative input Power amp DC feedback amplifier positive input Quiet ground for Tx circuitry Ground for Tx path circuitry Ground for Tx path circuitry Ground for Tx path circuitry +5.0V supply for power amp output stage 3/26 STLC1512 Table 1. Pin Description 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TXVCC2 TXVCC3 AMPOUT AMPIN AMPIP DCFBON DCFBOP TXANG FPP FPN PAIP PAIN RBIAS REF2P5 NC LPFOUT LPFIN AO AI VCC VCC AO AI AI AO AO AO AO AO AI AI AO AI +5.0V supply for power amp output stage +5.0V supply for Tx path circuitry and bias blocks Undedicated opamp output Undedicated opamp negative input Undedicated opamp positive input Power amp DC feedback amplifier negative output Power amp DC feedback amplifier positive output 2.5V Tx buffered reference Fast path positive output Fast path negative output Tx Power amplifier positive input Tx Power amplifier negative input Reference resistor generating bias current Externally supplied 2.5V reference Not connected LPF (low pass filter) Op Amp output LPF (low pass filter) Op Amp negative input The values of the components that are connected to the pins are shown in Figure 11. If the undedicated opamp is used in the transmit path, AMPPD can be connected to TXPD on the board. If the undedicated opamp is used in the receive path, AMPPD can be connected to RXPD on the board. This opamp is powered off of TXVCC3. 3.0 FUNCTIONAL DESCRIPTION The STLC1512 consists of the following functional blocks: s Transmit Signal Path s s Receive Signal Path Thermal Protection The receive path consists of a Programmable Gain Amplifier (PGA) and an active low pass filter. The PGA is programmable in four steps. The active low pass filter is composed of an on chip op amp and external passive components. The receive signal passes through the PGA, is low pass filtered and then driven off chip to the AFE chip. Both the PGA and the opamp can be powered down by RXPD signal. A thermal protection circuit has also been implemented on the chip to prevent the chip from overheating under fault conditions. 4.0 SPECIFICATIONS 4.1 Chip Specifications The cross-talk specifications are based on the assumption that cross-talk should not degrade the SNDR of the receive signal. If there is receive crosstalk into the transmit path, this signal will come back through the hybrid balance and cause noise in the receive path. If the signal is undistorted it will cause a small gain and phase error which will not affect performance. If it is distorted it will cause an increased The transmit signal that comes from the AFE is filtered before it reaches the line driver. STLC1512 contains an opamp that can be utilized as part of this filter. The AMPPD pin allows this op amp to be powered down independently. The line driver consists of a preamp followed by a current drive power stage. The preamplifier provides large open loop gain while the power stage provides open collector current drive to allow for single supply switching. The center tap of the primary side of the transformer is connected to a supply that can be switched between 5.0V and a lower supply to realize power savings on a DMT signal. The reference design sets this supply at 3.3V. The line driver can be powered down by a low at the TXPD pin. 4/26 STLC1512 noise floor which will degrade the SNDR of the receive signal. The same is true of the transmit signal. If the signal is undistorted it will show up out of band in the receive path and will not degrade SNDR. However, if the Table 2. Chip Performance Specifications Description Rx Cross-Talk into Tx Undistorted Rx Cross-Talk into Tx Distorted Tx Cross-talk into Rx Undistorted min nom max -55 Units dB Comments Measured from the active low pass filter output in the receive path to tip and ring. Measured from the active low pass filter output in the receive path to tip and ring. Measured from tip and ring to the active low pass filter output with the maximum gain setting in place. Measured from tip and ring to the active low pass filter output with the maximum gain setting in place. transmit signal is distorted by the cross-talk mechanism it will show up in the receive band and could reduce the SNDR. The cross-talk numbers are specified from output to output under maximum gain conditions. -73 dB -50 dB Tx Cross-talk into Rx Distorted -86 dB 4.2 Power Amplifier Performance Specifications The power amplifier must be specified with all of the external components in the application diagram. Without these components the amplifier will not function correctly. Specifications that are measured at the chip are specified as such in the comments. Table 3 contains the conditions over which the specifications in Table 4 apply. The limits on the specifications in Table are valid over all of the ranges specified in Table 3. The nominal values of the specification occur at the nominal value of all of the conditions in Table 3 unless otherwise specified. ... Table 3. Power Amplifier Performance Limits Description Gain Ambient Temperature Line Impedance min 19.9 -40 80 nom 20.1 27 100 max 20.3 85 160 Units dB oC Comments1,2 W A nominal chip will have no problem driving 200 Ω or 50 Ω. Supply voltage for TXVCC 4.75 5.0 5.25 V Nominal specifications are for nominal bias and process Maximum and minimum specifications are for worst case process and bias conditions 5/26 STLC1512 Table 4. Power Amplifier Performance Specifications Unless otherwise specified nom specs apply to the nom conditions in attribute and the max and min conditions are defined by the process and other spec limits that give these worst case corners. Description Quiescent current at PAOP/ PAON1 min 10 nom 15 max 18 Goal Units mA Comments The spec is measured as the sum of the currents at POAP1+PAOP2 or PAON1+PAON2. Measured at the center tap of the transformer. Measured at pin PAIP/PAIN. This parameter cannot be measured very accurately. Measured at pin PAOP1,2/ PAON1,2 Total quiescent current at output stage2 Input bias current3 20 30 36 mA 15 µA Minimum Voltage at PAOP/ PAON 4 High Current Drive Minimum Voltage at PAOP/ PAON5 Low Current Drive Common mode input voltage range6 Peak output sink current on pin PAOP and PAON7 Power supply rejection Slew Rate8 Output referred noise voltage9 Signal to distortion ratio Two tone A10 Im2 @ 200 kHz Im3 @ 100 kHz Two tone B10 Im3 @ 550 kHz Output DS Multi-tone11 28kHz < f < 121kHz 151kHz < f < 541kHz 35 1.6 0.85 Vpeak 0.70 Vpeak Measured at pin PAOP1,2/ PAON1,2 VCC0.5 1000 V Measured at pin PAIP/PAIN 600 mA This is the sum of the current from PAOP1 and PAOP2 or the sum of the currents from PAON1 and PAON2 See Figure 3. V/µS nV/÷√Hz Measured across the 100 Ohm line impedance measured at f=120kHz Simulated to be good from 30kHz to 540kHz. Measured at the line impedance. The 4 to 1 transformer must have total harmonic distortion better than 50dB over 30kHz < f < 550kHz. The multi-tone spec is the important spec. The two tone specs exist because the test equipment may not be able to create a good enough multitone input signal. 78 120 78 78 59 78 59 85 66 86 86 59 86 59 dB dB dB dB dB 6/26 STLC1512 Table 4. Power Amplifier Performance Specifications Thermal shutdown junction temperature 12 130 150 175 oC Only the power amplifier is shut down under overheat condition The quiescent current is the current flowing into pin PAOP/PAON when there is no signal. This is the current drawn from the power supply that is connected to the center tap on the primary side of the transformer. This is the current flowing into the pin PAIN or PAIP when there is no signal. The nature of the test set up makes this quantity very difficult to measure. It is verified through simulation. This will allow the distortion specs to be met while driving a 160W line impedance. This applies for a 550mA output current. The worst case impedance for a nominal chip is 200 W. This spec is meant as an aid in calculating the proper switching point. It applies for a 225mA output current. This is a requirement on the input signal that allows the distortion spec to be met. It is not a testable parameter. The ran ge has been arrived at from simulations. The minimum sink current refers to peak signal current in normal operation. This is tested by placing a 80 W load as the lin e impedance and ensuring that the amplifier still passes the distortion tests. The maximum sink current refers to the current tha t will be delivered if tip and ring are shorted. A nominal chip can drive a 50W load while a worst case chip will drive 80W. Slew Rate spec is to guarantee that there is no slewing limit on a maximum amplitude sine wave at 540kHz. A 100 mV step is placed at the power amp input and the slew rate at the output of the amplifier is measured across the 100 Ohm load impedance. Measured across the 100 Ohm line impedance. This noise spec can be converted to dB/Hz through the following formula, e n x1000 N dB = 10 log ------------------------100 The effect of the noise in the receive path can be obtained by subtracting the hybrid balance number. Two tone distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale (for signal gain of 20.1dB, the full scale signal at power amplifier input is 1.05 Vp). The two tone distortion requirement is measured from the rms voltage of a single signal tone to the rms voltage of the distortion product. For the Two Tone A spec the tones are at f1=500KHz and f2=300KHz giving Im2=200kHz and Im3=100kHz. For the Two tone B the tones are at f1= 500kHz and f2=450kHz so that Im3=550kHz. A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms voltage ratio of 5.3 and an rms voltage equal to 208mV. Each tone will have a peak amplitude of 30.8mV) The multi-tone test measures the difference between the power of the test tones and the maximum power of a single distortion product in the given bands. The thermal shut down can not be directly tested in production. It will be investigated at bench and a correlation will be done hermal shutdown temperature. 2 7/26 STLC1512 Figure 3. Power Supply Rejection of the Power Amplifier1 W DB ( PAOUT ) -40 -60 dB -80 -100 3.00e+04 1.00e+05 6.00e+05 Hz This is a nominal specification. 6 dB of margin should be added to arrive at a worst case spec. 4.3 Programmable Gain Amplifier (PGA) Performance Specifications It should be noted that the PGA and LPF in the receive path must be AC coupled to avoid problems with amplifying any offsets. Both the PGA and the amplifiers are specified in terms of the silicon only. This is to allow the system design to be more flexible. The appendices show how to convert some of the silicon specs to system specs. Table 5. PGA performance Specifications Unless otherwise specified, NOM specifications apply for VCC=5.0V, temperature range outlined in Table 4.4, nominal process and bias current. MAX and MIN performances with 5% variation on VCC, -40