STLC2500ATR

STLC2500A BluetoothTM Single Chip Preliminary Data Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Lowest power consumption Efficient support for WLAN coexistence in collocated scenario Auto calibration (VCO, Filters) – No need for calibration of the RF part Total number of external components limited to 7 (6 decoupling capacitors and 1 filter) Bluetooth™ specification compliance: V1.1 and V1.2 Ericsson Technology Licensing Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Supports Pitch-Period Error Concealment (PPEC) Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment (master & slave) Faster connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range Extended SCO (eSCO) links HW support for ACL, SCO and eSCO packet types (see Overview) Clock support for all cellular standards: system clock input and low power clock ARM7TDMI CPU with 32-bit core and AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization: on-chip RAM & ROM Communication interfaces: UART, PCM and I2C interfaces and 4 programmable GPIOs ■ ■ ■ ■ ■ Standard TFBGA 84 pins package ■ ■ Ciphering support up to 128 bits key Software support up to HCI stack – H4 HCI Transport Layer – HCI proprietary commands and single HCI command for patch/upgrade download Single power supply with internal regulators Supports 1.65 to 2.85 Volts IO systems Timer and watchdog Power class 2. Power class 1 compatible (with external power amplifier) Ultra low power architecture with 3 different low power modes: sleep , deep sleep, complete power down Dual Wake-up mechanism: initiated by the Host or by the Bluetooth device ■ Description The STLC2500A is a single chip ROM-based Bluetooth solution implemented in 0.13 µm ultra low power, low leakage CMOS technology for mobile terminal applications requiring integration up to HCI level. Patch RAM is available, enabling multiple patches/upgrades. The STLC2500A offers multiple interface options. The radio has been designed for single chip requirements and minimal power consumption. ■ ■ ■ ■ ■ ■ ■ Order codes Part number STLC2500A STLC2500ATR Package TFBGA84 TFBGA84 Packing Tray Tape on Reel February 2006 Rev1 1/37 www.st.com 37 Contents STLC2500A Contents 1 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 4.2 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 5.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bluetooth controller 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bluetooth controller 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5.1 5.5.2 5.5.3 5.5.4 V1.2 detailed functionality - Extended SCO . . . . . . . . . . . . . . . . . . . . . . 18 V1.2 detailed functionality - Adaptive Frequency Hopping . . . . . . . . . . 18 V1.2 detailed functionality - Faster connection . . . . . . . . . . . . . . . . . . . 19 V1.2 detailed functionality - Quality of service . . . . . . . . . . . . . . . . . . . . 19 5.6 Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 6.2 6.3 6.4 6.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Low power clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/37 STLC2500A Contents 6.6 6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7.1 6.7.2 6.7.3 6.7.4 SNIFF or PARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Inquiry/Page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 No connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.8 6.9 6.10 6.11 Initiated deep sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Patch RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Download of SW parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Bluetooth - WLAN coexistence in collocated scenario . . . . . . . . . . . . . . . 26 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 Algorithm 1: PTA (Packet Traffic Arbitration) . . . . . . . . . . . . . . . . . . . . . 26 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 4: Two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Algorithm 5: Alternating Wireless Medium Access (AWMA) . . . . . . . . . 28 7 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 7.2 7.3 7.4 7.5 The UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 The PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 9 10 HCI UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package machanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/37 Overview STLC2500A 1 Overview The STLC2500A is a single chip ROM-based Bluetooth solution implemented in 0.13 µm ultra low power, low leakage CMOS technology for mobile terminak applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The STLC2500A main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes. The Radio is designed for the single chip requirement and for drastic power consumption reduction. Features ■ ■ ■ ■ ■ ■ Bluetooth™ specification compliance: V1.1 and V1.2 Ericsson Technology Licensing Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Supports Pitch-Period Error Concealment (PPEC) – Improves speech quality in the vicinity of interference like e.g. WLAN – Used with CVSD air coding – Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range Extended SCO (eSCO) links HW support for packet types – ACL: DM1, 3, 5 and DH1, 3, 5 – SCO: HV1, 3 and DV – eSCO: EV3, 5 Clock support – System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz – LPO clock input at 3.2, 16.384, 32 or 32.768 kHz ARM7TDMI CPU – 32-bit Core – AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization – On chip RAM, including provision for patches – On chip ROM, preloaded with SW up to HCI Communication interfaces – Fast UART – PCM interface – 4 programmable GPIOs – External interrupts possible through the GPIOs ■ ■ ■ ■ ■ ■ ■ ■ ■ 4/37 STLC2500A – Fast master I2C interface ■ ■ ■ Overview Efficient support for WLAN coexistence in collocated scenario Ciphering support up to 128 bits key Software support – Lower level stack (up to HCI) – HCI Transport Layer: H4 (including proprietary extensions) – HCI proprietary commands (e.g. peripherals control) – Single HCI command for patch/upgrade download Single power supply with internal regulators for core voltage generation Supports 1.65 to 2.85 Volts IO systems Total number of external components limited to 7 (6 decoupling capacitors and 1 filter) thanks to: – Fully integrated synthesizer (VCO and loop filter) – Integrated antenna switch – Low IF receiver Auto calibration (VCO, Filters) No need for calibration of the RF part Timer and watchdog Power class 2. Power class 1 compatible (with external power amplifier) Ultra low power architecture with 3 different low power levels: – Sleep Mode – Deep Sleep Mode – Complete Power Down Mode Initiated Deep Sleep Modes Dual Wake-up mechanism: initiated by the Host or by the Bluetooth device Standard TFBGA-84 pins package ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5/37 Electrical characteristics STLC2500A 2 Electrical characteristics VDD_IO_x means VDD_IO_A, VDD_IO_B. (See also Table 12, subsection Power supply). 2.1 Absolute maximum ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Table 1. Symbol VDD_HV Absolute maximum ratings Parameter Regulator input supply voltage Min. Vss - 0.3 Vss - 0.3 -0.3 Vss - 0.3 -65 Max. 4.0 4.0 0.3 4.0 +150 +250 Unit V V V V °C °C VDD_IO_x Supply voltage I/O Vssdiff Vin Tstg Tlead Maximum voltage difference between different types of VSS pins(1) Input voltage of any digital pin Storage temperature Lead temperature