STLC3080
®
SUBSCRIBER LINE INTERFACE CIRCUIT
MONOCHIP SLIC SUITABLE FOR PUBLIC
APPLICATIONS
IMPLEMENTES ALL KEY FEATURES OF
THE BORSHT FUNCTION
DUAL CONTROL MODE CONFIGURATION:
SLAVE MODE OR AUTOMATIC ACTIVATION
MODE.
SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME
ON HOOK TRANSMISSION
LOOP START/GROUND START FEATURE
WITH PROGR. THRESHOLD
LOW POWER DISSIPATION IN ALL OPERATING MODES
AUTOMATIC DUAL BATTERY OPERATION
INTEGRATED RING TRIP DETECTION WITH
AUTOMATIC AND SYNCRONISED RING
DISCONNECTION
METERING PULSE INJECTION
SURFACE MOUNT PACKAGE
THREE RELAY DRIVERS FOR RING AND
TESTING
BLOCK DIAGRAM
REL0 REL1 RELR RGND
MODE
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D0
D1
D2
R1
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ORDERING NUMBER: STLC3080
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-40 TO +85°C OPERATING RANGE
DESCRIPTION
The STLC3080 is a SLIC device suitable for a
wide range of applications: public (CO), transmission (DLC) and private (PABX). The SLIC provides the standard battery feeding with full programmability of the DC characteristic. In particular
two external resistors allow to set the limiting current value (up to 50mA) and the value of the resistive feeding when not in constant current region.
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CRT RT1 RT2 PCD
LINE STATUS
LOGIC
INTERFACE
&
DECODER
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TQFP44 (10 x 10)
ILT
SUPERVISION
TIP
LINE
INTERFACE
ILL
RING
COMMANDS
DET
GDK/AL
CSIN
AC+
DC
CSOUT
CKRING
AC
RES
VREG
+
ILTF
DC
TTXIN
ZB
REFERENCE
&
BIAS SWITCHING
AC
PROCESSOR
TX
RX
ZAC1
January 2004
BGND
ZAC
RS
CAC
IREF
VCC
VDD
RLIM
DC
PROCESSOR
AGND CREV CSVR VBAT BASE
RTH
RDC
D98TL305B
1/23
STLC3080
CSVR
BASE
VREG
BGND
RING
TIP
PCD
MODE
CKRING
DET
GDK/AL
PIN CONNECTION
44 43 42 41 40 39 38 37 36 35 34
CSOUT
1
33
CREV
CSIN
2
32
IREF
D0
3
31
RLIM
D1
4
30
RTH
D2
5
29
AGND
R0
6
28
RT1
R1
7
27
RT2
RES
8
26
ILTF
VDD
9
25
RDC
VCC
10
24
CAC
CRT
11
23
TTXIN
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ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VBAT
Battery voltage
VCC
Positive supply voltage
VDD
IREL
Control Interface Supply Voltage
Current into relay drivers
A/R/BGND
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RX
ZAC1
ZAC
RS
ZB
TX
VBAT
RGND
RELR
REL0
REL1
12 13 14 15 16 17 18 19 20 21 22
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-
AGND respect BGND respect RGND
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OPERATING RANGE
Symbol
Parameter
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TopT
VCC
Operating temperature range
Positive supply voltage
VDD
VBAT
Control Interface Supply Voltage
Battery voltage
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A/R/BGND
PD (70)
PD(85)
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D98TL306A
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if VREL > VCC
AGND respect BGND respect RGND
Max. power dissipation @ Tamb = 70°C
Max. power dissipation @ Tamb = 85°C
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Value
Unit
-80 + VCC to +0.4
-80 + VREL to + 0.4
-0.4 to +7
V
V
V
-0.4 to +7
80
V
mA
-2 to +2
V
Value
Unit
-40 to +85
4.75 to 5.25
°C
V
3 to 5.25
-73 to -15
-78 + VREL to -15
V
-0.3 to +0.3
V
V
V
1.1
0.9
W
W
Value
Unit
60
°C/W
THERMAL DATA
Symbol
Rth j-amb
2/23
Parameter
Thermal resistance Junction to Ambient
Typ.
STLC3080
PIN DESCRIPTION
Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
CSOUT
CSIN
D0
D1
D2
R0
R1
RES
VDD
VCC
CRT
REL1
REL0
RELR
RGND
VBAT
TX
ZB
RS
ZAC
ZAC1
RX
23
TTXIN
24
25
26
27
28
29
30
31
32
33
34
35
36
CAC
RDC
ILTF
RT2
RT1
AGND
RTH
RLIM
IREF
CREV
CSVR
BASE
VREG
37
38
39
40
41
42
43
44
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Description
Chip-Select for output control bits DET and GDK . Active Low. (*)
Chip-Select for input control bits latches D0 D1 D2 R0 R1 . Active Low. (*)
Control Interface input bit 0. (*)
Control Interface input bit 1. (*)
Control Interface input bit 2. (*)
Relay driver 0 command. Active High. (*)
Relay driver 1 command. Active High. (*)
Reset Input; active low.
Control interface Power Supply. VDD = 3.3V or VDD = VCC.
Positive Power Supply (+5V).
Ring-Trip time constant capacitor.
Relay 1 driver output.
Relay 0 driver output.
Ringer Relay driver output.
Relay drivers ground.
Negative Battery Supply.
4 wires output stage (Transmitting Port).
Cancelling input of Balance Network for 2 to 4 wires conversion.
Protection resistors image. The image resistor is connected between this node and ZAC.
AC impedance synthesis.
RX buffer output/ AC impedance is connected between this node and ZAC.
4 wires input stage (Receiving Port). A 100K external resistor must be connected to AGND to
bias the input stage.
Metering Signal Input (AC) and Line Voltage Drop Programming (DC). If not used must be connectd
to AGND.
AC feedback input/ AC-DC split capacitor is connected between this node and ILTF.
DC current feedback input. The RDC resistor is connected between this node and ILTF.
Transversal Line Current Image.
Input pin to sense ringing current , for Ring-Trip detection.
Input pin to sense ringing current , for Ring-Trip detection.
Analog ground.
Off-Hook threshold programming pin.
Limiting current programming pin.
Voltage reference output to generate internal reference current.
Reverse polarity transition time programming.
Battery supply filter capacitor.
Driver of the external transistor. Connected to the base.
Regulated voltage. Provides the negative supply to the power line drivers. It is connected to the
emitter of the external transistor.
Battery ground.
B wire termination output. IB is the current sunk into this pin.
A wire termination output. IA is the current sourced from this pin.
Power Cross Detection Input
Interface Control Mode selection.
Clock at ringing frequency for relay synch and time reference for Automatic activation
Off-hook and Ring-Trip detection bit. Tri-State Output/Active Low.
Ground-Key/Alarm detection bit. Tri-State Output. Active Low.
BGND
RING
TIP
PCD
MODE
CKRING
DET
GDK/ AL
* Input pins provided with 15µA sink to AGND pull-down.
3/23
STLC3080
CONTROL INTERFACE
Slave mode (MODE=Low).
INPUTS
R0
R1
D0
D1
D2
X
X
X
X
X
X
X
X
0/1
X
X
X
X
X
X
X
X
X
X
0/1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
X
OUTPUTS
DET
GDK/AL
(Active Low)
(Active Low)
disable
disable
gnd-key
off/hk
gnd-key
off/hk
gnd-key
off/hk
disable
ring/trip
disable
ring/trip
gnd-key
off/hk
disable
off/hk
def by D0-D2
def by D0-D2
def by D0-D2
def by D0-D2
OPERATING MODE
Power down
Stand-by
Active N.P.
Active R.P.
Ringing (with SLIC Active N.P.)
Ringing (with SLIC Active R.P.)
Ground start
High Impedance Feeding
Rel 0 (on = 1, off = 0)
Rel 1 (on = 1, off = 0)
A parallel interface allow to control the operation
of STLC3080 through a control bus:
- D0 D1 D2 latched input bits defining the Slic
operation mode
- R0 R1 latched input bits (active High) drive the
test relays.
- DET and GDK/AL , tri-state outputs, signal the
status of the loop: On/Off-Hook and Ground-Key.
Pin GDK/AL goes low also when the device
thermal protection is activated or a line fault (Tip to
Ring, Tip and/or Ring to Ground or VBAT) is
detected (flowing current ≥ 7.5mA).
-CSIN: chip select for input bits, active Low,
strobes the data present on the control bus into
the internal latch.
- CSOUT: chip select for output bits ; active Low ,
when high DET and GDK/AL goes tri-state.
D0 D1 D2 R0 R1 CSIN and CSOUT inputs are
provided with a 15µA pull-down current to prevent
uncontrolled conditions in case the control bus
goes floating.
According to the above table, 8 operating modes
can be set:
1) Power-Down.
2) Stand-By.
3) Active N.P.
4) Active R.P.
5) Ringing (with SLIC Active N.P.).
6) Ringing (with SLIC Active R.P.).
7) Ground start.
8) High Impedance Feeding.
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reduce the power consumption.
It is worth noticing that two other conditions can
set the Slic in idle state but with some differences
as reported in the table:
Idle State Rel0/1 Drive
Power Down
Enable
Reset
Thermal
Alarm
Disable
Enable
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DET
Disable
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Disable
Low
Disable
Low
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Stand-By.
Mode selected in On-Hook condition when high
immunity to common mode currents is needed for
the DET bit.
To reduce the current consumption, AC feedback
loop is disabled and only DET and GDK/AL detectors are active.
DC current is limited at 16mA (not programmable); feeding characteristic shown in fig. a.
The voltage drop in on-hook condition is 7.8V.
Figure a: STLC3080 DC Characteristic in
Stand-By Mode.
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16mA
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RFEED = 2RP
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D98TL307
Power-Down
It’s an idle state characterised by a very low
power consumption; any functionality is disabled;
only relays Rel0 and Rel1 can be driven by
proper setting of bits R0 and R1.
It can be set during out of service periods just to
4/23
GDK/AL
Disable
VBAT -7.8V
V
Active
Mode selected to allow voice signal transmission.
When in ACTIVE mode the voltage drop in onhook condition is 7.8V in order to allow proper onhook transmission (Fig. b).
STLC3080
Figure b. STLC3080 DC Characteristic in
Active Mode.
Ground Start.
This mode is selected when the SLIC is adopted
in a system using the Ground Start feature. In this
mode the TIP termination is set in High Impedance (100kΩ) while the RING one is active and
fixed at Vbat +4.8V. In the case of connection of
RING termination to GND the sinked current is
limited to 30mA. When RING is connected to
GND both Off-Hook and Ground-Key detectors
become active. Power dissipation in this mode
with a -48V battery voltage is 100mW
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ILIM [20÷50mA]
RFEED =
RDC
5
RFEED = 2RP
+2RP
VBAT
V
VBAT -7.8V
Resistive Region is programmable by means of
external resistor RDC, limiting current can be selected by RLIM resistor.
Concerning AC characteristic the STLC3080 allows
to set 2W termination impedance by means of one
external scaled impedance that may be complex.
Two to four wire conversion is provided by an external network. Such network can be avoided in case
of application with COMBOII, in this case the two to
four wire conversion is implemented inside the
COMBOII by means of the programmable Hybal filter.
When in ACTIVE mode it is also possible to perform battery reversal in soft mode (with programmable transition time) without affecting the AC signal transmission.
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Ringing
When Ringing mode is selected the STLC3080
activates the ring relay injecting the ringing signal
on the line. As the ring trip is detected the logic indicator DET is set low and the ringing is automatically disconnected without waiting for the card
controller command (auto ring trip).
DET remains latched Low untill the operative
mode is modified.
If required , the ringing relay drive signal RELR
can be synchronised to a clock applied to
CKRING input.
This clock is derived from the ringing signal with
proper time delay, according to the activation/deactivation time of the relay.
RELR is activated on the low level of CKRING
clock. The duty cycle of CKRING can be modified
in order to activate the RELR when required:
CKRING low must last 1µs minimum.
If the synchronisation is not required, CKRING input must be steadily kept Low.
All the STLC3080 relay drivers are open drain
with the source connected to the RGND pin. Each
relay drivers integrates a protection structure that
allows to avoid external kick - back diodes, using
both 5V or 12V relays.
The ring trip circuit and its behaviour is described
in Appendix D.
(s)
High Impedance Feeding.
As Stand-By, this mode is set in On-Hook condition, with further reduced power consumption.
Higher power efficiency turns back a lower immunity of the Off-Hook detector to line common
mode currents.
The DC feeding shows a constant current characteristic (Ilim = 17mA) followed by a resistive range
with an equivalent series resistance RFEED =
1600Ω + 2Rp.
Thermal protection circuit is still active, preventing
the junction temperature, in case of fault condition, to exceed 150°C
In High Impedance Feeding most of the circuit is
switched off, only the circuit, dedicated to OffHook detection, is powered. This allows to reduce
the total power consumption in On-hook to 30mW
(typical).
The Off-Hook detection threshold is not programmable but defined at a fixed IDETHI = 8mA(max.)
Figure c. STLC3080 DC Characteristic in High
Impedance Feeding
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17mA
RFEED = 1600Ω +2RP
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VBAT -0.8V
V
5/23
STLC3080
CONTROL INTERFACE
Automatic activation mode (MODE=High).
Inputs
D0
D1
0
0
0
0
0
1
R0
X
X
X
R1
X
X
X
D2
0
1
0
RES
1
1
1
X
X
0
1
1
1
X
X
1
0
0
1
X
X
1
0
1
1
X
X
1
1
0
1
X
X
1
1
1
1
0/1
X
X
X
0/1
X
X
X
X
X
X
X
X
X
X
1
1
0
Operating Mode
(Mode = High)
Power Down
Ringing
On-Hook Transmission
Reverse Polarity
On-Hook Transmission
Direct Polarity
Active Direct Polarity
(default)
Active Direct Polarity
(default)
Active Reverse Polarity
Active Direct Polarity
(default)
R0 = 0/1: Rel0 = off/on
R1 = 0/1: Rel1 = off/on
Power Down; Rel0/1 = off
Outputs
DET
GDK/AL
disable
disable
Ring-Trip
disable
Off-Hook
Fault
Fault
Off_Hook
Fault
Fault
Off_Hook
Fault
Fault
Off_Hook
Fault
Fault
Off_Hook
Fault
Fault
Off_Hook
Fault
Fault
(1)
(1)
(1)
(1)
disable
disable
DET: On/Off Hook Signalling ; together with GDK/AL it is set Low also in case of Thermal Alarm or Ground-Key.
GDK/AL : Thermal Alarm or Ground-Key Signalling
(1) : DET and GDK/AL signalling function is related to D0,D1,D2 and it doesn’t depend on R0 and R1 setting.
As in Slave mode the control is performed
through a parallel bus, with independent chip selects, CSIN and CSOUT, for inputs and outputs.
In Automatic Activation, once Active mode is selected the device automatically selects the proper
operating mode (Active, Stand By or H.I. feeding)
depending on the loop status in order to optimise
the power consumption.
In order to guarantee the proper behaviour of the
internal state machine the "CKRING" signal must
be always applied, this signal in fact is used to generate the "WTIME" delay (see Appendix) necessary
to properly perform automatic state change.
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Idle State Rel0/1 Drive
Power Down
Enable
Reset
Disable
Thermal
Enable
Alarm
DET
Disable
Disable
Low
GDK/AL
Disable
Disable
Low
Ringing
When Ringing mode is selected the STLC3080
activates the ringing relay injecting the ringing signal on the line.
6/23
As a Ring-Trip is detected the logic indicator DET
is set Low and the ringing relay is automatically
switched-off without waiting for the card controller command (auto ring-trip).
DET remains latched Low until the operative
mode is modified.
Ringing relay drive signal RELR must be synchronised to a clock applied to CKRING input. This
clock is derived from the ringing signal with
proper time delay, according to the activation /
deactivation time of the relay.
RELR is activated on the low level of CKRING
clock. The duty cycle of CKRING can be modified
in order to activate the RELR when required:
CKRING low must last 1µs minimum.
All the relay drivers are open-drain with the
source connected to RGND pin.
Each relay driver integrates a protection structure
to avoid external kick-back diodes using both 5V
or 12V relays.
The ring trip circuit and its behaviour is described
in Appendix D.
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Power-Down
It’s an idle state characterised by a very low
power consumption; any functionality is disabled;
only relays Rel0 and Rel1 can be driven by
proper setting of bits R0 and R1.
It can be set during out of service periods just to
reduce the power consumption.
It is worth noticing that two other conditions can
set the Slic in idle state but with some differences
as reported in the table:
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On-Hook Transmission.
Sets the Slic for conversation even though the line
is in On-Hook; it is required for On/Hook transmission purposes; Active mode cannot support a conversation when the line is in On-Hook as it automatically turns in High Impedance Feeding.
Active.
The relevant feature of this setting is that when
Active Mode (D0D1D2=1XX) is set by the external control , internally, the device is able to select
between three operative states according to the
status of the line:
STLC3080
- High Impedance Feeding :
entered after a Power-On Reset or 1XX word, this
status is set during steady On/Hook condition;
most of the circuitry is idle and only a low power
Off-Hook detection circuit is kept alive.
Direct Polarity only is assumed , independently of
the selected one.
To minimise the power consumption the Off-Hook detection circuit has low common mode current rejection.
- Stand by
Notice that in Stand-By state the Off-Hook detector is sensitive only to the transversal component
of the line current with high immunity to common
mode disturbances; this performance implies an
increasing in power consumption: for that reason
Stand-By is not used as a quiescent state.
- Active state gets operative for conversation after an Off-Hook validity check performed in
Stand-By state, set after any Off-Hook detected in
High Impedance Feeding.
If the Off-Hook condition is confirmed in Stand By,
Active mode is set ; if not (in case of spurious detection), false activation is prevented, and High
Impedance Feeding is resumed.
In order to have the device falling back in HI-feeding mode after the line is back in on-hook condition. It is necessary to select as input state the active direct polarity mode (default).
During Active state On/Off-Hook status will affect in real time DET signalling bit.
In order to allow Pulse-Mode Dialling, once Active state is set, it cannot be changed by fast OnHook , but it is turned back to High Impedance
Feeding only if an On-Hook condition lasts
longer than 128 x CKRING period.
Automatic activation (and deactivation) is based
on an internal state-machine which is clocked by
a free running internal oscillator.
A detailed description is reported in the Appendix A.
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both lightning and power-cross.
- Additionally, STLC3080 is provided with the
PCD input to directly monitor overvoltages applied to the line wires.
When the current injected into PCD exceeds a
threshold of 320µA (+/- 30%) , DET and GDK/AL
are set Low signalling a fault condition. No
change on the SLIC mode is performed.
Voltage threshold is defined by proper value of
the series resistors (see Fig.1)
Figure 1.
VCC
DET
R
TIP
PCD
GDK/AL
R
RING
CSOUT
Ith
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D98TL385
This circuit gives the possibility to protect the device against power crosses through a relay instead of PTCs; once the fault condition is detected the controller drives this relay
disconnecting the Slic from the line terminals.
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METERING PULSE INJECTION
STLC3080 provides external pins and components for Metering Pulse injection. TTXIN pin is
the input for the 12kHz or 16kHz Metering Pulse
injection. This pin also provides a DC constant
current source that is injected into the external
RDA resistor (typ. 10kΩ to obtain 2.2Vrms on
200Ω) connected between TTXIN pin and AGND.
The voltage drop across TIP and RING line amplifiers and, consequentally the AC swing available.
When Metering Pulse injection is not used and
voltage drop is not required, TTXIN must be
shorted to AGND and RTTX, RDA and CTTX external components must be removed. The TTX
cancellation is obtained through an external
RTTX and CTTX network connected between
TTXIN and CAC pins.
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DUAL BATTERY CONFIGURATION
STLC3080 is also meant for low power consumption systems using Dual Battery solution. It is sufficient to connect the collector of the external transistor, through a diode, to the reduced battery
(see Fig. 2 for single battery solution and Fig. 3
for dual battery solution). The activation of the
batteries is automatic, only depending on the DC
load at the RING and TIP terminals; no controllers
action is required.
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PROTECTION CIRCUIT
- Suggested protection circuit is based on programmable Trisils (like LCP1511/2) as shown
in Fig.2 and Fig. 3, and the surge current is
limited by the resistors RPT2 and RPR2, which
are PTC types , protecting the device against
Fault detection
The device provides current sense on TIP and
RING wires that allow to detect longitudinal DC
current (ILL). When this ILL current becomes
higher than a threshold (see detectors table inside electrical characteristics) a fault indication is
provided on DET and GDK pin (both outputs become low). The fault indication is active till the
fault cause persists. With this circuit the following
fault condition can be detected.
TIP to VB1
TIP to GND
RING to VB1
RING to GND
RING to TIP to VB1
7/23
STLC3080
EXTERNAL COMPONENTS LIST
To set the SLIC into operation the following parameters have to be defined:
- The DC feeding resistance "Rfeed" defined as
the resistance of the traditional feeding system (most common Rfeed values are: 400,
800, 1000 ohm).
- The AC SLIC impedance at line terminals "Zs"
to which the return loss measurements is referred. It can be real (typ. 600 ohm) or complex.
- The equivalent AC impedance of the line "Zl"
used for evaluation of the trans-hybrid loss
performance (2/4wire conversion). It can be a
complex impedance.
- The value of the two protection resistors Rp in
series with the line termination.
- The reverse polarity transition time defined as
"∆VTR/∆T".
- The constant current limit value "Ilim".
- Rth: sets the OFF/Hook DETection threshold
Once, the above parameters are defined, it is
possible to calculate all the external components
using the following table.
When a fault is detected the line current is limited
in order to avoid any damage on the device itself
and also on the external transistor.
MISCELLANEOUS
- Thermal overload: the integrated thermal protection is activated when Tj reaches 150°C typ.;
the Slic is forced in Power-down mode, DET
and AL are set Low. The RELR relay driver is
turned off while it is still possible to control
REL0 and REL1 through R0 and R1 inputs.
- One low cost external transistor allows to reduce the power dissipated in the SLIC itself allowing the use of extreme small size package
(TQFP44). The external transistor size/package
can be selected depending on the max. power
requested by the particular application.
- The SLIC supports loop start lines and gives
the possibility to set loop current indicator
threshold by means of one external resistor.
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EXTERNAL COMPONENTS
Name
Function
CVCC
Positive Supply Filter
CVB
Battery Supply Filter
RREF (*)
Formula
Internal current reference
programming resistor
1.16
IREF =
RREF
CSVR
Battery ripple rejection capacitance
CRT
Ring Trip capacitance
RDC
DC sinthesized resistance
programming resistor
CAC
AC/DC splitter capacitance
RS
Protection resistor image
t
c
u
od
r
P
e
ZA
s
b
O
CCOMP
b
O
CSVR =
1
2π ⋅ fp ⋅ 1.3MΩ
100nF ±20% 100V
30.1kΩ ± 1%
100nF ±10% 100V
@ fp = 1.22Hz
see Appendix D
470nF ±20% 6V
@ 25Hz
RDC = 5[Rfeed -2Rp]
RDC ≥ 1kΩ
1.5kΩ ±1%
CAC =
1
2π ⋅ fsp ⋅ RDC
10µF ±20% 15V
@ fsp = 10Hz
RS = 25 ⋅ 2Rp
2.5kΩ ±1%
2 wire AC impedance
ZAC = 25[Zs - 2Rp]
12.5kΩ ±1%
ZA = 25 ⋅ Zs
15kΩ ±1%
Line impedance balancing network
ZB = 25 ⋅ Zl
AC feedback compensation
capacitance
CCOMP =
15kΩ ±1%
2
2π ⋅ fo[100 ⋅ Rp]
220pF ±20%
@ fo = 250kHz
RR
Feeding resistance for Ring Injection
≥400Ω
600Ω 2W
RS1
Sensing resistor for Ring Trip
1000 ⋅ RR
600kΩ ±1%
RS2
Sensing resistor for Ring Trip
1000 ⋅ RR
600kΩ ±1%
RT
QEXT
Feeding resistance for Ring Injection
≥0Ω
0Ω
External transistor
(1)
BD140, MJD32
RPT1
Line series resistor
≥20Ω
RPR1
Line series resistor
≥20Ω
8/23
so
Typical Value
100nF ±20%
SLIC impedance balancing network
t
e
l
o
ZAC
ZB
(s)
e
t
le
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P
)
s
t(
20Ω 1/4W ±1%
STLC3080
EXTERNAL COMPONENTS (continued)
Name
Function
Formula
Typical Value
RLIM (*)
Current limiting setting resistor
1.16
RLIM = 103 ⋅
ILIM
23.2kΩ ÷ 58kΩ
51.1kΩ
±1%
RTH (**)
OFF/HOOK DETection threshold
setting resistor.
RTH = 200 ⋅
1.16
ITH
21.1kΩ ÷ 77.3kΩ
26.1kΩ
±1%
CREV
Polarity reversal transition time
programming
CREV =
RDA
Output Voltage Drop Adjustment
RDA =
R1, R2
K
1
; K=
3750
∆VTR
∆T
47nF for 5.67V/ms
∆Drop ⋅ 20kΩ
9.6 − ∆Drop
10kΩ (∆Drop = 3.2V) (2)
Power Cross Detection
240kΩ
RTTX
Teletax Cancellation Resistor
CTTX
Teletax Cancellation Capacitor
RTTX = 12.5 ⋅ [Re (ZLTTX) + 2RP]
CTTX =
RPT2
Protection resistor
≥ 8Ω
RPR2
Protection resistor
≥ 8Ω
D1
Overvoltage protection
D2
Dual Battery Operation
CH
Trans-Hybrid Loss Frequency
Compensation
(3)
3.75kΩ
1
(12.5 ⋅ Im (ZLTTX) ⋅ 2π ⋅ fTTX)
c
u
d
)
s
t(
20Ω 1/4W ±1%
o
r
P
20Ω 1/4W ±1%
1N4448
e
t
le
CH = CCOMP
1N4448
220pF ±30%
o
s
b
O
-
Notes:
(1) Transistor characteristics: hFE ≥ 25, IC ≥ 100mA, VCEO ≥ 60V, fT ≥ 20MHz in all operating range (Ic from 1 to 100mA). PDISS depends on
application, see Appendix.
For SMD application possible alternatives are MJD350 in D-PACK or BCP53 in SOT223
(2) Typical value needed for 2.2Vrms metering pulse level, if no metering RDA = 0Ω.
(3) These resistors are needed to activate the power cross detection circuit, they should withstand the typical lighting voltage. If the power
cross detection is not needed R1, R2 can be avoided.
(*) RREF and RLIM should be connected close to the corresponding pins of STLC3080.
Avoid any digital line or high voltage swing line to pass close to IREF and RLIM pins. Eventually screen these pins with a GND track.
(**) Inside the formula the coefficient 1.16 must be changed to 1.20 if the selected value of Ith is lower than 5mA.
)
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9/23
STLC3080
Figure 2. Typical application diagram.
CVCC
ZAC1
ZAC
VCC
VDD
VREL
VDD
VCC
AGND
BGND
RGND REL0
REL1 RELR
RT
PCD
ZAC
RS
RS
CCOMP
RX
TX
TX
RPT1
LA
VB-
ZB
ZB
RPR1
MODE
MODE
D1
D1
D2
D2
R0
R0
R1
R1
DET
GDK/AL
CSIN
CSOUT
RT1
RS1
DET
VREG
GDK/AL
BASE
CSIN
VBAT
CVB
CKRING
TTX
TTXIN
RDA
CAC
ILTF RDC
CRT
IREF
RTH
RLIM
RDC
RREF
CRT
RLIM
RTH
ZAC1
ZAC
VCC
e
t
le
RX
RX
bs
CONTROL
INTERFACE
O
TX
r
P
e
t
e
l
o
D2
ZB
(2)
LB
RS1
RT2
VREG
GDK/AL
BASE
CSIN
VBAT
D1
VB-
CVB
CAC
ILTF RDC
CRT
RDC
CAC
(1) This components are needed only for Power Cross Indication (normally not used).
(2) Components needed only for Metering pulse injection.
IREF
CRT
RLIM
RREF
RLIM
D2
VRING
VB-
VB2
CSVR
RTTX
CTTX
RR
RS2
+
10/23
RPR2
RT1
DET
TTXIN
RDA
LCP
1511
RPR1
CKRING
TTX
RPT2
RING
STLC3080
CREV
RTH
RTH
R1(1)
LA
VB-
RES
CKRING
R2(1)
RPT1
CSOUT
RES
RT
PCD
TIP
D1
R1
CSOUT
REL1 RELR
D2
R1
CSIN
RGND REL0
VREL
D0
R0
GDK/AL
BGND
MODE
R0
DET
(s)
AGND
od
TX
D1
VDD
CSVR
o
s
b
O
-
t
c
u
RS
CCOMP
VDD
VCC
ZAC
RS
)
s
t(
o
r
P
CREV
CAC
Figure 3. Typical dual battery application diagram.
CVCC
c
u
d
CREV
(1) This components are needed only for Power Cross Indication (normally not used).
(2) Components needed only for Metering pulse injection.
D0
VB-
D98TL308C
RTTX
CTTX
MODE
VRING
VB-
CSVR
+
ZB
RR
RS2
RT2
RES
CKRING
(2)
STLC3080
CSOUT
RES
CH
LB
QEXT
CONTROL
INTERFACE
RPR2
RING
D0
D0
ZA
LCP
1511
D1
CH
R1(1)
RPT2
TIP
QEXT
ZA
RX
R2(1)
CREV
CSVR
D98TL310C
STLC3080
ELECTRICAL CHARACTERISTICS (Test Condition, unless otherwise specified: VCC = 5V, VDD = 3.3V,
VB- = -48V, AGND = BGND = RGND, Tamb = 25°C).
Note: the limits below listed are guaranteed with the specified test condition and in the 0 to 70°C temperature range. Performances over -40 to +85°C range are guaranteed by product characterisation.
Symbol
Parameter
AC CHARACTERISTICS
Zil
Long. Impedance
Long. Current Capability AC
Iil
L/T
Long. to transv.
T/L
Transv. to long
2wRL
THL
Ovl
2W return loss.
trans-hybrid loss.
2W overload level
TXoff
G24
G42
G24fq
TX output offset
Transmit gain abs.
Receive gain abs.
tx gain variation vs.
frequency
rx gain variation vs.
frequency
Tx gain variation vs. level
Rx gain variation vs. level
idle channel noise at line
terminals
idle channel noise at TX port
G42fq
G24lv
G42lv
V2wp
V4wp
Thd
GTTX
od
uc
total harm. dist. 2w-4w, 4w2w
Transfer Gain
r
P
e
Test Condition
Min.
each wire
H.I. feeding per wire (ONHOOK)
STANDBY or ACTIVE per
wire (ON-HOOK)
ACTIVE per wire (OFFHOOK). IT = Transversal
Current
NP with nominal RP at 300Hz
NP with nominal RP at 1020Hz
NP with nominal RP at 3400Hz
NP with nominal RP at 300Hz
NP with nominal RP at 1020Hz
NP with nominal RP at 3400Hz
300 to 3400Hz
1020Hz; 20Log |VRX/VTX|
ACTIVE MODE at line
terminals on ref. imped.
0dBm 1020Hz
0dBm 1020Hz
rel. 1020Hz, 0dBm 300 to
3400Hz
rel. 1020Hz, 0dBm 300 to
3400Hz
f = 10120Hz, input level
from 3dBm to -40dBm
(t s)
Typ.
Max.
Unit
40
5
Ω
mApk
13
mApk
80 -IT
mApk
60
60
55
37
40
40
22
30
3.2
uc
d
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P
e
let
o
s
b
O
-
-200
-12.38
5.74
-0.1
O
)
s
t(
C6
C2
mV
dB
dB
dB
-0.1
0.1
dB
-0.1
-0.1
-82
0.1
0.1
-78
dB
dB
dBmp
C8
-90
-84
dBmp
C7
-50
dB
14.5
t
e
l
o
bs
C5
200
-12.02
6.1
0.1
psophometric, Active On
Hook
psophometric, Active On
Hook
0dBm, 1KHz Il = 20 to
45mA
VTTX = 100mVRMS @ 16kHz
VL
GTTX = 20Log
VTTX
with RL = 200Ω
THD (TTX) TTX Harmonic Distortion
2.2VRMS = on 200Ω
DC CHARACTERISTICS (TTX pin connected to ground)
Vlohi
Line voltage
Il = 0, H.I. feeding
Vlo
Line voltage
Il = 0, SBY/ACTIVE/ONHOOK
Ilims
Short circ. curr.
Rloop = 0, SBY
Ilimb
Short circ. curr.
Rloop = 0, H.I. feeding
Ilima
Lim. current accuracy
Rel to progr. val. 20 to 50mA
ACTIVE NP, RP
VIREF
Bang up reference
Rfeed
Feed res. accuracy
ACTIVE NP, RP
Rfeed H.I. Feeding resistance
H.I. feeding
dB
dB
dB
dB
dB
dB
dB
dB
dBm
Fig.
C4
C1
dB
3
%
47
38.9
47.4
39.9
47.8
40.9
V
V
14
11
-10
16
17
18
20
10
mA
mA
%
1.08
-10
1100
1.16
1.24
10
2100
V
%
Ω
11/23
STLC3080
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Ilact
Ilsby
Parameter
Feed current ACTIVE
Feed current STBY
ITIP
IGS
IDA
Tip leackage current
Ring Lead Current
Reference current sourced
by TTX IN pin for Voltage
Drop programming
DETECTORS
Idet
Off-hook current threshold
ST-BY, ACTIVE
Idet H.I.
Hys
Td
ILL
Test Condition
ACTIVE NP, RP
Rloop = 1900Ω RDC = 1.5kΩ
STY, Rloop = 2.2KΩ
RDC = 1.5kΩ
Ground Start
Ground Start Ring to GND
VTTX = 0V
Min.
18
Rel. to progr. val. 7 to 11mA
Rel. to progr. val. 3 to 6mA
H.I. feeding
ST-BY, ACTIVE
ACTIVE
TIP to RING to GND or
RING to GND
-10
-20
5
Off-Hook current threshold
Off/On hook hyst.
Dialling distortion
Ground Key Current
threshold
ILL = IB - IA
Igst
Ground Start detection
Igst = 2 ⋅ Idet
threshold
GROUND START
DIGITAL INTERFACE
INPUTS: D0, D1, D2, R0, R1, CSIN, CSOUT
Vih
Input high voltage
VDD = 3.3V
Vil
Input low voltage
VDD = 3.3V
Iih
Input high current
Iil
Input low current
OUTPUTS: DET, GDK /AL
Vol
Output low voltage
Iol = 0.75mA; CSOUT = LOW
Voh
Output high voltage
Ioh = 0.1mA; CSOUT =
LOW
IOZ
Tri-State Output Current
CSOUT = High
OUTPUTS: RELR, REL0, REL1
Ird
Current capability
Vr
Output voltage
Ird = 40mA
Ird = 70mA
Iik
Off leakage current
POWER SUPPLY REJECTION
Vripple = 0.1Vrms
PSRRC
VCC to 2W port
50 to 4000Hz
PSRRB
Vbat to 2W port
Vripple = 0.1Vrms
50 to 4000Hz
POWER CONSUMPTION
ICC
VCC supply current
H. I. Feeding On-Hook
From 0 to 70°C
From -40 to 85°C
SBY On-Hook
From 0 to 70°C
From -40 to 85°C
Active On-Hook
From 0 to 70°C
From -40 to 85°C
Power Down
From 0 to 70°C
From -40 to 85°C
Typ.
20
13
1
-70
33
-60
)
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12/23
-45
+10
+20
8
15% Idet
-1
+1
7.5
-10
2
Fig.
µA
mA
µA
%
%
mA
mA
ms
mA
uc
+10
d
o
r
0.8
30
10
)
s
t(
%
V
V
µA
µA
0.5
V
V
+10
µA
0.6
1.1
3
mA
V
V
µA
2.4
-10
Unit
mA
mA
P
e
let
o
s
b
O
-
Max.
40
27
dB
C9
30
dB
C9
1.0
1.5
mA
mA
3.5
4
mA
mA
5.0
5.5
mA
mA
1.0
1.5
mA
mA
STLC3080
ELECTRICAL CHARACTERISTICS (continued)
Symbol
IBAT
Parameter
VBAT supply current
IDD
Test Condition
H. I. Feeding On-Hook
From 0 to 70°C
From -40 to 85°C
SBY On-Hook
From 0 to 70°C
From -40 to 85°C
Active On-Hook
From 0 to 70°C
From -40 to 85°C
Power Down
From 0 to 70°C
From -40 to 85°C
Any operating mode
VDD Supply Current
Min.
Typ.
100
Max.
Unit
0.5
1.0
mA
mA
2.5
3.5
mA
mA
4.5
5.0
mA
mA
0.5
1.0
320
mA
mA
µA
Fig.
LOGIC INTERFACE INPUT TIMING
t1
Min.
100ns
100ns
250ns
t1
t2
t3
t4
t5
t6
Max
t3
c
u
d
CSIN
D0.1.2,R0.1
100ns
100ns
CSOUT
e
t
le
250ns
t2
)
s
t(
o
r
P
DET, GDK
o
s
b
O
-
t4
t6
t5
D98TL312
Note: All measurements are performed with 100pF on outputs pin and with TTL compatible voltage levels.
)
s
(
ct
Figure 4. Test Circuit.
VCC
du
VCC
ZAC1
ZA
15KΩ
o
r
P
e
CCOMP
220pF
t
e
l
o
CH
220pF
O
bs
RS 2.5KΩ
ZB
15KΩ
CONTROL
INTERFACE
RX
TX
MODE
D0
ZAC
R1
R1
RT
PCD
LA
RPR1 20Ω
RPR2 30Ω
RING
STLC3080
LB
RT1
RS1 600KΩ
RR
600Ω
RS2 600KΩ
RT2
DET
VREG
GDK/AL
BASE
CSIN
VBAT
D1
1N4448
CSOUT
RES
CKRING
CKRING
TTX
TTXIN
CAC
RTTX
3.75K
RPT2 30Ω
RPT1 20Ω
TIP
D0
R0
RDA
10K
VREL
RELR
MODE
R0
RES
REL1
ZB
D1
CSOUT
RGND REL0
TX
D2
CSIN
BGND
RS
D2
DET
AGND
RX
D1
GDK/AL
VDD
QEXT
BD140
ZAC
12.5KΩ
VDD
CSVR
VRING
VBVB-
CREV
ILTF RDC
CAC
+
RDC
1.5KΩ
IREF
CRT
CRT
470nF
RLIM
RREF
30.1KΩ
RTH
RLIM
RTH
CREV
47nF
CSVR
100nF
D98TL313G
CTTX 1µF 10µF
13/23
STLC3080
APPENDIX A
The flow-chart in Fig.A1 describes the sequence
of state machine supervising the STLC3080 operation when the control is set for Active mode,
D0 D1 D2= 1 X X.
The state machine is a synchronous sequential
circuit internally clocked by a free running oscillator ; the ringing frequency applied at the CKRING
input is used to generate the long time delay
WTIME=128xCKRING necessary for proper operation as further described.
External control is supposed to be set for Active
mode :
D0 D1 D2= 1 X X.
OH-HI : line status flag , set High when Off-Hook
condition is detected in High Impedance Feeding;
it differs from OHK because it’s sensitive to the
longitudinal current.
OHK: line status flag , set High when Off-Hook
condition is detected in Stand-By or in Active
mode; it differs from OH-HI for its immunity to longitudinal current .
DLY: time-out flag, it is set High to resume, with
a given delay, the High Impedance Feeding when
an On-Hook condition (OHK=Low) is detected in
Stand-By or Active state.
1) Note that in this section the word "mode" has
been used to indicate the operating status set
with D0, D1 and D2 pin: the word "state" has
been used to indicate an internal status of the
finite state machine.
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14/23
c
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Flow-chart Description
H) A Reset condition, generated at Power On or
setting RES pin Low, forces a Power-Down
condition.
A) High Impedance Feeding is entered after the
Active mode word is set and its maintained un-
)
s
(
ct
til an Off-Hook condition is detected (OHHI=High) ; in this case Stand-By state entered.
B) Stand-By state is set to perform a validity
check of the Off-Hook status of the line before
entering Active state. If it is confirmed
(OH=High), immediately Active state is entered.
If not , Stand-By state remains set for a time
period WTIME generated through a counter
that times out after 128 x CKRING ; DLY=High
signals the state machine the time out to resume the High Impedance Feeding.
An OHK = High detected during WTIME will immediately enter Active state.
C) Active state is set for conversation and
DET=Low signals to the controller the Off-Hook
condition of the line.
The status remains set as long as OHK=High
(Off-Hook).
D) When OHK=Low is detected (On Hook), DET
is immediately set High whereas Active state is
maintained for the period WTIME; when it expires DLY is set High and High Impedance
Feeding is resumed.
If, during WTIME, OHK=High is detected Off
Hook), the state is returned to C) , i.e. Active
with DET=Low.
E) Ringing mode is set when D0 = D1 = 0 and D2 = 1.
After ring trip detection the SLIC is automatically set in Active state (reverse or normal polarity according to D2 value set before ringing
mode). Ring trip detection is indicated by DET
pin: when it happens the SW must remove the
ringing mode word (001) and set the Active
mode word (100).
F) On-Hook Tx mode is selected when D0 = 0,
D1 = 1 and D2 = X.
After Off Hook detection the SLIC is automatically set in Active state.
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STLC3080
Figure A1.
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15/23
STLC3080
APPENDIX B
STLC3080: allowed Rfeed values vs. Ilim
The STLC3080 device has been designed in order to fit in a small SMD package (TQFP44). This
target has been achieved by using a dedicated
circuit for power management based on one external transistor (Qext).
The particular power management circuit adopted
allows to define the percentage of power dissipated on the SLIC itself and on the Qext. The
sharing percentage is defined by the Rfeed value,
in particular the higher is Rfeed, the higher is the
percentage dissipated on the SLIC.
Rfeed represents the DC feeding impedance at
TIP/RING terminals (including 2xRp) when the
SLIC is in the resistive feed region of the DC
characteristics.
Since the max. power dissipation inside the SLIC
is limited it is important to know which value of
Rfeed can be implemented without exceeding the
max power allowed in the SLIC.
In order to define the allowed Rfeed values several other parameters should be considered, in
particular:
Pdslic:
Max allowed power dissipation on SLIC, two values are considered:
1.1W for 70°C Tamb application;
0.9W for 85°C Tamb application;
Pdqext:
Max allowed power dissipation on Qext, three values are considered:
1.0W
)
s
(
ct
1.5W
2.0W
These values depend on the package and the assembly of the Qext.
Ilim:
Programmed constant current value, continuous
variations are considered from 20mA to 50mA.
Vbat:
Battery voltage, three values are considered:
48V
54V
62V
The following diagrams show the allowed Rfeed
values depending on the above parameters. three
diagrams are shown each one for a particular battery (Vbat = -48V, -54V, -60V).
In each diagrams you can find an upper and a
lower limits for the Rfeed value:
The upper limit is defined by one of the two b1, b2
curves.
b1 is the limit when max. power on SLIC is
equal to 0.9W (Tamb = 85°C)
b2 is the limit when max. power on SLIC is
equal to 1.1W (Tamb = 70°C)
The lower limit is defined by one of the three a1,
a2, a3 curves.
a1 is the limit when max. power allowed on
Qext is equal to 1.0W
a2 is the limit when max. power allowed on
Qext is equal to 1.5W
a3 is the limit when max. power allowed on
Qext is equal to 2.0W
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16/23
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Figure B1. Rfeed allowed values vs. Ilim (Vbat = -48V).
u
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STLC3080
Figure B2. Rfeed allowed values vs. Ilim (Vbat = -54V).
c
u
d
Figure B3. Rfeed allowed values vs. Ilim (Vbat = -60V).
)
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(
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)
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EXAMPLE:
Considering the following parameters:
Vbat = -48V, max Tamb = 70°C, Ilim = 25mA,
Qext able to dissipate 1W, the possible values of
Rfeed can be found in fig. 1 and are limited by the
b2 curve (upper limit) and the a1 curve (lower
limit).
In particular considering the Ilim = 25mA the
Rfeed allowed range will be:
500Ω < Rfeed < 1700Ω
17/23
STLC3080
APPENDIX C
STLC3080 Test Circuits referring to the application diagram shown in figure 4 and using as external components the typ. values specified in the
"External Components", find below the proper
configuration for each measurement.
Figure C1. Receive Gain.
Figure C2. THL Trans Hybrid Loss.
TIP
300
Rp
TX
TIP
STLC 3080
Vl
STLC 3080
300
test circuit
Vtx
test circuit
VL
300
TX
300
RX
RING
Figure C3. T/L Transversal to Longitudinal
Conversion
TIP
so
test circuit
300
RX
RING
)
s
(
ct
T/L = 20log (Vl / Vtl )
b
O
-
r
P
e
t
e
l
o
Figure C5. L/T Longitudinal to transversal
Conversion.
TIP
Vac
L/T = 20log ( E / Vac )
18/23
TX
Vtx
STLC 3080
RX
RING
Figure C6. 2W Return Loss.
TIP
TX
TX
RING
STLC 3080
1000
test circuit
test circuit
E
E
300
TIP
G24 = 20log (2Vtx / E )
STLC 3080
10uF
o
r
P
test circuit
E
600
300
)
s
t(
Vrx
u
d
o
s
b
O
e
t
le
600
TX
STLC 3080
Vl
c
u
d
Figure C4. Transmit Gain.
Rp
Vtl
Vrx
THL = 20log (Vrx /Vtx )
G42 = 20log (Vl / Vrx )
300
RX
RING
Rp
Vrx
RX
1000
Vs
RING
2WRL = 20log ( E / 2Vs )
RX
STLC3080
Figure C7. Idle channel psophometric noise
at TX port.
TIP
TX
TIP
STLC 3080
600
Figure C8. Idle channel psophometric noise
at line terminals.
Vtx
Vtx
STLC 3080
test circuit
Vl
600
test circuit
RX
RING
TX
RX
RING
V2wp = 20log (Vl / 0.775V )
V4wp = 20log (Vtx / 0.775V )
Figure C9. PSRRC = Power Supply Rejection VCC to 2W Port
PSRRB = Power Supply Rejection VBAT to 2W Port
TIP
STLC 3080
test circuit
Vl
600
e
t
le
Vbat/Vcc
o
s
b
O
-
PSRRC = 20log (VnVcc / Vl )
)
s
(
ct
o
r
P
RX
RING
PSRRB = 20log (VnVbat / Vl )
c
u
d
TX
)
s
t(
Vn = 0.1Vrms
u
d
o
r
P
e
t
e
l
o
s
b
O
19/23
STLC3080
APPENDIX D
RINGING MODE AND RING TRIP DETECTION
component by integrating the line current: the detection threshold can be reached only if the line
current has a DC component higher than the
threshold. As a consequence the response is not
immediate (as it is for off-hook in Active state): it
takes an amount of time that is dependent on the
DC current value (i.e. on the line length). The AC
rejection and the delay depend on the CRT capacitor value (see Fig.D1).
When the voltage on the capacitor exceeds 3V,
the Ring-Trip is detected (see fig.D3). CRT
should be selected in order to avoid that during
one half sinewave cycle, in on-hook, its voltage
VCRT exceeds 3V (ring-trip threshold). The minimum value of CRT can be carried out with the following formula:
In ringing mode the STLC3080 provides:
- Relay driver capability (relay is synchronized
with low level of CKRING)
- Ring-Trip detection
The monitor of the line state is performed by
sensing the line current converted into a voltage
drop across the RR resistor connected in series
to the line. This voltage is read via RS1and RST2
input pins of a differential stage that identifies,
during the ringing phase, the ON/OFF HOOK
state of the line (see Fig. D1).
The Ring-Trip condition is detected by sensing
the DC component of the line current, rejecting
the AC component. With RR = 600Ω the RingTrip threshold is: Iline>7.5mA
When the Ring-Trip is detected, the STLC3080:
- deactivates the ringing relay RELR (if CKRING
is low);
- indicates the ring-trip detection by setting
DET=low;
- forces the Active state.
The information at RELR and DET pins is lached
and it doesn’t change opening the current loop.
To reset the latched informations the Active or
On-Hook Transmission mode have to be entered
(in general changing the device mode the latched
information is removed).
Although the ring-trip detection sets DET to signal
the line status, there is a substantial difference respect to the on/off-hook detection. In Ringing
mode on-hook condition, an AC current is present
on the line. The ring-trip detector rejects the AC
)
s
(
ct
u
d
o
Ccrt > 6µF/Fring
c
u
d
With Fring = 20Hz, you obtain a Ccrt = 390nF.
When the CRT capacitor is selected, it must be
considered that it is also used for the rejection of
the common mode current. In this case the minimum value of the CRT capacitor can be carried
out with the following formula:
e
t
le
so
o
r
P
Ccrt > (Ip/Fl) ⋅ 560µF
b
O
-
Where Ip is the peak of the longitutudinal current
and Fl is the frequency of this current. With Ip =
25mA @ Fl = 50Hz you obtain 330nF.
For this reasons the suggested value for typical
central office application is 470nF.
Figure D1.ring trip circuit block diagram.
r
P
e
t
e
l
o
s
b
O
VCC
ILINE
Ith=7.5uA(typ)
RS1
IRING
RR
ICRT
RS2
CRT
VB
20/23
IRING=ILINERS1/RR
RS1=RS2
)
s
t(
COMP
3Volt
DET
STLC3080
Figure D2. relation between Icrt and Iline.
ICRT
+30uA
ILINE
ILINEth=7.5mA(typ)
(if RR=600Ω and RS1=RS2=600KΩ)
ILINEth=IthRS1/RR
-30uA
RS1 must be connected to the positive RR; RR
should be connected directly to the ringing generator as it is in the figure. The ratio between RS1
and RR must be chosen considering that there is
an offset current in the input stage equal to
7.5µA. This offset has been introduced to take in
account the leackage current of the line.
In fig.D2 is shown the relation between the CRT
charging current ICRT and the line current ILINE. In
the range -30µA
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