STLC5046

® STLC5046 PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER PRODUCT PREVIEW PROGRAMMABLE MONOLITHIC 4 CHANNEL CODEC/FILTER SINGLE +3.3V SUPPLY PIN STRAP / MCU CONTROL MODE A/µ LAW PROGRAMMABLE LINEAR CODING (16 BITS) OPTION PCM HIGHWAY FORMAT AUTOMATICALLY DETECTED: 1.536 or 1.544MHz; 2.048, 4.096, 8192 MHz TX GAIN PROGRAMMING: 16dB RANGE; 00h:Digitalgain is inserted in the RX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR0=1: -0.8dB gain (value = E2h): 1 1 1 0 0 0 1 0 Transmit Gain channel #2 (GTX2) Addr=0Dh; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GR0=0: -2.36dB gain (value = AFh): 1 0 1 0 1 1 1 1 00h: Stop any trasmit signal, null level is transmitted in the corresponding timeslot on DX output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gain (value = FFh): 1 1 1 1 1 1 1 1 Overall gain including also RXG: GR0 = 1:-0.8dB; GR0 = 0: -4.3dB Receive Gain channel #1 (GRX1) Addr=10h; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GX0=0: -3.5dB gain (value = 8Fh): 1 0 0 0 1 1 1 1 Transmit Gain channel #3 (GTX3) Addr=0Eh; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00h:Stop any received signal, AGND level is forced on the VFRO1 analog output. >00h:Digitalgain is inserted in the RX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR1=1: -0.8dB gain (value = E2h): 1 1 1 0 0 0 1 0 GR1=0: -2.36dB gain (value = AFh): 00h:Stop any trasmit signal, null level is transmitted in the corresponding timeslot on DX output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gan (value = FFh): 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 Overall gain including also RXG: GR1= 1:-0.8dB; GR1 = 0: -4.3dB Receive Gain channel #2 (GRX2) Addr=11h; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GX0=0: -3.5dB gain (value = 8Fh): 1 0 0 0 1 1 1 1 00h:Stop any received signal, AGND level is forced on the VFRO2 analog output. >00h:Digitalgain is inserted in the RX path equalto: 13/27 STLC5046 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR2=1: -0.8dB gain (value = E2h): 1 1 1 0 0 0 1 0 Example: if T06..T00=00: TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0 Pin strap value (value 80h): 1 0 0 0 0 0 0 0 GR2=0: -2.36dB gain (value = AFh): 1 0 1 0 1 1 1 1 Referred to FS0. Transmit Time Slot channel#1 (DXA1) Addr=14h; Reset Value=00h Bit7 EN1 Bit6 T16 Bit5 T15 Bit4 T14 Bit3 T13 Bit2 T12 Bit1 T11 Bit0 T10 Overall gain including also RXG: GR2 = 1:-0.8dB; GR2 = 0: -4.3dB Receive Gain channel #3 (GRX3) Addr=12h; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EN1=0: 00h:Stop any received signal, AGND level is forced on the VFRO3 analog output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR3=1: -0.8dB gain (value = E2h): 1 1 1 0 0 0 1 0 GX3=0: -4.3dB gain (value = AFh): 1 0 1 0 1 1 1 1 Selected transmit time slot on DX output is in H.I. EN1=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI1. T16..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI1 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T16..T10=00: TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0 Overall gain including also RXG: GR3 = 1:-0.8dB; GR3 = 0: -4.3dB Transmit Time Slot channel #0 (DXA0) Addr=13h; Reset Value=00h Bit7 EN0 Bit6 T06 Bit5 T05 Bit4 T04 Bit3 T03 Bit2 T02 Bit1 T01 Bit0 T00 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 Referred to FS1. Transmit Time Slot channel #2 (DXA2) Addr=15h; Reset Value=00h Bit7 EN2 Bit6 T26 Bit5 T25 Bit4 T24 Bit3 T23 Bit2 T22 Bit1 T21 Bit0 T20 EN0=0: Selected transmit time slot on DX output is in H.I. EN0=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0. T06..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. 14/27 EN2=0: Selected transmit time slot on DX output is in H.I. EN2=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI2. T26..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI2 is carried out. If linear mode is selected (LIN=1 of CONF regis- STLC5046 t er) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T26..T20=00: TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10 on carrying the PCM signal to be decoded and tranferred to VFRO0 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R06..R00=00: TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 Pin strap value (value 80h): 1 0 0 0 0 0 0 0 Referred to FS2. Transmit Time Slot channel #3 (DXA3) Addr=16h; Reset Value=00h Bit7 EN3 Bit6 T36 Bit5 T35 Bit4 T34 Bit3 T33 Bit2 T32 Bit1 T31 Bit0 T30 Referred to FS0. Receive Time Slot channel #1 (DRA1) Addr=18h; Reset Value=00h Bit7 EN0 Bit6 R16 Bit5 R15 Bit4 R14 Bit3 R13 Bit2 R12 Bit1 R11 Bit0 R10 EN3=0: Selected transmit time slot on DX output is in H.I. EN3=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI3. T36..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI3 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T36..T30=00: TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10 EN1=0: EN1=1: Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R16..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and tranferred to VFRO1 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R16..R10=00: TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 Referred to FS3. Receive Time Slot channel #0 (DRA0) Addr=17h; Reset Value=00h Bit7 EN0 Bit6 R06 Bit5 R05 Bit4 R04 Bit3 R03 Bit2 R02 Bit1 R01 Bit0 R00 Referred to FS1. Receive Time Slot channel #2 (DRA2) Addr=19h; Reset Value=00h Bit7 EN2 Bit6 R26 Bit5 R25 Bit4 R24 Bit3 R23 Bit2 R22 Bit1 R21 Bit0 R20 EN0=0: EN0=1: Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO0 output. R06..0:Define receive time slot number (0 to 127) EN2=0: EN2=1: Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R26..0:Define receive time slot number (0 to 127) 15/27 STLC5046 on carrying the PCM signal to be decoded and tranferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R26..R20=00: TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10 FS rising edge. Pin strap value (value=00h): 0 0 0 0 0 0 0 0 Interrupt Mask Register for I/O port (DMASK) Addr=1Ch; Reset Value=FFh Addr=1Dh; Reset Value=XFh Bit7 MD7 Bit6 MD6 Bit5 MD5 Bit4 MD4 Bit3 MD3 Bit2 MD2 Bit1 Bit0 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 MD1 MD0 MD11 MD10 MD9 MD8 Referred to FS2. Receive Time Slot channel #3 (DRA3) Addr=1Ah; Reset Value=00h Bit7 EN3 Bit6 R36 Bit5 R35 Bit4 R34 Bit3 R33 Bit2 R32 Bit1 R31 Bit0 R30 EN3=0: EN3=1: Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R36..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and tranferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R36..R30=00: TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10 MD11..0=1: The corresponding I/O doesn’t generate interrupt. MD11..0=0: The corresponding I/O (programmed as Input) generate interrupt if a change of status is detected. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check registers PCHKA/B. Lines without persistance check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Pin strap value. 1 1 1 1 1 1 1 1 1 1 1 1 Interrupt Mask Register for CD port (CMASK) Addr=1Eh; Reset Value=XFh Bit7 Bit6 Bit5 Bit4 Bit3 MC3 Bit2 MC2 Bit1 Bit0 Pin strap value (value=80h) 1 0 0 0 0 0 0 0 MC1 MC0 Referred to FS3. PCM Shift Register (PCMSH) Addr=1Bh; Reset Value=00h Bit7 Bit6 XS2 Bit5 XS1 Bit4 XS0 Bit3 Bit2 RS2 Bit1 RS1 Bit0 RS0 XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge. RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7) after the 16/27 In MCU mode, dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n : MC3..0= 0 Any I/O line of the related channel is enabled to generate interrupt depending on DMASK setting. MC3..0=1 Any I/O line of the related chanel is disabled to generate interrupt indipendently of DMASK setting. In MCU mode, static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines. MC3..0=1: The corresponding I/O doesn’t generate interrupt. MC3..0=0: The corresponding I/O generate interrupt if a change of status is detected. STLC5046 I nput lines with persistency check generate interrupt if the changed status remains stable longer than the time programmend in the persistency check registers PCHKA/B Lines without persistency check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Pin strap value (value=00h): 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Interrupt Register (INT) Addr=21h; Reset Value=00h Bit7 Bit6 Bit5 Bit4 ICKF Bit3 ID3 Bit2 ID2 Bit1 ID1 Bit0 ID0 Persistency Check Register (PCHK-A/B) Two input signals per channel , labeled A and B, are submitted to persistency check. In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin13) and IO1 (pin14). In static mode (STA=1) the persistency check is performed on four pairs of lines, assigned to each channel according to the table: CHAN# 0 1 2 3 Input A IO0 (pin 13) IO4 (pin 17) IO6 (pin 48) IO10 (pin 44) Input B IO1 (pin 14) IO5 (pin 18) IO7 (pin 47) IO11 (pin 43) ICKF = 1: If interrupt is generated by a change of bit 0 in register ALARM. In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel. Any single bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled to generate interrupt ). In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively: ID0 : is set High when the interrupt is requested from any the I/O11..0 lines. ID2: is set High when the interrupt is requested from any of the CS3..0 (configured as I/O). ID0 and ID2 are cleared after reading related I/O register. ID1 and ID3 are don’t care. Pin strap value (value=00b): 0 0 0 0 0 Addr=1Fh; Addr=20h; Bit7 TA7 TB7 Bit6 TA6 TB6 Reset Value=00h Reset Value=00h Bit5 TA5 TB5 Bit4 TA4 TB4 Bit3 TA3 TB3 Bit2 TA2 TB2 Bit1 TA1 TB1 Bit0 TA0 TB0 Alarm Register (ALARM) Addr=22h; Reset Value=00h Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 POR Bit0 CKF TA7..0 and TB7..0, content of PCHKA and PCHKB registers, define the minimum duration of input A and B to generate interrupt ; spurious transitions shorter than the programmed value are ignored. The time width can be calculated according to the formula: Time-Width A = (TA7..0) x 64µs Time-Width B = (TB7..0) x 64µs If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will generate interrupt. All the inputs, with or without persistency check, are sampled with a repetition rate of 32µs Pin strap value: CKF=1: If number of PCM clock pulses in one frame period does not match expected value. POR=1: If a Power On Reset is detected during operation. The register ALARM is cleared after reading operation only if signals are inactive. Pin strap value (value=00h): 0 0 Interrupt Mask Register for Alarm (AMASK) Addr=23h; Reset Value=11b Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MCF 17/27 STLC5046 MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt. MCF=0: The corresponding alarm bit (CKF) generates interrupt. Pin strap value (value=00h): 1 Bit7 Bit6 Bit5 R12 Bit4 R11 R31 Bit3 R10 R30 Bit2 R02 R22 Bit1 R01 R21 Bit0 R00 R20 0 0 0 0 Receive Amplifier Gain Registers (RXG-10/32) Addr: 26h; Reset Value=00h Addr: 27h; Reset Value=00h Loopback Register (LOOPB) Addr=24h; Reset Value=00h Bit7 DL3 Bit6 DL2 Bit5 DL1 Bit4 DL0 Bit3 AL3 Bit2 AL2 Bit1 AL1 Bit0 AL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Rn2 R32 Rn1 Rn0 0 1 0 1 0 1 0 1 Receive Amplifier Gain Ch#n (dB) Mute -13.98 -7.96 -4.44 -1.94 0 0 0 DL3..0=0: Normal Operation DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the programmed Receive Time Slot is transferred to the programmed Transmit Time Slot. AL3..0=0: Normal Operation AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is tranferred to the VFXI input internally into the Codec. When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have no signal on the VFRO output programming the GR register to 00h in case of digital loopback. Pin strap value (value=00h): 0 0 0 0 0 0 0 0 Overall receive gain depends on the receive amplifier gain (Rn2..0 setting in RXG reg.) and digital gain (GRXn reg. setting). As a reference : when Rn2..0 is set for 0dB gain and GRXn=FFh (max. gain) 0dBm0 at DR input correspond to a level at VFRO output equal to 547mVrms (e.g. -3dBm 600ohm) Pin strap value : Rn2 GRn = 1 1 1 Rn1 1 0 Rn0 1 0 Transmit Preamplifier Gain Register (TXG) Addr=25h; Reset Value=X0h Bit7 Bit6 Bit5 Bit4 Bit3 XG3 Bit2 XG2 Bit1 XG1 Bit0 XG0 GRn = 0 Overall gain including also GRXn; GRn = 1: -0.8dB; GRn = 0: -4.3dB. Silicon Revision Identification Code (SR=D) Addr: 31h; Read Only. X X X X 0 0 0 0 XG3..0=0:Transmit preamplifier gain ch. 3..0= 0dB XG3..0=1:Transmit preamplifiergainch. 3..0= 3.52dB Overall transmit gain depends on combination of TXG and GTXn registers. For XGn=0 and GTXn=FF 0dBm0 at DX output correspond to 15dBm|600Ω (137mVrms) at VFXI input. Pin strap value (value=00h): 18/27 VCC(3.3V) 0.1µF VDD(3.3V) VCC VCC 61 60 59 58 RAC ZAC 20 19 25 RDC ILTF 26 RX 33 VFRO0 CRX MODE 41 39 17 43 44 3 4 5 6 7 1 2 8 30 23 42 TO OTHER SLICs RTH TTXIN CKRING CRT 11 CRT RLIM 31 RLIM REF 32 33 IREF 27 36 35 16 RT2 VREG BASE VBAT CVB CSRV 34 CREV CREV CSRV AGND and BGND must be shorted together on the LINE CARD VBAT VBAT QEXT VRING RS2 TIP RP1 TX CTX 100nF DET GDK/AL D0 D1 D2 R0 R1 CSOUT TO OTHER SLICs CS0 CSIN RES RTH 28 29 53 53 VFRO1 VFXI1 VFRO2 VFXI2 VFRO3 VFXI3 39 38 42 43 48 46 CS3 CS2 CS1 24 RP2 TIP 22 CAC CAC RT 18 14 RS RDC RS CH ZB ZB ZA CC 57 IO11 VREL IO10 21 RELR IO9 ZAC1 12 9 10 29 37 13 REL1 IO8 VDD VCC AGND BGND REL0 IO7 VCC (5V) GND VDD VDD 9 VEE 0.1µ F VSS 8 SUB 41 GRX=+6dB GTX=-12dB DX DR 11 10 FS PCM INTERFACE MCLK 14 13 VFXI0 35 IO0 19 IO1 IO2 IO3 IO4 IO5 IO6 20 21 22 23 24 62 TSX 12 M0 27 STLC5046 40 38 28 STLC3080 PCD RING RP1 VBAT LCP 1511 RING RT1 RS1 RR RP2 VCC M1 54 INT 3 CS CCLK 4 CO 7 SERIAL CONTROL PORTS CI 5 6 CAP 40 Figure 5. Typical Application Circuit with STLC3080 without Metering Pulse injection and I/O pins in dynamic mode. CAP 0.1 µF D99TL430 STLC5046 19/27 STLC5046 ELECTRICAL CHARACTERISTICS (Typical value 25°C and nominal supply voltage. Minimum and maximum value are guaranteed over the temperature 0 to 70°C range by production testing and supply voltage range shown in the Operating Ranges. Performances over -40 to +85°C are guaranteedby product characterisation unless otherwise specified.) DIGITAL INTERFACE Symbol Vil Vih Iil Iih Ci Vol Voh Parameter Input Voltage Low DI pins Input Voltage High DI pins (1) Input Current Low DI pins Input Current High DI pins Input Capacitance (all dig. inp.) Output Voltage Low DX, TSX pins Output Voltage High DX pinn Iol = 3.2mA (other pins Iol = 1mA) 0 Ioh = -3.2mA (other pins Iol = 1mA) 0.85VDD Test Condition Min. 0 0.8V DD -10 -10 5 0.4 VDD Typ. Max. 0.2VDD 5.5 10 10 Unit V V µA µA pF V V ANALOG INTERFACE RIX ROR Transmit Input Amplifier Input Impedance (VFXI) Receive Output Impedance (-1.0V< VFRO