STLC5432Q

STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRELIMINARY DATA ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD) ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2) HDB3/BIN ENCODER AND DECODER ON CHIP MULTIFRAME STRUCTURE HANDLING BUILT IN CRC4 EASY LINK TO ST5451/MK50H25/MK5027 LINK CONTROLLERS. DATA RATE: 2048, 4096 AND 8192 Kb/s FOR MULTIPLEXED APPLICATIONS FOUR LOOPBACK MODES FOR TESTING PSEUDO RANDOM SEQUENCE GENERATOR AND ANALYZER FOR ON-LINE, OFFLINE AND AUTOTEST CLOCK RECOVERY CIRCUITRY ON CHIP 64 BYTE ELASTIC MEMORY FOR TIME COMPENSATION AND AUTOMATIC FRAME AND SUPERFRAME ALIGNMENT 32 ON CHIP REGISTERS FOR CONFIGURATIONS, TESTING, ALARMS, FAULT AND ERROR RATE CONTROL. AUTO ADAPTATIVE DETECTION THRESHOLD AUTOMATIC EQUALIZER OPTION 5V POWER SUPPLY AMI OR HDB3 CODE SELECTION PARALLEL OR SERIAL MICROPROCESSOR INTERFACE OPTION BOTH µp AND STAND ALONE MODE AVAILABLE DESCRIPTION STLC5432, CMOS device, interfaces the multiplex system to the physical CEPT Transmission link at 2048Kb/s. Furthermore, thanks to its flexibility, it is the optimum solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 specifications. STLC5432 is the real single chip solution that allows the best system flexibility and easy design. STLC5432 can work either in 2048 or 4096 or 8192 Kbit/s systems programming the CR4 register (when parallel micro interface selected). July 1996 TQFP44 (10 x 10) ORDERING NUMBER: STLC5432Q PIN CONNECTION (Top view) GNDA 44 43 42 41 40 39 38 37 36 35 34 GNDD SA/RESET DIN A/D0 A/D1 A/D2 A/D3 INT RCLI BRDI DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BRDO XTAL1 XTAL2 VCCD2 AS/ALE VCCD1 DS/RD RCLO LCR BXDO HCR D93TL043D VCCA 33 32 31 30 29 28 27 26 25 24 23 LO2 LO1 DPI LI2 LI1 CS VT P1 P0 BXDI AL0 AL1 A/D7 A/D6 A/D5 A/D4 R/W/WR LFSX LFSR LCLK 1/46 STLC5432 PIN DESCRIPTION Name VCCD1 VCCD2 VCCA GNDD GNDA LI1 LI2 VT L01 L02 XTAL1 Pin 18 17 34 1 44 40 42 41 36 37 15 Type I I I I I I I O O O I Function Positive power supply inputs for the digital (VCCD1) and analog (VCCA) sections and for microprocessor interface signals (VCCD2). They must be +5 Volts and must be directly connected together. Negative power supply pins which must be connected together close to the device. All digital and analog signals are referred to these pins, which are normally at the system ground. Receive HDB3 signal differential inputs from the line transformer. Positive power supply output for fixing reference voltage to the receive transformer. Typical value is 2.375V Transmit HDB3 signal differential outputs to the line transformer.When used with an appropriate transformer, the line signal conforms to the output specifications in CCITT with a nominal pulse amplitude of 3 volts for a 120Ω load on line side. The master clock input which requires either a parallel resonance crystal to be tied between this pin and XTAL2, or a clock input from a stable source. This clock does not need to be synchronized to the system clock. Crystal specifications = 32764 kHz ± 50 ppm parallel resonant; RS ≤ 20Ω loaded with 33pF to GND each side. The output of the crystal oscillator, which should be connected to one end of the crystal if used. High clock received, bit clock. When the device has recovered the clock from the HDB3 signal, HCR signal is synchronized to the remote circuit. The HCR frequency is either 8192kHz if 8MCR bit of CR1 Register is put to 1 or 4096 kHz if 8MCR is set to 0. Low clock received, frame clock. When the device has recovered the clock from the HDB3 signal, LCR signal is synchronized to the remote entity. The LCR frequency is 8 kHz if 8KCR bit is set to 1, or 4 kHz if 8KCR bit is set to 0. When the remote clock is not recovered, HCR and LCR frequency are synchronized to master clock (16384 kHz). HCR and LCR can be used by the system in Terminal Mode.These two clocks can be used by the transmit function of the device. Binary Receive Data Output, 2048 kbit/s or 64kbit/s. Receive Clock output, 2048 kHz or 64kHz. After decoding, Binary Data and clock associated are provided for different applications. Binary Receive Data Input. 2048 kbit/s. Receive Clock Input 2048 kHz. Binary Transmit Data Output, 2048 kbit/s or output clock at 64kHz. Before encoding Binary Data is provided to different applications (Optical Interface for instance). Local clock is associated to this data. This binary signal can replace BXD internal signal to be encoded if SELEX bit (CR1 Register) is set to 1. Data Output. 30 B+D primary access data received from the line.Data can be shifted out from the tristate output DOUT at the LCLK frequency on the rising edges during all the time slots,except Time Slot Zero in accordance with TSOE bit (CR1Register). NB : If parallel micro-interface is selected, DOUT is at high impedance after Reset. DOUT is at low impedance after writing CR4 register. Data Input : 30B+D primary access data to transmit to the line.Data can be shifted in at the LCLK frequency on the falling edges during all the time slots, except Time Slot Zero, in accordance with TSOE bit (CR1 Register). XTAL2 HCR 16 19 O O LCR 20 O BRDO RCLO 12 14 O O BRDI RCLI BXDO 10 9 22 I I O BXDI DOUT 33 11 I O DIN 3 I 2/46 STLC5432 PIN DESCRIPTION (continued) Name LCLK Pin 23 Type I Function Local Clock : this clock input determines the data shift rate on the two digital multiplexes. This clock frequency can be indifferently 2048, 4096, 8192 or 16384kHz. Data Out and Data In rate is always 2048 kbit/s when Serial Interface microprocessor: an internal automatic mechanism divides by two the frequency if 4096 kHz. Local Frame Synchronization for the Receiver. This clock input defines the start of the frame on the digital multiplex Data (pin DOUT). This clock frequency can be indifferently 8 kHz or a submultiple of 8 kHz. Local Frame Synchronization for the Transmitter. This clock input defines the start of the frame on the digital multiplex Data (pin DIN). This clock frequency can be indifferently 8 kHz or a submultiple of 8 kHz. If submultiple of 8 kHz, LFSX defines the start of even frame on DIN. The TSO of this even frame will contain the Frame Alignment Signal (FAS) on the line. Alarm 0 Output, alarm 1 Output. These pins are open drain outputs which are normally in high impedance state. AL1 Z 0Volt Z 0Volt AL0 Z Z 0Volt 0Volt Alarm definitions Frame or Multiframe recovered, A bit received is 0. Frame or Multiframe recovered, A bit received is 1 Frame and Multiframe lost, AIS Alarm Indication Signal is detected. Frame and Multiframe lost, AIS Alarm Indication Signal is not detected. LFSR 24 I LFSX 25 I AL0, AL1 32 31 O O DPI SA/RESET 38 2 I I DPI input: The internal DPLL is synchronized either by the signal applied on DPI input (if DPIS bit of CR5 register is = 0) or by the 2MHz clock recovered from the line. Stand Alone : When this pin is connected to 5 Volts, the device works without microprocessor. The configuration is given by the values per default of programmable registers. BRDI and BXDI must not be used. RESET: When this pin is put to 5 Volts during 100 ns at least every programmable register is reset (value per default). When this pin is set at zero Volt, the type of microprocessor is selected by P0, P1 pins. P0, P1 39, 43 I Processor interface. These two input pins define the microprocessor interface chosen. P1 P0 Microprocessor Interface ----------------------------------------------------------------------------------0 0 Serial Microprocessor Interface 0 1 ST9 Microprocessor Interface 1 0 Multiplexed Motorola processor interface 1 1 Multiplexed Intel processor interface Address Strobe/Address Latch Enable. Input Chip Select. A high level on this input selects the PRCD for a read write operation. Read/Write/Write Data. Input. Data Strobe/Read Data. Input. Address/Data 0 to 7. Input-Output. Interrupt Request. The signal is activated low when the PRCD requests an interrupt. It is an open drain output. AS/ALE CS R/W/WR DS/RD A/D0 to A/D7 INT 13 35 26 21 4 to 7; 27 to 30 8 I I I I I/O O 3/46 4/46 RCLO BRDO BRDI LFSR SYNCHRONIZATION STLC5432 BLOCK DIAGRAM HCR LCR Q=32764KHz DPLL A RDBRD CLOCK DATA RECOVERY RD+ HDB3/BIN DECODER 64 BYTES ELASTIC MEMORY A B From A, B or DIN DOUT LCLK 2Mb/s S2/T2 INTERFACE PSEUDO RANDOM SEQUENCE GENERATOR LOOPBACK 3 LOOPBACK 2 LOOPBACK 1 PSEUDO RANDOM SEQUENCE ANALYZER LOOPBACK 4 PROGRAMMABLE REGISTERS µP INTERFACE To D or DOUT BXD BIN/HDB3 ENCODER LINE DRIVER ALARM SIGNALS 64KHz CLOCK MULTIFRAME GENERATION DIN D LFSX D93TL044F BXDI BXDO STLC5432 ABSOLUTE MAXIMUM RATINGS Symbol VCC to GND VI ILO1, IOL2 IC Tstg TL Parameter Supply Voltage to Ground Voltage at any digital or analog input Current at LO1 and LO2 Current at any digital or analog input Storage temperature range Lead Temperature (soldering, 10s) Value 7 VCC+1 to GND-1 ±100 ± 30 -65 to +150 +300 Unit V V mA mA °C °C THERMAL DATA Symbol Rthj-amb Parameter Thermal Resistance Junction to ambient Max. Value 50 Unit °C/W ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, Tamb = 0 to 70°C; Typical characteristics are specified at VCC = 5V, Tamb = 25°C; all signal are referenced to GND, unless otherwise specified.) Symbol Parameter DIGITAL INTERFACE Vil Input Low Voltage Vih Input High Voltage Vilx Input Low Voltage Vihx Input High Voltage Vol Output Low Voltage Test Condition Min. Typ. Max. 0.8 0.5 0.4 0.4 Unit V V V V V V V V 10 10 10 µA µA µA Voh Output High Voltage Iil Iih Ioz Input Low Current Input High Current Output Current in High Impedance (tri-state) All digital inputs All digital inputs 2.2 XTAL1 input XTAL1 input VCC-0.5 IL = 7mA for pins AL0, AL1, INT, DOUT, HCR, LCR. All other digital outputs: IL = 1mA IL = 7mA for pins AL0, AL1, 2.4 INT, DOUT, HCR, LCR. 2.4 All other digital outputs: IL = 1mA Any digital input, Gnd < Vin < Vil Any digital input, Gnd < Vin < VCC All digital tri-state I/Os without internal pull-up or pull-down resistor. DC measurement between LI1 and LI2 with the equalizer not connected Relative to LI1/LI2 pins with fixed detection threshold 75Ω at transformer secondary 120Ω at transformer secondary 75Ω or 120Ω at transformer secondary % nominal amplitude at 50% of peak amplitude 200 LINE INTERFACE FEATURES Zin Differential Input Resistance KΩ Vin Vpk75 Vpk120 Sym Rx sensitivity Transmit amplitude Transmit Amplitude Pulses Symetry 0.6 2.14 2.7 2.37 3 2.60 3.30 5 Vpk Vpk Vpk % Zero Zero level 10 % Pwdth Tx pulses width 219 244 269 ns Zout Differential Output Resistance 1 Ω MASTERCLOCK MCLK MCLK Frequency 32.764 MHz MCLK Frequency tolerance –50 50 ppm JITTER PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresponding characteristics plotted in following page). Intrinsic jitter Filter 20Hz - 100KHz 0.125 UI Intrinsic jitter Filter 700Hz - 100KHz 0.12 UI 5/46 STLC5432 ELECTRICAL CHARACTERISTICS (continued) Symbol Icc75 Icc120 Parameter Active Current (including line current) Active Current (including line current) Turns ratioes L Windings Resistance M and N winding resistances Inductance of winding L Leakage inductange of a winding, the other being short circuited Inter winding capacitance Turns ratioes L Windings Resistance M and N winding resistances Inductance of winding L Leakage inductange of a winding, the other being short circuited Inter winding capacitance Motional capacitance Shunt capacitance Inductance Serial resistance Load (corresponding to two 33pF capacitors connected to XTAL1 and XTAL2 pins on the application schematic) LCLK high to DOUT valid LCLK high to BXDO valid XTAL1 high to HCR high or low LCLK high to DOUT HZ HCR high to LCR high or low RCLO high to BDRO high or low All data inputs to clock low Clock low to all data inputs 150pF; 7mA 50pF; 1mA 150pF; 7mA 150pF; 7mA 150pF; 7mA 50pF; 1mA –20 10 10 F = 100KHz, Vrms = 100mV F = 100KHz, Vrms = 100mV F = 100KHz, Vrms = 100mV 0.2 6 4.718 15 20 2 0.2 15 F = 100KHz, Vrms = 100mV F = 100KHz, Vrms = 100V 2 0.3 Test Condition random output (50% of ones) random output (50% of ones) Min. Typ. 40 40 Max. Unit mA mA POWER CONSUMPTION TRANSFORMER SPECIFICATION FOR 75 Ω L:M:N: RL RMN LL Ls 1.57:1:1 0.23 0.11 Ω Ω mH µH Ck L:M:N: RL RMN LL Ls Ck Co Cc Lo Rs CL F = 100KHz, Vrms = 100mV 2:1:1 0.2 0.1 15 pF TRANSFORMER SPECIFICATION FOR120Ω Ω Ω mH µH pF pF pF mH Ω pF XTALL SPECIFICATIONS DYNAMIC CHARACTERISTICS tpd 50 ns tpdz td ts th 50 20 ns ns ns ns 6/46 HCR BRDO BRDI LCR DPI RCLO Figure 1: Receiver Diagram DPLL 1 DATA 64Kb/s LP3 1 1 LP1 SELER 64 x 8 MEMORY B 1 HDB3/BIN DECODER 1 1 CLOCK DATA RECOVERY SIG DPIS A A DOUT 2n-1 GENERATOR RDS SGV 2Mb/s S2/T2 INTERFACE SAV A B 2n-1 ANALYZER BIN/HDB3 ENCODER 1 ASP 1 RD RX A TRANSMITTER DIAGRAM SINGLE PULSE DIN D93TL046C AIS ALARM STLC5432 7/46 STLC5432 I NTRODUCTION This single chip CMOS Device interfaces the physical multiplex of the application to the physical CEPT transmission link at 2048kb/s. STLC5432 contains analog and digital functions to implement line interface function and frame synchronization. It meets pulse shape and jitter specifications in accordance with CCITT Recommendations and CEPT standards. Ck: Lh: RcuI and RcuIII : Inter winding capacitance Principal inductance of windings DC resistances of winding I and III. FUNCTIONAL DESCRIPTION 1. LINE INTERFACE 1.1 Receiver The receive input signal should be derived via a transformer of the same type used for the transmit direction. The suggested transformer is the VAC L4097-X004 or equivalent for the 75 ohms case and the VAC 4097-X012 or equivalent for the 120 ohms case. The electrical models of the transformers are summarized in the following table : Loads (Ω ) 75 120 n 1.57:1:1 2:1:1 Ls (µH) ≤0.3 ≤0.2 Ck (pF) ≤15 ≤15 Lh (mH) ≥2 ≥2 Rcul (Ω) 0.11 0.10 Rculll (Ω) 0.23 0.20 Wiring between the transformer and the circuit should respect the application schematic given in annex. (see fig 4). The internal fixed threshold is set to 200 mV over the common mode voltage VCM (VCM = 2.375 V nominal) to insure the specified transmission range with a good noise immunity. Two options are provided for special applications requiring improved transmission ranges: AUTO-ADAPTATIVE THRESHOLD: Using the configuration register CR4 (AVT), a peak amplitude detector circuit is connected to the received signal and after digital processing, an adaptative threshold value equal to 3/8 of the peak value is obtained at the output of a D to A converter and used for data detection. AUTOMATIC EQUALIZER: connecting two external capacitors of 100pF in series between the transformer and the circuits inputs, and using the configuration register CR4 (EQV), the circuit will select automatically a pre-compensation filter for long line configuration (see application schematic on figure 3 and 4 given in annex). with: n: Ls: Winding ratioes Leakage inductance Figure 2: Transmitter Diagram RD RX DOUT SGV 2n-1 GENERATOR LP4 RDS D TS GENERATOR TSO 1 BIN/HDB3 ENCODER 1 SELEX LP2 64KHz CLOCK 1 SIG 1 CRC4 1 1 1 1 DIN TM SIG ADAPTOR: WHEN DATA IN CLOCK IS AT 64KHz, DATA OUT CLOCK AT 2048KHz D93TL045B BXDI BXDO BXDI 8/46 STLC5432 Using both options allow the reception of a signal attenuated up to 12dB at 1024kHz. The Clock recovery is performed by a first PLL that guaranties the CCITT I431 requirements for the allowed Jitter, see Figure 23, this clock, RCL, is used internally and as local clock. A second DPLL starting from this RCL clock attenuate the Jitter, to fulfil the CCITT I431, see figure 8, this DPLL generate HCR, bit clock, and LCR frame clock, practically without Jitter. 1.2 Transmitter The line driver outputs are designed to drive the suitable transformer mentioned in the previous section. The transformer results in a signal amplitude of 3 volts on the line which meet G.703 pulse shape for a 120 ohm load (2.37 volt for a 75 ohms load). A special test mode is provided to check the pulse template according to the CCITT mask by using the configuration register CR3 (ASP). When the ALS command is valid, consecutive logical ”ones” are transmitted on the line. When APS command is valid, consecutive 1, 0, 1... 1, 0, 1, 0... are transmitted on the line. 2 CODING 2.1 HDB3/BIN DECODING The two constituents of the data signal are decoded and the binary Receive Data Signal (BRD) is processed by the next functions. 2.2 BIN/HDB3 ENCODING The binary transmit data signal (BXD) is encoded. The entire data stream, including all the time slots, is scanned for an occurence of four consecutive zeros. Such occurence is replaced by the appropriate HDB3 code. 3. BINARY INPUT-OUTPUT STLC5432 can directly interface binary data stream by means of the 6 dedicated pins: BRDO, RCLO, BRDI, RCLI, BXDO and BXDI. This allows the use of STLC5432 also for particular cases as for optical fiber or for different purposes. The functions of these 6 pins are defined by the SIG bit (SIGR register). 3.1 SIG = 0 When the bit SIG = 0 the binary data are exchanged at 2048KHz and the 6 extra pins are defined hereafter. 3.1.1 Extra pins for receive data The BRDO and RCLO output pins deliver respectively BRD binary receive data at 2048kb/s and the remote clock recovered at 2048kHz. Two BRDI and RCLI input pins can receive external binary receive data at 2048kb/s and the receive clock associated at 2048kHz. The SELER command replaces BRD internal signal with BRDI signal. 3.1.2 Extra pins for transmit data The transmit binary data output pin BXDO delivers transmit binary data BXD. Input pin BXDI can receive external binary transmit data. The SELEX command replaces BXD internal signal with BXDI signal. 3.2 SIG = 1 When SIG = 1, a signaling channel at 64 kb/s is implemented. 3.2.1 Extra pins for Receive data BRDO and RCLO output pins deliver respectively receive data at 64kb/s selected by an internal Time Slot Assigner and the receive clock associated at 64kHz. In this case, BRDI and RCLI are not used. 3.2.2 Extra pins for Transmit Data Output BXDO delivers the 64kHz clock for an external application. This external entity delivers data at 64kb/s on the rise edge of the clock. Input BXDI shifts data at 64 kb/s on the fall edge of the 64kHz clock. The same Time Slot Assigner is used by transmitter and receiver (See SIGR Register). 4 LOOPBACK 4.1 LOOPBACK 1 When LP1 Command is valid (LP1 bit high, see CRC3 register), output data signal replaces input data signal. Then, the recovery clock function provides the local clock. The loopback is transparent if AIS is at 0. If AISX is at 1, consecutive logical ”ones” are transmitted on the line. 4.2 LOOPBACK 2 LP2 Command (LP2 bit high, CR3 register) replaces BXD and XCLK signals (respectively Binary Transmit Data and transmit clock) with BRD and RCLK (respectively Binary Receive data and its clock recovered). 4.3 LOOPBACK 3 LP3 Command (LP3 bit high, CR3 register) replaces BRD and RCLK (respectively Binary Receive Data and its clock recovered) with BXD and 9/46 STLC5432 XCLK (respectively Transmit Data and its clock associated). Frame and multiframe generated by the transmitter of the circuit are processed by the receiver of the circuit, without encoding and decoding. 4.4 LOOPBACK 4 LP4 Command replaces Data in with Data out near of DIN and DOUT pins (See LP4R register). – or when bit 2 in time slot 0 in odd frames has been received with an error, i.e. at 0, on three consecutive occasions, – or when 915 errored CRC blocks out of 1000 have been detected. 5.2 FRAME ALIGNMENT RECOVERY Frame alignment will be assumed recovered when the following sequence is detected: – Detection of the correct Frame Alignment Signal, FAS – detection of bit 2 of 32nd byte after FAS, at 1. – detection of the correct Frame Alignment signal in the 64th byte after the first FAS detected. 5.3 MULTIFRAME ALIGNMENT RECOVERY Multiframe Alignment will be assumed recovered when at least two valid multiframe alignment signals MFAS have been detected within 8 ms. 5 FRAME ALIGNMENT Time slot 0 is used for the synchronization (G.706). At software Reset Frame and Multiframe are lost and a new research of FAS and MFAS is launched. 5.1 LOSS OF FRAME ALIGNMENT Frame alignment will be assumed to have been lost : – either when three consecutive incorrect frame alignment signals have been received, Table 1: CRC4 Multiframe Structure G.704 Sub Multiframe Frame 0 1 2 I 3 4 5 6 7 8 9 10 II 11 12 13 14 15 FAS: MFAS: E1–E2: C1 to C4: A: Sa4 to Sa8: Sa61 to Sa64: TIME SLOT ZERO BIT NUMBERS 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E1 C4 E2 1 A 1 A 1 A 1 A 1 A 1 A 1 A 2 0 1 3 0 A 4 1 Sa4 F Sa4 F Sa4 F Sa4 F Sa4 F Sa4 F Sa4 F Sa4 5 1 Sa5 A Sa5 A Sa5 A Sa5 A Sa5 A Sa5 A Sa5 A Sa5 6 0 Sa61 S Sa62 S Sa63 S Sa64 S Sa61 S Sa62 S Sa63 S Sa64 Sa7 Sa8 Sa7 Sa8 Sa7 Sa8 Sa7 Sa8 Sa7 Sa8 Sa7 Sa8 Sa7 Sa8 7 1 Sa7 8 1 Sa8 Frame Alignment Signal in each even Time Slot. Multi Frame Alignment Signal 0 0 1 0 1 1 CRC4 error Indication bits Cyclic Redundancy Check 4 (CRC4) bits Remote Alarm Indication Five bits in each odd Time Slot ETSI bits 10/46 STLC5432 5.3.1 Typical case Remote entity transmits Frame Alignment Signal (FAS) and Multiframe Alignment Signal (MFAS). As soon as lost of Frame Alignment is occured (LOF = 1), the local receiver recovers FAS from 254 up to 500µs after. As soon as FAS is recovered (LOF = 0), the local receiver recovers MFAS from 4 up to 6ms after. 5.3.2 Old Existing Equipment Case Remote entity transmits Frame Alignment Signal (FAS) without Multiframe Alignment Signal (MFAS). As soon as lost of Frame Alignment is occured (LOF=1), the local receiver recovers FAS from 254 up to 500µs after. Then LOF = 0, and 400ms after the local receiver indicates that the Multiframe Alignement Signal has not been recovered (MFNR = 1). 5.3.3 Particular Case: Spurious Frame Alignment Signal Local receiver receives true FAS and true MFAS among several spurious FAS. Multiframe Alignment signal (MFR=1) is recovered from 8 to 400ms after the Frame Alignment signal is recovered (LOF=0). Then, this FAS is either a spurious one (the ”Spurious Time slot Zero” is carrying FAS without MFAS), or true FAS. Anyway, when the Multiframe Alignment has been recovered (MFR=1), the good Frame Alignment Signal is taken into account and data are loaded into the Frame Memory at the good location. See Fig. 13 synchronization algorithm. 5.3.4 Worst Case Local receiver receives true FAS and true MFAS among several spurious FAS and several spurious MFAS. In this case, if the circuit has recovered a spurious FAS and MFAS, the CRC blocks will be detected with an high error rate. As soon as 915 errored CRC block within 1000 will be detcted, the MFAS will be assumed as spurious and a new research starts at the point just after the location of the assumed spurious Frame Alignement Signal. 5.4 Transmitter SIDE The Frame Alignement Signal is transmitted continuously on the transmitter side, with bit 1 of TS0 at logical 1. The MFAS signal is transmitted in accordance with NMF bit register (CR5 Register): if NMF is programmed to ”1” Logic, no MFAS is transmitted; if NMF is programmed to ”0” Logic the MFAS signal is transmitted continuously. Table 2. LOF 1 0 0 0 MFR 0 0 1 0 MFNR 0 0 0 1 RECEIVER STATE FAS or MFAS has been lost. State: Research of FAS FAS has been recovered. State: Research of MFAS Frame and Multiframe recovered State: Good working. Frame recovered. State: Good working without multiframe received from transmitting side. 6 Interfacing with the microprocessor The device can work in one of the 3 following modes : – Parallel microprocessor Interface Mode – Serial microprocessor Interface Mode – Without microprocessor : Stand Alone Mode. The choice is done by means of the SA/Reset, P0 and P1 pins. 6.1 Parallel Microprocessor Interface Mode The microprocessor can read (or write) the registers of the STLC5432 using the fifteen parallel Interface pins. The use of TSO (Time Slot Zero) of DIN and DOUT digital multiplex is defined by TSOE bit of CR5 Register. – If TSOE = 1, TSO on DIN multiplex Input is used to transfer Sa4 to Sa8 bits to the line and TSO on DOUT multiplex output is used to transfer Sa4 to Sa8 bits from the line. – If TSOE = 0, DOUT output is high impedance during TSO, and DIN Input ignores data during TSO. 6.2 Serial Microprocessor Interface Mode Fifteen parallel Interface pins are ignored, they are tied to ground. In this mode, the time slots 0 of internal multiplexes are considered like a channel used by the devices and the control entity located in the system to communicate. This channel can be switched across a switching network -or not- before its final destination. The message is constituted by two bytes which are transmitted on two consecutive Time Slots Zero. The bits of word are numbered 0 to 7, bit 0 is transmitted first. When the bit 7 of a byte is 0, this byte is the first word of the message. The bit 6, of the first word, is R/W bit: R/W = 1. Message to read a register whose address is designated by the following bits of the word ( A 0/5). 11/46 STLC5432 R/W = 0. Message to write a register, addressed by the bits A0/5. The bit 7 of following byte is 1 and the seven D 0/6 bits are data to load into register. To transfer one message, 250µs are necessary. Between two messages, the bits are 1 during TS0. See fig.7 for details. 6.2.1 Reading of a register The remote entity connected to the DIN and DOUT multiplexes can request reading of a register if it transmits, during TSO, on DIN the address bit A0/5, the R/W bit at 1 and the last bit at 0. The following word, ending with 1, is not taken into account by the device. The device returns two words during TSO of DOUT : –The first word begins with 0, R/W bit is put to 1, the address bits of the register are transmitted. –The second word begins with 1, then seven data bits of the register are transmitted. 6.2.2 Writing of a register The remote entity connected to the DIN and DOUT multiplexes can request writing, then it transmits the first bit at 0, the second bit at 0 and the register address A 0/5 during TSO of DIN. The following word begins with 1 and seven next bits are Data to load into register. There is no acknowledge after writing. The writing messages can be transmitted consecutively. 6.3 Stand Alone Mode Whatever the received frequency on LCLK pin (2.048kHz or 4.096kHz), the device automatically fits and always works at 2.048kHz. When SA pin is at 1, the multiframe research is automatically launched after each lost of frame and the device provides the following alarms on DOUT during the Time Slot 0: 7 F/S SKIP AR MFNR LOF B AIS LOS 7 RESET During Hardware Reset (Pin : SA/RESET) : – All the programmable registers are configurated with the default value. – Interrupts are not generated (INT PIN is high impedance). – The research of Multiframe is always active. At Software Reset (addressing the Reset register): – The registers are configurated with the default value only. After Reset : – The registers may be configurated with any value. 8 INTERRUPT All the bits of Alarm Registers generate an interrupt if they are not masked, except SLC (CAR2). An alarm generates an interrupt if the mask bit associated is 0. If a temporary event is detected from the line. ALR Alarm Register, CAR1 and CAR2 Complementary Alarm Registers can be read after interrupt or by polling. In this last case, these Alarm Registers can be considered like particular status registers. If a temporary event is detected from the line, then the appropriate bit is put to one. After reading by the microprocessor, this bit is put to zero until new event. If a permanent state occurs, then the appropriate bit is put to one. After reading by the microprocessor, this bit remains at one until disappearance of the cause. 8.1 Parallel Interface Mode ALR Alarm Register, CAR1 and CAR2 Complementary Alarm Registers can be read after interrupt or by polling. In this last case, these Alarm Registers can be considered like particular status registers. INT pin is put to 0 volt. The microprocessor reads Alarm Register. For example, after reading the ALR and CAR1 registers the microprocessor could act as follows: – If SC bit (clock 1 second) is 1, then the microprocessor reads fault counter registers. – If EXT1 bit (EXTENSION 1) is 1, then the microprocessor reads Complementary Alarm Register 1. – If TSOR (or Sa6R) bit of CAR1 is 1, the microprocessor reads TSORR (or Sa6RR) Register Loss of signal Alarm Indication Signal If LOF = 1, then B = 915 If LOF = 0, then B = WER LOF Loss of Frame MFNR Multi Frame Not Recovered AR A Bit Received SKIP Jump F/S Fast/Slow. Bits definitions are the same than bits definitions of ALR, CAR1 and CAR2 Registers. These bits represent the current state of the line; DIN is ignored during Time Slot Zero. LOS AIS B 12/46 STLC5432 8.2 Serial Interface Mode When an Alarm bit is put to 1 in ALR (Alarm Register), this bit generates automatically the transmission of two bytes message onto DOUT during Time slot 0 with : – The first bit of the first byte at 0; the second bit is at 0 and after the address bits of Alarm Register. – The data of the ALR (Alarm Register) is the secondbyte. NB : When TSOR or Sa6R bit of the CAR1 (Complementary Alarm Register 1) is put to ”1”, it generates a message in which there are address and data of TSORR Register (if TSOR bit is not masked), or address and data of Sa6RR register (if Sa6R is not masked). If the four occurences to transmit a message are simultaneous,the priority order is: Priority 1 : Priority 2 : Priority 3 : Priority 4 : Transmission of Alarm Register data if an alarm has been detected. Transmission of Register data after reading message from remote entity. Transmission of TSORR data after loading of this register. Transmission of Sa6RR data after loading of this register. 8.3 Stand Alone Mode Interrupts are not generated. AL0, AL1 pins indicate the current state of three alarms : LOF, AIS, A bit received and DOUT pin indicates the current state of nine alarms during time-slot zero (See Par. 6.3). 13/46 STLC5432 T able 3: The registers and their bits. After ADD Register Reset bit 7 (Dec.) Name (Hexa) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 88 FF 80 FF 80 FF 80 80 80 80 80 80 B8 80 9F X 9F 8F X 90 80 84 80 80 80 80 80 80 FF X 80 80 80 RESET ALR AMR CAR1 CAMR1 CAR2 CAMR2 FCR1 FCR2 ECR1 ECR2 PCR1 PCR2 ERTR TS0RR Sa6RR RES TS0XR Sa6XR RES SIGR LP4R CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 RES TCR1 TCR2 TCR3 1 1 1 SGV SAV CRCC 1 1 1 1 1 1 1 1 1 1 SHCR SLCR MERA DOHZ ASP EQV TS0E POLSa AMI FILT 1 1 WT WT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EXT1 MEXT1 EXT2 MEXT2 PRSL F6 F13 E6 E13 P6 P13 IT2 0 0 AR MAR 0 Nu PRSR F5 F12 E5 E12 P5 P12 IT1 0 AR AE Nu SIG LP4 LTM RDS1 Nu AVT APD OSCD Sa81 SP GTS5 ATS5 EBC bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/ Write Page NOT USED DUMMY REGISTER SC MSC Sa6R MFNR F4 F11 E4 E11 P4 P11 IT0 Sa4R Sa5R Sa4X Nu STS4 LTS4 8KCR RDS0 AISX DEL NMF SaT Sa80 Sa4P GTS4 ATS4 PELC LOF MLOF TS0R MFR F3 F10 E3 E10 P3 P10 VT3 Sa5R Sa61R Sa5X Sa61X STS3 LTS3 MCR1 POL ALS DCP HCRD Sa51 Sa71 Sa5P GTS3 ATS3 PULS 915 M915 ER MER 0 Nu F2 F9 E2 E9 P2 P9 VT2 Sa6R Sa62R Sa6X Sa62X STS2 LTS2 MCR0 NR LP3 M2 DPIS Sa50 Sa70 Sa6P GTS2 ATS2 FASC AIS MAIS CRCF SLC 1 F1 F8 E1 E8 P1 P8 VT1 Sa7R Sa63R Sa7X Sa63X STS1 LTS1 SELEX NX LP2 M1 Sa41 Sa61 Sa7P GTS1 ATS1 ODTS LOS MLOS WER SKIP MSKIP F0 F7 E0 E7 P0 P7 VT0 Sa8R Sa64R Sa8X Sa64X STS0 LTS0 SELER TM LP1 M0 Sa40 Sa60 Sa8P GTS0 ATS0 TWI W R R-W R R-W R R-W R R R R R R R-W R R R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W 15 15 15 15 15 16 16 16 16 16 16 17 17 17 17 17 18 18 18 18 20 20 21 21 23 23 24 24 25 25 26 MSa6R MTS0R MCRCF MWER MPRSL MPRSR MMFNR MMFR RESERVED: Avoid Addressing RESERVED: Avoid Addressing CENTER FROZ RESERVED: Avoid Addressing 35 to 63 Nu = Not used. Reserved for the die test: Avoid Addressing 14/46 STLC5432 9.1 Reset Register 7 1 Dummy Register 0 The software reset of the circuit is performed when this register is addressed whatever the value of its bits may be. Reading or writing is irrelevant. All the programmable registers are configurated by the default value indicated in each register description and the mechanism of multiframe is launched in accordance with the procedure described in the introduction. This register can be written or read. When a bit of this register is set to 1, the corresponding bit of the ALR register, which has the same number, is masked and an interrupt cannot be generated by this bit. 9.4 CAR1: Complementary Alarm Register 1 7 1 EXT2 0 Sa6R TS0R 0 ER CRCF WER After Reset = 80H 9.2 ALR: Alarm Register 7 1 EXT1 AR SC LOF 915 AIS 0 LOS WER After Reset = 88H LOS AIS 915 LOF SC AR EXT1 Loss of Signal. This bit is set to 1 when ten consecutive zeros have been detected before the HDB3/BIN decoder. Alarm Indication Signal: this bit is set to 1 in accordance with G.775 when the incoming signal is recived with only two, or less, zero for two consecutive double frame period (i.e. 512 x 2 bit). This bit is set to 1 when 915 errored CRC message blocks have been received within 1 second. Loss of Frame Alignment Word. When at 1, the synchronization is lost. One second Clock. This bit is set to one every second when there is synchronization. The number of faults which have been counted during the previous second is in fault counters FCR, ECR and PCR. A bit Received. This bit is set to 1 when the bit 3 of the odd time slot zero has been received consecutively two times at 1. Extension bit 1. This bit is set to 1 when one bit out of CAR1 Register bits is put to 1. CRCF ER TS0R Sa6R EXT2 Frame Word Error Rate. This bit is at ”1”when the threshold of fault condition has been reached; this bit is at ”0” when the threshold of deactivating has been reached. These two thresholds are indicated by the error Rate Threshold Register (ERTR). The Error Rate function is validated when the synchronization is achieved. CRC Frame. After remultiframe time, this bit is at ”1” when an eight frame block has been received with an error. E Bit received. ER bit is at ”1” during the frame 13 received when the E1 bit value of the same frame 13 is zero. ER bit is at ”1” during the frame 15 received when the E2 bit value of the previous frame 15 is zero (E1 and E2 = first bit of time slot zero in frames 13 and 15 respective). Time slot Zero Register. Thisbit is at ”1” when the TS0RR Register has been loaded in accordance withCR8 register and bit POLSa(CR6 register). Sa6R Register. This bit is put to one when Sa6RR Register has been loaded in accordance with SaT bit (CR6 Register). EXTENSION Bit 2 This bit is at ”1” when one bit out of CAR2 Register bits has been set to ”1”. 9.3 AMR Alarm Mask Register 7 1 MEXT1 MAR MSC MLOF M915 After Reset = FFH 0 MAIS MLOS 9.5 CAMR1 Complementary Alarm Mask Register 1 7 1 0 MEXT2 Nu MSaRm MTSOR MER MCRCF MWER At Reset = FFH This register can be read or written. 15/46 STLC5432 When a bit of this register is at ”1”, the CAR1 Register bit which has the same number is masked. The CAR1 bit which is masked do not generate an interrupt. 9.8 FCR1: Fault Counter Register 1 7 1 F6 F5 F4 F3 F2 F1 F0 0 After Reset = 80H F0/6 9.6 CAR2: Complementary Alarm Register 2 7 1 PRSL PRSR MFNR MFR After Reset = 80H 0 SLC SKIP 0 7 less significant bits of the FCR counter. 9.9 FCR2: Fault Counter Register 2 7 1 F13 F12 F11 F10 F9 F8 F7 0 SKIP SKIP. After frame recovery, this bit is at ”1” when an entire frame (32 words) has been ignored or has been repeated two times onto DOUT. SLC Slow Local Clock. This bit does not generate interrupt. When the value of this bit is 0, local clock is faster than the remote clock. When the value is ”1”, local clock is slower than the remote clock (an entire frame has been ignored). MFR Multiframe recovered within 400 ms. After reframe time, if the multiframe is recovered within 400 ms, MFR is set to ”1”. MFNR Multiframe Not recovered within 500 ms. After reframe time, the circuit researches the multiframe during 500 milliseconds. After this time, if the multiframe has not been recovered, MFNR is set at ”1”. Then the circuit is activated with the frame recovery only, and the AX bit (bit 3 of the odd Time Slot Zero transmitted) is set at ”0”. PRSR Pseudo Random Sequence Recovered. When the PRS analyzer is validated (SAV = 1), PRSR bit is set at ”1” if the synchronization is performed. PRSL Pseudo Random Sequence Lost. PRSL, this bit is set to ”1” when PCR1/2 14 (PRS Counter Register) has reached 2 detected faults. After Reset = 80H F7/13 7 most significant bits of the FCR counter. If POL bit of CR2 register is at ”0”, the value of 14 bits fault counter is loaded into these registers each second. If POL = 1, the registers are resetted after each access. (POL indicates the difference between polling mode and interrupt mode, see also CR2 register). When the multiframe has not been recovered within 400ms (MFNR = 1), these two registers indicate the number of errored bits of Frame Alignment Signal received over one second period. When the multiframe is recovered, these two registers indicate the number of errored CRC blocks received over one second period. 9.10 ECR1: E Bit Counter Register 1 7 1 E6 E5 E4 E3 E2 E1 E0 0 After Reset = 80H E 0/6 7 less significant bits of ECR counter 9.11 ECR2: E Bit Counter Register 2 7 1 E13 E12 E11 E10 E9 E8 E7 0 9.7 CAMR2: Complementary Alarm Mask Register 2 7 1 MPRSL MPRSR MMFNR MMFR Nu After Reset = FFH 0 1 MSKIP After Reset = 80H This register can be read or written. Bits: MMFNR, MMFR and MSKIP mask respectively bit MFNR, MFR and SKIP when they are at ”1”. 16/46 E 7/13 7 most significant bits of the ECR counter . ECR1 and ECR2 are two registers associated to ECR counter. Each second, the value of the counter is loaded into these register (POL = 0). When the multiframe is recovered, these two registers indicate the number of errored E bits received over 1 second period. STLC5432 9.12 PCR1: PRS Counter Register 1 7 1 P6 P5 P4 P3 P2 P1 P0 0 After Reset = 80H P0/6 7 less significant bits of the Pseudo Random Counter Register. IT 0/2 Error Rate Inhibition Threshold of WER IT 0/2 bits give the threshold of deactivating the indication of Alarm. Per default, WER is set at ”0” when 12 or less erroneous Frame Alignment Words are detected. The Alarm deactivation requires the confirmation of the condition for the following 2 sec. 9.13 PCR2: PRS Counter Register 2 7 1 P13 P12 P11 P10 P9 P8 P7 0 IT2 0 0 0 0 1 1 1 1 IT1 0 0 1 1 0 0 1 1 IT0 0 1 0 1 0 1 0 1 Number of erroneous Frame Alignment words received during 2 seconds 8 9 10 12 14 16 20 24 After Reset = 80H P7/13 7 most significant bits of the PseudoRandom Counter Register. PCR1 and PCR2 are two registers associated to Pseudo Random Sequence Counter. When the Pseudo Random Sequence Analyser is validated, the counter indicates the number of erroneus bits received after the synchronisation of the Pseudo Random Sequence. 9.14 ERTR: Error Rate Threshold Register 7 1 IT2 IT1 IT0 VT3 VT2 VT1 VT0 0 NB: If the threshold value of deactivating the indication of Alarm is superior to threshold value of activating the indication of Alarm, then the value of deactivating is irrelevant. 9.15 TS0RR: Time Slot Zero Received Register 7 1 0 0 0 Sa4R Sa5R Sa6R Sa7R Sa8R After Reset 80H After Reset = B8H VT 0/3 Error Rate Validation Threshold of WER. VT0/3 bits give the threshold of activating the indication of Alarm for erroneous Frame Alignment words. WER is set to ”1” only if the fault condition is confirmed within the following 2 seconds. VT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Number of erroneous Frame Alignement words received during 2 seconds 16 18 20 22 24 26 28 30 32 36 40 44 48 52 56 60 Sa4R to Sa8R Bits 4 to 8 of the odd Time Slot Zero (Sa4 to Sa8) received from the line. During reframe time, these bit are at ”1”. Sa4R to Sa8R fix the contentof TS0RR in accordancewith CR8 Register and bit POLSa (CR6 register) 9.16 Sa6RR: Sa6 Bits Receive Register 7 1 0 AR After Reset = 9FH 0 Sa5R Sa61R Sa62R Sa63R Sa64R Sa61R to Sa64R These four bits are received from Sa6 subchannel. When a new word constituted by these four bits is detected in accordance with SaT (CR6 Registers), a Sa6R interrupt is generated (a new word can occur each millisecond). Sa5R. Thisbit is the same asSa5R in TS0RR register. AR A bit received. It’s the same bit than the AR bit of ALR register (see 9.2). 17/46 STLC5432 9.18 TS0XR: Time Slot Zero transmit Register STS 0/4 Signalling Time Slot 0/4: these five bits indicate which time Slot out 7 0 of 32 to transmit and to receive on BRD0 and BXDI pins respectively, when SIG bit is at 1. 1 WT AE Sa4X Sa5X Sa6X Sa7X Sa8X SIG Signalling Validated. After Reset = 9FH Receiver Side : Sa4X to Sa8X Bits 4 to 8 of each odd Time Slot Zero to be transmitted onto the line When SIG is at ”1”, the contents of Time in accordance with CR6 and CR7 Slot selected appear on the BRDO pin at AE A bit to transmit. 64 kb/s and its clock associated o AX bit to be transmitted onto the line is given the RCLO pin at 64kHz. by the logical ”or” of LOF (Loss of Frame), When SIG is at ”0”, the contentsof 32 Time WER (if the bit MERA is at 0, CR1 register) slots received appear onto BRDO pin at and AE (see fig 5). 2 048 kb/s and clock associated onto AX(Odd TS0 Bit3) = AE + LOF + WER NOT RCLO pin at 2 048 kHz. MERA transmitter side : WT Word to Transmit. This bit is read only. When SIG is at ”1”, a bit stream at 64 kb/s First Case FILT = 1. on BXDI pin will be introduced into time After TS0XR writing by microprocessor with Slot, selected by STS0 to STS4 bits, to WT = 1, WT is resettedat ”0” afterthree the line. The bit stream on the input BXDI consecutive transmissions of Sa4X to pin is clocked by clock at 64KHz delivered Sa8X bits onto the line. by BXDO pin (BXDI pin is an input and Second Case FILT = 0. BXDO pin is an output). After TSOXR writing by microprocessor with When SIG is at ”0”, the bit stream at 2 048 WT = 1, WT is resettedat ”0” afterone kb/s on BXDI pin will be introduced into 32 transmission of bits located in TS0XRregister. Time Slots to the line. SHCR: Synchronization of High Clock Received. 9.19 Sa6XR: Sa6 Bits Transmit Register If DPIS (CR5) = 0: SHCR = 1, DPLL receives RCLI signal 7 0 from RCLI pin. SHCR = 0, DPLL receives the remoteclock 1 WT Nu Nu Sa61X Sa62X Sa63X Sa64X recovered from the line. After Reset = 8FH If DPIS (CR5) = 1: SHCR is not taken into account. Sa61X, Sa62X, Sa63X, Sa64X These four bits are transmitted on subchannel Source of the signal at the DPLL Sa6 in accordance with CR6 and CR7 Registers. DPIS SHCR input: WT Word to Transmit. This bit is read only. 0 0 1 1 0 1 0 1 line First Case SaT = 1. After Sa6XR writing by microprocessor, WT = 1. WT is resettedat ”0” afterthree consecutive transmissions of Sa61X to Sa64X bits onto the line. Second Case SaT = ”0”. After Sa6XR writing by microprocessor, WT = 1, WT is resetted at ”0” after one transmission of bits located in Sa6XR Register. RCLI pin DPI pin DPI pin 9.22 LP4R: Loop Back 4 Register 7 1 SLCR LP4 0 LTS4 LTS3 LTS2 LTS1 LTS0 After Reset = 80 H 9.21 SIGR: Signalling Register 7 1 SHCR SIG 0 STS4 STS3 STS2 STS1 STS0 LTS 0/4Loo Back time Slot 0/4: these five bits indicate which time slot out of the 32 is selected for the loopback. After Reset = 90H 18/46 STLC5432 LP4 Loopback 4 When this bit is at ”1”, loop back 4 is validated during Time Slot selected. The loop back is located between DOUT and DIN pins. The loop back is transparent during the Time Slot selected. DOUT always delivers the contents of each Time Slot. SLCR Synchronization of Low Clock Received Relevant if LTM (CR1) = 0. SLCR = 1, LCR output signal will be synchronized once when MFR bit (or MFNR bit) will go to ”1”. After synchronizing, the falling edge of LCR signal is in accordance with the 6th bit of time slot 1 seen at the input of the circuit. (LI1 pin or LI2 pin). The input signal is assumed without jitter. SLCR = 0, LCR output signal is free. The LCR frequency is a submultiple of HCR frequency. DELAY BETWEEN INPUT SIGNAL (LI1 OR LI2) AND OUTPUT SIGNAL (LCR) AT 8KHz AFTER SYNCHRONIZING (when SLCR = 1, LP4R Register Bit) 19/46 STLC5432 9.23 CR1: Configuration Register 1 7 1 0 MERA LTM 8KCR MCR1 MCR0 SELEX SELER After Reset = 84H 9.24 CR2: Configuration Register 2 7 1 DOHZ RDS1 RDS0 POL After Reset = 80H NR NX TM 0 SELER Selection of an external signal side receiver. When SELER=1, the internal binary data signal and its clock associated are replaced by the external binary data signal and its clock associated (respectively BRDI and RCLI). SELEX Selection of an external signal side transmitter. When SELEX = 1, the internal binary data signal is replaced by the external data signal BXDI. MCR0/1 HCR Frequency HCR pin delivers a square wave MCR1 0 0 1 1 MCR0 0 1 0 1 HCR Frequency in kHz 2048 4096 8192 TM NX 8KCR 8kHz Clock Received 8KCR = 1 LCR pin delivers a square wave at 8kHz (Low clock received) 8KCR0 = 0 LCRpindelivers asquarewaveat 4kHz LTM Line Termination Mode When LTM is at ”1”, the jitter filter is not validated. HCR and LCR pins deliver signals at a submultiple frequency of the frequency applied to XTAL1 pin. HCR frequency is in accordance with MCR0/1 and LCR frequencyis in accordance with 8KCR. When LTM is at ”0”, jitter filter is validated andMCR and LCR pins deliver cloks issued from DPLL in accordance with MCR0/1 and 8KCR. MERA Mask Error rate MERA = 0 WER bit (Error Rate over threshold) is taken into account to transmit A bit and to force to 1 the DOUTpin. MERA = 1 WER bit is ignored by A bit transmission and DOUT pin. NR POL Transparent Mode. For the transmitter, when this bit is at 1, the bit stream received on DIN pin is introduced directly into the Binary HDB3 encoder. In this case, FSX (Frame Synchronization Signal) from the pin is not used by the transmitterand Time Slot 0 is not known by the transmitter. The logical result is thesame if the bit stream is introduced onto BXDI pin at 2048 kb/s. For the receiver, when TM is at ”1”, every bit received from HDB3-BIN decoder is connected onto DOUT through the Elastic Memory. The synchronization is researched and indicated by the different alarm registers but DOUT pin delivers the received bit stream without taking into account the result of the synchronization. BRDO and RCLO pins provide the bit stream received from the decoder. PRBS Type to be transmitted. When the generator of Pseudo Random Binary Sequency is validated (SGV =1): if NX = 0, the length of sequence is 2*15-1 bits if NX = 1, the length of sequence is 2*11-1 bits. PRBS type received. When the Analyzer of Pseudo Random Binary Sequence is validated (SAV = 1): If NR = 0, the length of sequence received is 2*15-1 bits (O.151) If NR = 1, the length of sequence received is 2*11-1 bits (O.152) Fault Counter Register Polling. POL = 1 FCR1 and FCR2 registers or ECR1 andECR2 registersor PCR1 and PCR2 registers are read by the microprocessor (Polling Mode). First FCR1, or ECR1, or PRC1, is read then FCR2, or ECR2, or PRC2, mandatory. The contents of a pair of registers indicate the number of faults occured from the last reading of this pair of register. POL = 0 The two pairs of registers indicate the number of faults occured during the second which is passed just before InterruptSC. 20/46 STLC5432 RDS0/1Receive Data Select Bit 0/1 When the PRS analyser is validated SAV = 1 (TCR2), Sequence is checked by the analyser during the Time Slot(s) selected by TCR2. RDS1 0 0 1 RDS0 0 1 0 Source Sequence comes from Memory input. Sequence comes from memory Output. Sequence comes from Data Input (DIN pin). Instead of sequence, ”1” are transmitted onto the line. Sequence comes from Data Input (DIN pin). Sequence is transmitted onto the line. ALS AISX ASP 1 1 data stream coming from the decoder HDB3-BIN, just before frame memory input. Alarm Line Signal to be transmitted. When this bit is at 1, AIS or APS are transmitted onto the line. Alarm Indication signal. If ALS is at ”1”, and AISX is at ”1”: Alarm Indication signal (All 1s) is transmitted onto the line. If ALS is at ”1” and AISX is at ’0”: Auxiliary pattern (0-1-0-1-0-1...) is transmitted onto the line. Alternate Single Pulse If ASP = 1 The L01 andL02 outputsdeliver pulse every 3.9 microseconds. On theline, onewill bepositive,the next negativeand so on. When the PRS generator is validated, SGV = 1 (TCR1 register), Sequence is transmitted by the generator during the Time Slot(s) selected by TCR1. RDS1 0 RDS0 X Destination Sequence is transmitted onto the line. Loopback 1 or 3 can be validated. 9.26 CR4 Configuration Register 4 7 1 EQV AVT DEL DCP M2 M1 M0 0 After Reset = 80H The first three bits of this register, M 0/2, must not be changed by the microprocessor if the serial µP is selected, they can be programmed only in par1 X Sequence is transmitted on allel interface mode. If Serial interface or Stand Data Out (DOUT pin). Alone mode is chosen, then Multiplexes are at 2 048kb/s and local clock frequency may be either DOHZ DOUT High Impedance 2 048 kHz or 4 096 kHz. DOHZ = 1, DOUT pin is high impedance NB : If parallel micro interface is selected, DOUT DOHZ = 0, DOUT pin is in accordance with will be valid after writing CR4 Register. TS0E bit of CR5 register. M 0/2 Multiplex DIN and Multiplex DOUT M2 = 1 9.25 CR3 Configuration Register 3 Multiplexes are at 8 192 kb/s. Each multiplex includes 128 Time Slots. 7 0 M0 and M1 indicate the Time Slots selected by the device. 1 ASP Nu AISX ALS LP3 LP2 LP1 M2 = 0 and M1 = 1 After Reset = 80H Multiplexes are at 4 096 kb/s. Each multiplex includes 64 Time Slots. LP1 Loop Back 1 M0 indicates the Time Slots selected This loop back is the nearestto the line side by the device. pins. If LP1 = 1 incoming data are replaced by M2 = M1 = 0 outgoingdata. Multiplexes are at 2 048 kb/s. Each If AISX=0, loopback is transparent(outgoing multiplex includes 32 Time Slots. data is transmitted) If AISX=1, Alarm IndicationSignal is transmitted. DCP Double Clock Pulse When this bit is at ”1”, local clock frequency LP2 Loop Back 2 value is twice the data rate value. Loopback located between the HDB3/BIN Data In are shifted on the second falling decoderoutput and the BIN/HDB3 encoder edge of the local clock (LCLK). input. Loop back 2 is always transparent. When this bit is at ”0”, local clock frequency If LP2 = 1 Data received from the line are and data rate value have same value. returned to the line. Data in are shifted on the falling edge of the LP3 Loop Back 3 local clock. If LP3 = 1 Frames and Multiframes generaDEL Delayed mode. ted by the emitter are connected instead of 21/46 STLC5432 When DEL is at ”0”, Bit 0 of TS0 is indicated by the rising edge of Frame synchronization signal. When DEL is at ”1”, Bit 0 of TS0 is delayed; the rising edge of Frame Synchronization indicates the bit located just before Bit 0 Time Slot 0. AVT Adaptative Voltage Threshold Validation. When AVT is at 1, the adaptive voltage threshold is validated. When AVT = 0, the adaptive function is not validated; receiving is performed if the attenuation of the signal is less than 6 dB. EQV Equalizer Validation. When EQV is at ”1” internal equalizer is validated (external capacitors are required at the LI1 and LI2 inputs). When EQV is at 0, the equalizer is never operating (external capacitors are not required). TABLE OF DIFFERENT LOCAL MULTIPLEX (with Parallel microprocessor interface only) CONFIGURATION BITS M2 M1 M0 DCP Local Clock LCLK in kHz Multiplexes Data Rate in Kb/s DIN Number of Time Slots (TS) DOUT Time Slot in accordance with the TSn of the device 0 ≤ n ≤ 31 TSn 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048 4096 4096 8192 4096 8192 8192 16384 8192 16384 8192 16384 8192 16384 2048 1 X 32 TS 2n 4096 2 X 32 TS 2n + 1 TS 4n 8192 4 X32 TS 4n + 1 TS 4n + 2 TS 4n + 3 Ex : M2 = 1, M1 = 1, M0 = 0, each Multiplex includes 128 Time Slots, the data processed by the device during the internal time Slot 3 are the data connected to multiplexes during the external time slot 14 = 4 X 3 + 2. 22/46 STLC5432 9.27 CR5 Configuration Register 5 7 1 0 TS0E APD NMF HCRD DPIS CENTER FROZ After Reset = 80H FROZ Frozen DPLL. FROZ = 1, the DPLL is immediately frozen. Id est: DPLL retains its phase and its frequency while FROZ is at ”1”. CENTER Crystal Oscillator Rference. CENTER = 1, DPLL is synchronised by the Crystal Oscillator. CENTER = 0, DPLL is synchronised by the clock recovered from the line or by the signal applied to DPLL INPUT PIN (DPI) in accordance with DPIS. DPIS DPLL Input Selection. DPIS = 1, internal DPLL input receives the signal applied to DPLL INPUT PIN (DPI) DPIS = 0, internal DPLL input receives the signal recovered from the line. HCRD HCR Disabled. HCRD = 1, HCR pin is high impedance HCRD = 0, HCR pin is low impedance. NMF No Multiframe. NMF = 1 the multiframe is not transmitted, only the Frame Alignement Signal (FAS) is transmitted onthe line duringthe time slot 0. The receiver is not concerned by this bit. NMF = 0 the multiframe (MFAS) is transmitted with the CRC4, the Frame Alignement Signal (FAS) is transmitted in accordance with G.704. APD Alarm Pattern on DOUT. When this bit is ”1”, DOUT Pin delivers Auxiliary Pattern: (0-1-0-1-0-1...). TS0E DOUT enabled during Time Slot Zero. In serial microprocessor mode, this bit is not significant: in this case Time Slot Zero is used to exchange data between the device and the remote serial interface microprocessor. In parallel microprocessor mode,TS0E bit is taken into account: TS0E =1. Sa4R to Sa8R bits of the TS0RR Register are transmitted onto DOUT during the time Slot Zero. The bits 1 to 3 of this same time Slot Zero are ODD, SKIP, SLC. - When ODD = 1, the contents of Time Slot 1 to 31 are relative to the contents of odd frame received from the line. - When ODD = 0, the contents of Time Slot 1 to 31 are relative to the contents of even frame received from the line. If the sinchronisation is lost or if the error rate is over the programmed threshold, the DOUT pin is set at ”1”. The bits 4 to 8 of the incoming time Slot Zero (DIN pin) are transmitted onto the line in accordance with CR6 and CR7 Registers. Bits 1 to 3 are ignored. TS0E = 0. DOUT is high impedance during the time Slot Zero. Incoming bits on DIN pin are ignored during Time Slot Zero. 9.28 CR6 Configuration Register 6 7 1 0 POLSa OSCD SaT Sa51 Sa50 Sa41 Sa40 After Reset = 80H Sa40/Sa41 Sa41 Sa40 0 0 1 1 0 1 0 1 For Subchannel Sa4 in Transmission, the source is: Bit Sa4X of TS0XR Register Bit Sa4X of DIN received during TS0 For Subchannel Sa4 in Reception, the destination is: TS0RR Register receives Bit Sa4R and DOUT pin delivers Bit Sa4R. Reserved Code: Do not use Reserved Code: Do not use Sa50/Sa51 Sa51 Sa50 0 0 1 1 0 1 0 1 For Subchannel Sa5 in Transmission, the source is: Bit Sa5X of TS0XR Register Bit Sa5X of DIN received during TS0 For Subchannel Sa5 in Reception, the destination is: TS0RR Register receives Bit Sa5R and DOUT pin delivers Bit Sa5R. Reserved Code: Do not use Reserved Code: Do not use SaT Same Bits Three times. SaT = 1: if a new value for the Sa5R, Sa61R, Sa62R, Sa63R and Sa64R bits has been received three times identical, these bits are loaded into Sa6RR register and a Sa6R interrupt is generated. SaT = 0: each millisecond the Sa5R, Sa61R, Sa62R, Sa63R and Sa64R bits are loaded into Sa6RR register and a Sa6R interrupt is generated. 23/46 STLC5432 Transmitter side: SaT fixs the number of consencutive transmissions of Sa61 to Sa64 bits onto the line before resetting WT (Sa6XR register). See definition of WT bit in chapter 9.19 OSCD Oscillator Disabled OSCD = 1, The clock pulse applied to XTAL1 input pin comes from an external generator. The internal oscillator is disabled to reduce power consumption. XTAL2 pin has to be left open. OSCD = 0, The two pins of a crystal are connectedto XTAL1 pin and XTAL2 pin in accordance with the application schematic andthe internal oscillator is enabled. POLSa = 1: Each bit of TS0RR register is reset after a reading cycle from microprocessor except if the condition to set the bit at ”1” is still present. POLSa = 0: Each bit of TS0RR Register is always reset after a reading cycle from microprocessor. (see also SP bit of CR8 Register). 9.29 CR7 Configuration Register 7 7 1 AMI 0 Sa81 Sa80 Sa71 Sa70 Sa61 Sa60 After Reset = 80H Sa60/Sa61 Sa61 Sa60 0 0 0 1 For Subchannel For Subchannel Sa6 Sa6 in Reception, in Transmission, the destination is: the source is: Bit Sa6X of TS0XR Sa60 and Sa61 are Register not taken into account: TS0RR Bit Sa6X of DIN received during TS0 Register receives Bit Sa6R and DOUT pin delivers Bit Sa6R Contents of Sa6XR Sa6RR Register Register Reserved Code: Do not use 1 1 0 1 AMI Sa70/Sa71:same definition as Sa40/Sa41. Sa80/Sa81:same definition as Sa40/Sa41. Alternate Mark Inversion. AMI = 0, select HDB3 code on the line. AMI = 1, select AMI code on the line. 9.30 CR8 Configuration Register 8 7 1 FILT SP 0 Sa4P Sa5P Sa6P Sa7P Sa8P After Reset = FFH Sa8P 24/46 Sa8 Bit Polarity. This bit is taken into account if SP =1. Sa8P =1, Sa8R bit (of TS0RR Register) is set at ”1”, in accordance with FILT, when Sa8 bit received from the line goes from ”0” to ”1”. Sa8P =0, Sa8R bit (of TS0RR Register) is set at ”1”, in accordance with FILT, when Sa8 bit received from the line goes from ”1” to ”0”. Sa7P to Sa4P Same definition as Sa8P SP Single Polarity SP =1, Sa8P to Sa4P and POLSa (CR6 Register) bits are taken into account. Sa8 to Sa4 (changing state) received from the line are stored into TS0RR Register in accordance with FILT. When TS0RR Register is read by the microprocessor, TS0RR is put to 0 in accordance with POLSa bit (CR6 register). SP = 0, Sa8P to Sa4P and POLSa bits are not taken into account. Sa8 to Sa4 bits received from the line are stored into TS0RR Register in accordance with FILT. When TS0RR Register is read by the microprocessor, TS0RR keeps its contents. FILT FILTERING Receiver side: FILT = 1 and SP = 1, Sa8R to Sa4R bits of TS0RR Register are set at ”1” respectively if a new state has been received three times consecutively from each channelSa8 to Sa4 processed separately one by one. A TS0R interrupt is generated. FILT = 0 and SP = 1, Sa8R to Sa4R bits of TS0RR Registerare set at ”1” respectively if a new state has been received twice consecutively from each channel Sa8 to Sa4 processed separately one by one. A TS0R interrupt is generated. FILT = 1 and SP = 0, Sa8 to Sa4 bits received from the line and processed independently are stored into TS0RR Register if one new bit has been received three times identically at least. A TS0R interrupt is generated. FILT = 0 and SP = 0, Sa8 to Sa4 bits received from the line are stored into TS0RR Register each 250ms without processing. A TS0R interrupt is generated. Transmitter side: See TS0XR register definition chapter 9.18. STLC5432 9.32 TCR1: Test Configuration Register 1 7 1 0 SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0 After Reset = 80H SGV Sequence(PRBS) provided by the internal generator (see Table). Sequence Generator Validated. When SGV is at ”1”, the generator provides Pseudo Random Binary Sequence in accordance with NX bit. When SGV is at 0, the generator is not validated. GTS0 to GTS5 Time Slot associated to generator. These 6 bits indicate Time Slot(s) selected to transmit the Pseudo Random Binary GTS5 0 0 1 1 1 ↓ 1 1 GTS4 0 X 0 0 0 ↓ 1 1 GTS3 0 X 0 0 0 ↓ 1 1 GTS2 0 X 0 0 0 ↓ 1 1 GTS1 0 X 0 0 1 ↓ 1 1 GTS0 0 1 0 1 0 ↓ 0 1 Time Slot(s) selected to transmit PRBS All the Time Slots except TS0 All the Time Slots including TS0 Not use TS1 TS2 ↓ TS30 TS31 9.33 TCR2: Test Configuration Register 2 SAV 7 1 0 SAV ATS5 ATS4 ATS3 ATS2 ATS1 ATS0 After Reset = 80H ATS0 to ATS5 Time Slot associated to Analyzer. These 6 bits indicate Time Slot(s) selected to receive the Pseudo Random Binary Sequence (PRBS). The internal analyzer ATS5 0 0 1 1 1 ↓ 1 1 ATS4 0 X 0 0 0 ↓ 1 1 ATS3 0 X 0 0 0 ↓ 1 1 ATS2 0 X 0 0 0 ↓ 1 1 GTS1 0 X 0 0 1 ↓ 1 1 checks the sequence. Sequence Analyzer Validated. When SAV is at ”1”, the analyzer is validated and the counter ECR1-ECR2 (14 bits) is associated to analyzer. The length of PRBS is in accordance with NR bit. After the sequence is recovered by the analyzer. PRSR is set at ”1” (Complementry Alarm Register); the associated counter indicates the number of faults received. GTS0 0 1 0 1 0 ↓ 0 1 Time Slot(s) selected to receive PRBS All the Time Slots except TS0 All the Time Slots including TS0 Not use TS1 TS2 ↓ TS30 TS31 25/46 STLC5432 9.34 TCR3 Test Configuration Register 3 7 1 CRCC EBC PELC PULS FASC ODTS TWI After Reset = 80H 0 TWI TSO corrupted TWICE. If FASC=1 and TWI=1, Time Slot 0 selected by ODTS is corrupted twice only. If FASC=1 and TWI=0, Time Slot 0 selected by ODTS is corrupted three times only. ODTS Odd Time Slot 0 If FASC=1 and ODTS=1, Odd Time Slot zero is transmitted with Bit 2 at ”0”. If FASC=1 and ODTS=0, Even Time Slot Zero is transmitted with Bit 2 at ”1”. FASC Frame Alignment Signal Corrupted. In accordance with ODTS and TWI. If FASC=1, Time Slot 0 transmitted is corrupted. After transmitting twice or three times consecutively,FASC changes from ”1” to ”0”. PULS PULSE First case : SGV = 0 (TCR2 Register) If PELC=1 and PULS=1, 512 consecutive pulses are transmitted on the line during frame 0 and frame 1. If PELC=1 and PULS=0, no pulses are transmitted during 16 time-bit (7,8 microseconds). Second case : SGV = 1 (TCR2 Register) PULSE is ignored; if PELC changes ”0” to ”1”, one pseudo random sequence bit transmitted is corrupted.After transmitting corruptedbit, PELC changes”1” to ”0”. PELC Pulses transmitted on the line are corupted in accordance with PULS and SGV (TCR2 Register). After transmitting once time, PELC changes from ”1” to ”0”. EBC E Bit Corrupted. If EBC=1, E bit of the next frame 13 and E bit of the next frame 15 will be transmitted at ”0”. After transmitting once time, EBC changes from ”1” to ”0”. CRCC CRC4 corrupted When CRCC is at ”1”, CRC4 transmitted into multiframe is continuously corrupted. 26/46 STLC5432 Figure 3: Connections with and without Internal Equalizer. 33pF 32768MHz 33pF (*) 0V 100pF LI1 XTAL1 XTAL2 0V VCCD1 VCCD2 VCCA +5 10µF 60Ω Zc=120Ω 60Ω VT LI2 10µ F 0V 100pF 100nF GNDD GNDA 0V 100nF (*) STLC5432 7mA max 15Ω LO1 AL1 +5 Zc=120Ω AL0 15Ω LO2 D93TL048C (*) To be inserted for the internal Equalizer Figure 4: STLC5432 Line Interface Configurations (CEPT 120Ω or 75Ω) Z = 120Ω 15Ω LO1 1:2 LO1 Z = 75Ω 15Ω 1 : 1.57 AUTOMATIC EQUALIZER CONFIGURATION 15Ω LO1 120Ω or 75Ω CONFIG 15Ω LO2 2 : 1.57 100pF LI1 60Ω 75 Ω VT 60Ω 100pF LI2 120Ω or 75Ω CONFIG TX 15Ω LO2 1:1 LI1 60Ω 120Ω 15Ω LO2 75 Ω LI1 60Ω 120Ω 60Ω VT 60Ω LI2 0.1µF 10µF 0.1µF 10µF RX VT LI2 0.1 µF 10µF D93TL070A 27/46 STLC5432 Figure 5: Main Alarm Processing LINE STATE RECEIVING ALARMS DETECTED (TSOXR) AE Bit REGISTERS ALARMS TRANSMITTED ODD TS0 BIT 3 Ax or and MERA (CR1) ALR ALARMS REGISTER CAR1 COMPLEM. ALARM REGISTER LOS AIS 915 LOF AR WER Bit 0 Bit 1 Bit 2 Bit 3 Bit 5 Bit 0 D93TL050B Figure 6: DIN and DOUT During Time slot 0. SA pin: 0V Serial Interface P0 + P1 = 0 During Time Slot 0: Parallel Interface: P0 + P1 # 0 IF TSOE = 0 (CR5) During Time Slot 0: Dout pin is High Z. IF TSOE = 1 During Time Slot 0: Dout pin delivers consecutively: Dout pin delivers messages and Din pin receives messages ODD SKIP SLC Sa4R Sa5R Sa6R Sa7R Sa8R SA pin: 5V Stand Alone During Time Slot 0: Dout pin delivers eight alarms SLC SKIP AR MFNR LOF B AIS LOS ODD = 1 The contents of 31 Time Slots is related to odd frame received from the line. ODD = 0 The contents of 31 Time Slots is related to even frame received from the line. (See Figure 6a). Din pin receives eight bits: X X X Sa4E Sa5E Sa6E Sa7E Sa8E Din pin is ignored during Time Slot 0 D93TL051E 28/46 STLC5432 F igure 6a: DOUT during Timeslot 0 (Bits 1 to 3) when TS0E = 1 (CR5) Without skip Odd frame n - 1 Even frame n Odd frame n + 1 Even frame n + 2 ODD = 1 SKIP = 0 SLC = X ODD = 0 SKIP = 0 SLC = X ODD = 1 SKIP = 0 SLC = X ODD = 0 SKIP = 0 SLC = X With skip and loss of Even frame n Odd frame n - 1 Odd frame n + 1 Even frame n + 2 Odd frame n + 3 ODD = 1 SKIP = 0 SLC = X ODD = 1 SKIP = 1 SLC = 1 ODD = 0 SKIP = 0 SLC = 1 ODD = 1 SKIP = 0 SLC = 1 With skip and duplication of Odd frame n Even frame n - 1 Odd frame n Odd frame n Even frame n + 1 ODD = 0 SKIP = 0 SLC = X ODD = 1 SKIP = 0 SLC = X ODD = 1 SKIP = 1 SLC = 0 ODD = 0 SKIP = 0 SLC = 0 29/46 STLC5432 F igure 7: DIN/DOUT multiplex during Time Slot 0 - Serial Microprocessor Interface Mode. BIT NUMBER 0 1 2 3 4 5 6 7 A ADDRESS REGISTER A0 A1 A2 A3 A4 A5 R R/W 0 D DATA D0 D1 D2 D3 D4 D5 D6 1 1 1 1 1 1 1 1 1 IDLE THE BITS ARE TRANSMITTED TO MULTIPLEX IN ORDER, BIT 1 FIRST 0 TWO CONSECUTIVE WRITE CYCLES TSO TSO 0 0 D0/6 1 TSO A0/5 0 0 D0/6 1 DIN A0/5 A 125µs D 125 µs A 125µs D WRITE CYCLE 250µs 2nd WRITE CYCLE D93TL053A READ CYCLE A0/5 DIN 10 11111111 IDLE or WRITE CYCLES A0/5 00 11111111 NEW READ CYCLE A0/5 10 125µs n x 125µs INTERRUPT MESSAGE A0/5 DOUT 10 D0/6 1 A0/5 10 READ CYCLE 1 IDLE 11111111 ALARM REGISTER ADDRESS 250µs ALARM REGISTER DATA REGISTER ADDRESS 250 µs REGISTER DATA D93TL052A 30/46 STLC5432 Figure 8: Jitter Transfer Characteristic (CCITT I431) Gain (dB) x 0 20dB/dec y fa fb fc D94TL134 fd Carrier frequency (logarithmic scale) Y –19.5dB X 0.5dB fa 10Hz fb 40Hz fc 400Hz fd 100kHz Figure 9: Level 1 - Level 2 Process with Parallel Interface µP. 2Mb/s DOUT TS0 Z TS16 TS0 SYSTEM LEVEL 1 S2/T2 PRCD DIN TS16 TS0 TS16 Z 5451 HDLC PARALLEL INTERFACE 5451 HDLC LEVEL 2 ST9 µP 64Kb/s SIGNALLING LAP D POINT TO POINT D93TL055A 31/46 STLC5432 Figure 10: Primary Rate Controller Device PRCD - TE mode with serial Microprocessor XTAL 32764KHz XTAL1 XTAL2 HCR LCR LFSR 4KHz 4096KHz MEMORY DOUT 2Mb/s INTERFACE S2/T2 RECEIVER EMITTER LCLK NETWORK DIN µP STLC5432 PRCD LTM=0 (Configuration Register1) LFSX SYSTEM D93TL056C Figure 11: Four STLC5432 in LT Mode MASTER CLOCK 32764KHz 8MHz 8KHz LCR DOUT 0 XTAL1 HCR STLC5432 LCLK LFSX/R DIN FRAME SIGNAL BIT CLOCK XTAL1 DOUT 1 8Mb/s SWITCHING NETWORK STLC5432 LCLK LFSX/R DIN 8Mb/s XTAL1 DOUT 2 STLC5432 LCLK LFSX/R DIN XTAL1 DOUT 3 STLC5432 LCLK LFSX/R DIN LTM=1 (Configuration Register1) D93TL057C 32/46 DOUT TIME SLOTS 1 to 31 DIN Bits: A, Sa 4, 7 & 8 FRAME & CRC4 MULTIFRAME GENERATOR Figure 12: ETSI NT1 Option 2 LOOPBACK 1 Bits: E, LOS, LOF Sa 4 to Sa 8 MESSAGE Sa 5, Sa 61 to Sa 64 FRAME & CRC4 MULTIFRAME ALIGNMENT CRC4 CHECK STLC5432 STLC5432 EBIT CRC4 GENERATOR NETWORK SIDE CRC4 CHECK T REFERENCE EBIT EMITTER DIN MESSAGE Sa 61 to Sa 64 TIME SLOTS 1 to 31 DOUT Bit: E, LOS, LOF Bits: A, Sa 4 to Sa 8 RECEIVER CRC4 GENERATOR FRAME & CRC4 MULTIFRAME GENERATOR FRAME & CRC4 MULTIFRAME ALIGNMENT µP ST9 D93TL058A STLC5432 33/46 STLC5432 Figure 13: Synchronization Algorithm LOF = 1 LOSS OF FRAME DOUT DELIVERS ”ALL 1s” FRAME RESEARCH Ax = 1; Ex = 0 NO FRAME ALIGNMENT RECOVERY YES LOF = 0 DOUT IS VALIDATED. TIMER OUT 400ms STARTS. MULTIFRAME RESEARCH Ax = 0; Ex = 0 MULTI FRAME ALIGNMENT RECOVERY YES NO FRAME ALIGNMENT LOST YES NO MFR = 1 FCR 1/2 COUNTER IS VALIDATED TO COUNT CRC4 BLOCKS RECEIVED FALSE ECR 1/2 COUNTER IS VALIDATED TO COUNT E BIT RECEIVED AT ”0” TIME OUT 400ms EXPIRED YES NO MFNR = 1 FCR 1/2 COUNTER IS VALIDATED TO COUNT BITS OF FRAME ALIGNMENT SIGNAL RECEIVED FALSE YES 915 CRC4 BLOCK RECEIVED FALSE NO FRAME ALIGNMENT LOST YES NO FRAME ALIGNMENT LOST YES D93TL059B NO 34/46 STLC5432 Figure 14: Three Cases of Synchronization. TYPICAL CASE LOF 500µs max 6ms max MFR MFNR OLD EXISTING EQUIPMENT CASE LOF 500µs max MFR 400ms max MFNR PARTICULAR CASE: SPURIOUS FAS LOF 500µs max 8ms min - 400ms max MFR MFNR D93TL060B 35/46 STLC5432 Figure 15: Pseudo Random Sequence Analyzer Algorithm. START SAV =1 YES PRS DURING ALL THE TIME SLOTS YES NO NO MFNR + MFR =1 YES NO NO LOF = 1 YES PSEUDO RANDOM SEQUENCE RESEARCH SAV SEQUENCE ANALYZER VALIDATED LOF LOSS OF FRAME MFR MULTIFRAME RECOVERED MFNR MULTIFRAME NOT RECOVERED PRSR PSEUDO RANDOM SEQUENCE RECOVERED PRS RECOVERED YES NO PRSR INTERRUPT D93TL061A 36/46 STLC5432 Figure 16: Transmitter Side Timing SIG = 0 DATA RATE AT 2048Kb/s 488ns LCLK (CLOCK) BXDO (DATA) tpd tH ts BXDI (DATA) SIG = 1 DATA RATE AT 64Kb/s 15.6µs BXDO (CLOCK) tH ts BXDI (DATA) D93TL062B Figure 16a: Transmitter Side: Delay on BXD0 pin Example applied to DIN pin with Data Rate at 2048Kb/s LFSX LCLK DIN BIT 254 BIT 255 BIT 0 BIT 1 BIT 2 BXDO BIT 253 BIT 254 BIT 255 BIT 0 BIT 1 D96TL254 BXDO output has 2 LCLK pulse of delay from DIN input 37/46 STLC5432 Figure 17: Receiver Side Timing T T1/2 T1/2 RCLO (CLOCK) td td BRDO (DATA) T’ T’1/2 T’1/2 RCLI (CLOCK) tH ts BRDI (DATA) D93TL063B SIG = 0 T = 488ns±61 (2048Kb/s) SIG = 1 T = 15.6µs±61 (64Kb/s) T’ = 488ns ±61 (RCLI e BRDI not used) Figure 18: HCR and LCR versus configuration bits. RCLI DPI CLOCK RECOVERED FROM THE LINE RCLO XTAL2 SHCR 1 Q=32764KHz DPIS 1 XTAL1 CENTER DPLL FROZEN 3 2,4 & 8M 3 2,4 & 8M DIVIDER LTM 3 1 MCR0/1 2 SELECT 2,4 & 8MHz HCR 8KCR DIVIDER 4 & 8KHz LCR D95TL232A 38/46 STLC5432 Figure 18a: High Clock and Low Clock in LT and TE Mode t=30.5ns XTAL1 { LT MODE ONLY tpd THCR/2 THCR THCR/2 tpd HCR TL TLCR TLCR LCR td td 8MCR 1 (8MHz) 0 (4MHz) THCR 122ns 8KCR 1 (8MHz) 0 (4KHz) TLCR 125µs 250µs D93TL064C td td 244ns LTM = 1 LT MODE HCR AND LCR ARE GENERATED BY CLOCK APPLIED TO XTAL1 PIN. JITTER FILTER IS NOT VALIDATED LTM = 0 LE MODE HCR AND LCR CLOCK ARE RECOVERED FROM THE LINE VIA JITTER FILTER Figure 19: Double Clock Pulse Timing. BIT 0; TS 0 T T LCLK tH ts LFSX LFSR tpd tpdz DOUT tH ts DIN DCP = 1 DOUBLE CLOCK PULSE T = 244ns MULTIPLEX AT 2Mb/s T = 122ns MULTIPLEX AT 4Mb/s T = 61ns MULTIPLEX AT 8Mb/s D93TL065A 39/46 STLC5432 Figure 20: Single Clock Delayed Mode. BIT n T LCLK tH ts LFSX LFSR tpd tpdz DOUT tH ts DIN DCP = 0 SINGLE PULSE T = 488ns MULTIPLEX AT 2Mb/s T = 244ns MULTIPLEX AT 4Mb/s T = 122ns MULTIPLEX AT 8Mb/s NOT DELAYED MODE BIT n IS THE FIRST BIT OF THE FRAME (125µs) BIT 0 TIME SLOT ZERO (LIKE GCI) DELAYED MODE BIT n IS THE LAST BIT OF THE FRAME (125µs) D93TL066A DEL = 0 DEL = 1 Figure 21: Multiplex Diagram LCLK DOUT 0 DOUT 1 DOUT 2 DOUT 3 3.9µs D93TL067 EX: FOUR ST5432 OUTPUTS WHEN CONNECTED TO THE SAME MULTIPLEX AT 8Mb/s 40/46 STLC5432 Figure 22: CCITT G703 HDB3 Pulse Template 269ns (244 + 25) 20% 10% V=100% 10% 20% 194ns (244 - 50) IDEAL PULSE 50% 244ns 219ns 10% 0% 10% 20% 10% (244 - 25) 10% 488ns (244 + 244) D93TL068 CCITT 32540 Figure 23: Allowed Jitter at the TE and LT Inputs (CCITT I431) A0 A1 PEAK TO PEAK JITTER AMPLITUDE (UI) A2 0 f0 f1 f2 20dB/DECADE SLOPE f3 f4 D93TL069A JITTER FREQUENCY (LOGARITHMIC SCALE) A0 20.5 IU A1 1.0 A2 0.2 IU f0 12 x 10-6 Hz f1 20Hz f2 3.6kHz f3 18kHz f4 100kHz 41/46 STLC5432 Multiplexed Motorola-like µP bus timing. (P0 = 0V; P1 = 5V) t WAS AS tWDS tASDS DS tRWS tRWH R/W tCSS t CSH CS tAAS tAAH tDV READ DATA VALID tDWS Signal name Corresponding pin AS DS R/W CS AD0/7 AS/ALE (13) DS/RD (21) R/W/WR (26) CS (35) A/D0 to A/D7 ( 4 ........30) D93TL071B tDF AD0/7 READ CYCLE AD0/7 ADDRESS VALID WRITE DATA VALID tDWH AD0/7 WRITE CYCLE Symbol tWAS tWDS tASDS tRWS tRWH tCSS tCSH tAAS tAAH AS Pulse Width DS Pulse Width AS low to DS high R/W to DS setup R/W hold after DS CS to DS setup CS hold after DS Address to AS setup Address hold after AS Parameter Min. 30 110 10 20 10 20 10 20 10 Max. Unit ns ns ns ns ns ns ns ns ns READ CYCLE Symbol tDV tDF Data Valid after DS Output Flat Delay Parameter Min. Max. 80 25 Unit ns ns WRITE CYCLE Symbol tDWS tDWH 42/46 Data to DS setup Data Hold after DS Parameter Min. 35 10 Max. Unit ns ns STLC5432 Multiplexed ST9-like µP bus timing. (P0 = 5V; P1 = 0V) AS tWAS tASDS DS tRWS tWDS tRWH R/W tCSS tCSH CS t AAS tAAH tDV READ DATA VALID tDWS Signal name Corresponding pin AS DS R/W CS AD0/7 AS/ALE (13) DS/RD (21) R/W/WR (26) CS (35) D93TL072B t DF AD0/7 READ CYCLE AD0/7 ADDRESS VALID WRITE DATA VALID tDWN AD0/7 WRITE CYCLE A/D0 to A/D7 ( 4 ........30) Symbol tWAS tWDS tASDS tRWS tRWH tCSS tCSH tAAS tAAH AS Pulse Width DS Pulse Width AS high to DS low R/W to DS setup R/W hold after DS CS to DS setup CS hold after DS Address to AS setup Address hold after AS Parameter Min. 30 110 10 20 10 20 10 20 10 Max. Unit ns ns ns ns ns ns ns ns ns READ CYCLE Symbol tDV tDF Data Valid after DS Output Flat Delay Parameter Min. Max. 80 25 Unit ns ns WRITE CYCLE Symbol tDWS tDWH Data to DS setup Data Hold after DS Parameter Min. 35 10 Max. Unit ns ns 43/46 STLC5432 Multiplexed Intel-like µP bus timing. (P0 = 5V; P1 = 5V) Signal name Corresponding pin ALE AS/ALE (13) CS (35) & DS/RD (21) CS (35) & R/W/WR (26) A/D0 to A/D7 ( 4 ........30) READ CYCLE tWA CS.RD CS.WR AD0/7 ALE tRR tRI CS.RD tAL tLA tRD tDF DATA ADDR WRITE CYCLE CS.WR tWW tWI tDW tWD AD0/7 DATA D93TL073B DATA READ CYCLE (Multiplexed Intel Mode) Symbol tLA tAL tRD tRR tDF tRI tWA tCSS tAAH Address Hold After ALE Address to ALE Setup Data Delay from RD RD Pulse Width Output Float Delay RD Control Interval ALE Pulse Width CS to RD or WR set-up tCSS CS hold after RD or WR tCSH 70 30 20 10 110 25 Parameter Min. 10 20 80 Max. Unit ns ns ns ns ns ns ns ns ns WRITE CYCLE (Multiplexed Intel Mode) Symbol tWW tDW tWD tWI WR Pulse Width Data Setup to WR Data Hold after WR WR Control Interval Parameter Min. 60 35 10 70 Max. Unit ns ns ns ns 44/46 STLC5432 TQFP44 (10 x 10) PACKAGE MECHANICAL DATA DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008 D D1 D3 A1 33 34 23 22 0.10mm .004 Seating Plane A A2 E3 E1 B 44 1 11 12 E B C L K e L1 TF4 QP4 45/46 STLC5432 I nformation furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 46/46