STLD125N4F6AG
Automotive N-channel 40 V, 2.4 mΩ typ., 120 A STripFET™ F6
Power MOSFET in a PowerFLAT™ 5x6 dual side cooling
Datasheet - preliminary data
Features
Order code
VDS
RDS(on) max.
ID
STLD125N4F6AG
40 V
3.0 mΩ
120 A
Designed for automotive applications
Very low on-resistance
Very low gate charge
High avalanche ruggedness
Low gate drive power loss
Applications
Switching applications
Figure 1: Internal schematic diagram
Description
D(5, 6, 7, 8)
This device is an N-channel Power MOSFET
developed using the STripFET™ F6 technology
with a new trench gate structure. The resulting
Power MOSFET exhibits very low RDS(on) in all
packages.
G(4)
S(1, 2, 3)
AM15540V4
Table 1: Device summary
Order code
Marking
Package
Packaging
STLD125N4F6AG
125
PowerFLAT™ 5x6 dual side cooling
Tape and reel
February 2016
DocID029009 Rev 1
This is preliminary information on a new product now in development
or undergoing evaluation. Details are subject to change without notice.
1/12
www.st.com
Contents
STLD125N4F6AG
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
4.1
5
2/12
PowerFLAT™ 5X6 dual side cooling package information ............... 9
Revision history ............................................................................ 11
DocID029009 Rev 1
STLD125N4F6AG
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
40
V
VGS
Gate-source voltage
± 20
V
ID(1)(2)
Drain current (continuous) at TC = 25 °C
120
A
ID(2)
Drain current (continuous) at TC = 100 °C
101
A
Drain current (pulsed)
480
A
Total dissipation at TC = 25 °C
130
W
- 55 to 175
°C
IDM(2)(3)
PTOT
(2)
TJ
Operating junction temperature range
Tstg
Storage temperature range
Notes:
(1)Limited
(2)The
by package.
value is rated according to Rthj-case bottom side.
(3)Pulse
width limited by safe operating area.
Table 3: Thermal data
Symbol
Rthj-c top side
Rthj-c bottom side
Rthj-pcb
(1)
Parameter
Value
Thermal resistance junction-case top side
2.9
Thermal resistance junction-case bottom side
1.14
Thermal resistance junction-pcb
31.3
Unit
°C/W
Notes:
(1)When
mounted on 1 inch² 2 Oz. Cu board, t ≤ 10 s
Table 4: Avalanche characteristics
Symbol
Parameter
Value
Unit
IAV
Avalanche current, repetitive or not repetitive (pulse width limited by
maximum junction temperature)
90
A
EAS
Single pulse avalanche energy (Tj = 25 °C, IC = IAV, VDD = 16 V)
150
mJ
DocID029009 Rev 1
3/12
Electrical characteristics
2
STLD125N4F6AG
Electrical characteristics
(TC= 25 °C unless otherwise specified)
Table 5: On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage Drain
current
IGSS
VGS = 0 V, ID = 1 mA
Min.
Typ.
Max.
40
Unit
V
VGS = 0 V, VDS = 16 V
1
µA
VGS = 0 V, VDS = 16 V,
Tj = 125 °C(1)
10
µA
Gate-body leakage current
VDS = 0 V, VGS = ± 20 V
±100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 1 mA
4
V
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 75 A
2.4
3
VGS = 6.5 V, ID = 75 A
2.7
3.5
Min.
Typ.
Max.
Unit
-
5600
-
pF
-
890
-
pF
-
560
-
pF
-
91
-
nC
-
28
-
nC
-
27
-
nC
Min.
Typ.
Max.
Unit
-
47
-
ns
-
300
-
ns
-
255
-
ns
-
220
-
ns
2
mΩ
Notes:
(1)Defined
by design. Not subject to production test.
Table 6: Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output
capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
VDS= 10 V, f = 1 MHz, VGS = 0 V
VDD = 32 V, ID = 75 A, VGS = 10 V (see
Figure 14: "Test circuit for gate charge
behavior")
Qgs
Gate-source
charge
Qgd
Gate-drain charge
Table 7: Switching times
Symbol
td(on)
Turn-on
delay time
tr
Rise time
td(off)
Turn-offdelay time
tf
4/12
Parameter
Test conditions
VDD = 30 V, ID = 75 A RG = 30 Ω,
VGS = 10 V (see Figure 13: "Test circuit for
resistive load switching times")
Fall time
DocID029009 Rev 1
STLD125N4F6AG
Electrical characteristics
Table 8: Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD(1)
Source-drain
current
-
120
A
ISDM(1)(2)
Source-drain
current
(pulsed)
-
480
A
-
1.2
V
Forward on
voltage
VSD (3)
trr
Reverse
recovery time
Qrr
Reverse
recovery
charge
IRRM
Reverse
recovery
current
VGS = 0 V, ISD = 90 A
ISD = 90 A, di/dt = 100 A/µs, VDD = 20 V
(see Figure 15: "Test circuit for inductive
load switching and diode recovery times")
-
40
ns
-
41
nC
-
2
A
Notes:
(1)Limited
by package.
(2)Pulse
width is limited by safe operating area
(3)Pulse
test: pulse duration = 300 µs, duty cycle 1.5%
DocID029009 Rev 1
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Electrical characteristics
2.1
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STLD125N4F6AG
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID029009 Rev 1
STLD125N4F6AG
Electrical characteristics
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs
temperature
Figure 12: Source-drain diode forward characteristics
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Test circuits
3
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STLD125N4F6AG
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID029009 Rev 1
STLD125N4F6AG
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
PowerFLAT™ 5X6 dual side cooling package information
Figure 19: PowerFLAT™ 5x6 dual side cooling package outline
Plated Area
8548760_1
DocID029009 Rev 1
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Package information
STLD125N4F6AG
Table 9: PowerFLAT™ 5x6 dual side cooling mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.66
0.71
0.76
A1
0.60
b
0.33
0.43
0.53
c
0.15
0.203
0.30
D
D1
5.00 BSC
4.06
D2
D3
0.75
4.21
4.36
2.40 BSC
2.80
E
3.30
3.80
6.00 BSC
E1
3.525
3.675
3.825
E2
1.05
1.20
1.35
E3
E4
3.80 BSC
4.20
e
4.70
5.20
1.27 BSC
I
0.15
L
0.15
0.25
0.35
L1
0.925
1.05
1.175
L2
0.45
0.575
0.70
ϑ
12° BSC
ϑ1
7° BSC
j
0.20 BSC
Figure 20: PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in
mm)
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DocID029009 Rev 1
STLD125N4F6AG
5
Revision history
Revision history
Table 10: Document revision history
Date
Revision
16-Feb-2016
1
DocID029009 Rev 1
Changes
First release.
11/12
STLD125N4F6AG
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12/12
DocID029009 Rev 1
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