STLD1TR

STLD1 Datasheet Power-line communication dual line driver Features QFN24 (4x4 mm) • • • • • Dual line driver suitable for differential or single-ended configuration Up to 18 V p-p single-ended, 36 V p-p differential output range Very high linearity for EMC compliance Externally configurable power amplifier topology Up to 1.5 ARMS max. current • • • • Embedded overtemperature protection Suitable for any narrow-band power-line communication (PLC) applications Available in QFN24 (4x4x1 mm) package -40 °C to +105 °C temperature range Applications • • Smart metering, smart grid and Internet of Things applications Suitable for application designs compliant with CENELEC, FCC and ARIB regulations Description The STLD1 line driver is a low-distortion, high-current dual power amplifier specifically designed for power-line communication applications, where high output current drives the AC power-line loads. Operating on a single 8-18 V supply, the STLD1 can deliver high output current up to 1.5 ARMS and an output voltage swing-up to 18 V peak-to-peak single-ended / 36 V peak-to-peak differential. Product status link STLD1 Order code STLD1 STLD1TR Package QFN24 (4x4 x1 mm) Packing Tray Tape and reel The STLD1 features a very low output impedance (down to 0.1 Ω in the typical configuration) to ensure efficient transfer of power to very low impedance loads, typically between 5 Ω and 100 Ω. The device has very low in-band and out-of-band two-tone intermodulation distortion (IM3) as well as very high spurious-free dynamic range (SFDR) to guarantee and meet CENELEC, ARIB and FCC emission requirements. It also features thermal shutdown as well as current sense output. DS12339 - Rev 2 - June 2018 For further information contact your local STMicroelectronics sales office. www.st.com STLD1 Block diagram 1 Block diagram Figure 2. STLD1 basic block diagram Thermal sense IBIAS 5V REG. Vbg DS12339 - Rev 2 page 2/13 STLD1 Pin descriptions 2 Pin configuration Figure 3. Pin connections Table 1. Pin descriptions Pin Name Description 1 PGND Power amplifier ground PA2_OUT Power amplifier 2 output PA1_OUT Power amplifier 1 output 6 PGND Power amplifier ground 7 PVCC 8-18 V power amplifier supply input 8 VCC 9 AGND 10 CSF_OUT 11 AVDD_5V 12 RSV0 Reserved - connect to AGND 13 PA1_INN Power amplifier 1 negative input 14 PA1_INP Power amplifier 1 positive input 2 3 4 5 DS12339 - Rev 2 8-18 V analog supply input for 5 V internal regulator and analog circuitry. It has to be externally shorted to PVCC Analog ground. It has to be externally shorted to PGND Power amplifier current feedback output 5 V internal regulator output Use ≥ 10 μF bypass capacitor to AGND page 3/13 STLD1 Pin descriptions DS12339 - Rev 2 Pin Name Description 15 PA2_INP Power amplifier 2 positive input 16 PA2_INN Power amplifier 2 negative input 17 RSV1 Reserved - leave floating 18 RSV2 Reserved - connect to AGND 19 RSV3 Reserved - connect to AGND 20 THERM Thermal feedback current output 21 IBIAS_IN Reference current input 22 TX_ON_2 23 TX_ON_1 24 PVCC Power amplifier supply input 25 Exposed pad It has to be connected to an AGND ground plane on PCB Enable for power amplifier 2 (active high) Force low to set PA2_OUT to Hi-Z ( approx. 30 kΩ ) Enable for power amplifier 1 (active high) Force low to set PA1_OUT to Hi-Z ( approx. 30 kΩ ) page 4/13 STLD1 Maximum ratings 3 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Min. Max. Unit PVCC, VCC Line driver supply voltage range PGND -0.3 20 V AVDD_5V 5 V internal regulator voltage range AGND -0.3 Min. (5.5, PVCC +0.3) V AGND - PGND Variations between different ground pins -0.3 +0.3 V PA_OUT PA output pin voltage range PGND -0.3 Min. (20, PVCC +0.3) V PA_IN PA input pin voltage range AGND -0.3 Min. (20, VCC +0.3) V PA_INP - PA_INN PA input differential voltage on the same amplifier -11 11 V All other pins AGND -0.3 Min. (5.5, AVDD_5V + 0.3) V(ESD) Maximum withstanding voltage range, ANSI-ESDAJEDEC_JS-001 human body model acceptance criteria: “normal performance” I(PA_OUT) PA repetitive RMS current -2 V +2 kV 1.5 Arms Table 3. Thermal characteristics Symbol Parameter T(J) Min. Max. Operating junction temperature 150 Peak junction temperature 170 TAMB Operating ambient temperature -40 105 TSTG Storage temperature -50 150 Unit °C Table 4. Thermal data DS12339 - Rev 2 Symbol Parameter Conditions RthJA Maximum thermal resistance junction-ambient steady-state Mounted on a 2s2p PCB, with a dissipating surface, connected through vias, on the bottom side of the PCB 35 °C/W Pd Continuous power dissipation Ta = 70 °C 2.3 W Typ. Unit page 5/13 STLD1 Electrical characteristics 4 Electrical characteristics T(AMB) = -40 to +105 °C, T(J) < 125 °C unless otherwise specified. Typical values are at T(AMB) = 25 °C. Table 5. Power supply characteristics Symbol Parameter V(PVCC) Line driver supply voltage I(PVCC)_RX Min. Typ. Max. Unit 8 Line driver supply current. Rx mode I(VCC)_RX I(PVCC)_TX Test conditions 15 18 350 400 560 850 No-load on AVDD_5V. Dual power amplifier configuration 40 54 No-load on AVDD_5V. Single power amplifier configuration 20 No-load on AVDD_5V Line driver supply current. Tx mode, no- load V(PVCC)_TH Line driver supply voltage turn-on threshold V(PVCC)_TL Line driver supply voltage turn-off threshold V(PVCC)_HYST Line driver supply voltage hysteresis V(AVDD_5V) 5 V regulator output voltage, no-load 7 6.1 4.5 V μA mA mA 7.4 V 6.5 V 0.5 V 5.2 5.5 V Table 6. Line driver characteristics DS12339 - Rev 2 Symbol Parameter Test conditions V(PAx_OUT) BIAS Power amplifier output. Bias voltage Rx mode PVCC/2 V Z(PA_OUT) RX Power amplifier output impedance in RX mode TX_EN low 30 kΩ V(PA_IN) BIAS Power amplifier input. Bias voltage Set through external resistor divider PVCC/2 V GBWP Power amplifier. Gainbandwidth product 149 MHz tON Power amplifier startup time TX_EN toggled low to high (1) 1 μs I(PA_OUT) Power amplifier output current Repetitive peak V(PA_OUT) HD2 Power amplifier output. 2nd harmonic distortion V(PAx_OUT) HD3 Power amplifier output. 3rd harmonic distortion V(PAx_OUT) THD Min. Typ. Max. 1.5 Unit A rms -73 dBc -76 dBc Power amplifier output. Total harmonic distortion -70 dB V(PAx_OUT) HD2 Power amplifier output. 2nd harmonic distortion -57 dBc V(PAx_OUT) HD3 Power amplifier output. 3rd harmonic distortion -76 dBc V(PAx_OUT)THD Power amplifier output. Total harmonic distortion -54 dB VCC = 18 V, V(PA_OUT) = 13 Vpp (single-ended), Rload = 50 Ω, f = 100 kHz V(PA_OUT) DC = PVCC/2 VCC = 18 V, V(PA_OUT) = 13 Vpp (single-ended), Rload = 50 Ω, f = 500 kHz, V(PA_OUT) DC = PVCC/2 page 6/13 STLD1 Electrical characteristics Symbol Parameter Test conditions C(PAx_INP), C(PAx_INN) Power amplifier input capacitance PA_IN+ vs. AGND, see (1) 10 pF PA_IN- vs. AGND, see (1) 10 pF PSRR Power supply rejection ratio 50 Hz -100 dB 1 kHz -88 dB CSF_RATIO Ratio between PA_OUT and CSF output current 106 A/A IBIAS_IN Reference current input Typical conditions 16 or 32 μA VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz (2) -72 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -71 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -67 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) -74 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -72 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -68 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz (2) -71 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -68 dB VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -65 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) -75 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) -73 dB VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) -68 dB IM3 in-band IM3 out-of-band DS12339 - Rev 2 In band 3rd order intermodulation distortion Out-of-band third-order intermodulation distortion Min. Typ. Max. Unit page 7/13 STLD1 Electrical characteristics Symbol SFDR Parameter Spurious-free dynamic range Test conditions Min. Typ. Max. Unit VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) 71 dBc VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) 68 dBc VCC = 15 V, Vout = 24 V p-p (differential), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) 65 dBc VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 50 kHz, f2 = 80 kHz, see (2) 69 dBc VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 200 kHz, f2 = 300 kHz, see (2) 68 dBc VCC = 15 V, Vout = 12 V p-p (singleended), Zload = 50 Ω, f1 = 450 kHz, f2 = 500 kHz, see (2) 67 dBc V(TX_ON_x) IL TX_ON_x pin input low level voltage AGND 0.95 V V(TX_ON_x) IH TX_ON_x pin input high level voltage 1.85 AVDD_5V V V(TX_ON_x) HYST TX_ON_x pin input voltage hysteresis 500 mV T1 Thermal sensor threshold see (2) 70 °C T2 Thermal sensor threshold see (2) 100 °C T3 Thermal sensor threshold see (2) 125 °C T4 Thermal sensor threshold see (2) 170 °C T_HYST Thermal sensor hysteresis see (2) 10 °C 1. Not tested in production, guaranteed by design. 2. Characterization data, not tested in production. Figure 4. Line driver test circuit (single-ended configuration) R2 R1 VCC R3 100k C2 100 nF 10k 40k PAx_INN - SIGNAL IN PAx_INP 100 nF R4 100k DS12339 - Rev 2 C3 PAx_OUT C1 + 1 uF R_LOAD 50R page 8/13 STLD1 Electrical characteristics Figure 5. Line driver test circuit (differential) C5 C8 27 pF 4.7 pF R2 R1 VCC 2k C2 100 nF 6k8 PA1_INN - R3 47k C3 PA1_OUT C1 IN+ PA1_INP + 22 uF 100 nF R4 47k C11 C10 27 pF C13 100 nF R6 47k 2k 10 ZLOAD 4 7 6k8 PA2_INN - C9 PA2_OUT C12 IN- T3 4.7 pF R7 R2 VCC 1 PA2_INP + 22 uF 100 nF R11 47k DS12339 - Rev 2 page 9/13 STLD1 Device characteristics 5 Device characteristics 5.1 Thermal protection Any overtemperature event forces the line driver to self-disable the power amplifiers, thus preventing the STLD1 from damage. The thermal feedback is provided on THERM pin by a current that is N times the IBIAS_IN input current, according to the relationship described in the following table. Table 7. Thermal current level vs. junction temperature 5.2 I(THERMAL) Junction temperature level 0 x I(IBIAS_IN) Tj < T1 1 x I(IBIAS_IN) T1 < Tj < T2 2 x I(IBIAS_IN) T2 < Tj < T3 3 x I(IBIAS_IN) T3 < Tj < T4 4 x I(IBIAS_IN) Tj > T4 Current feedback Current sense feedback is provided by CSF_OUT current output, proportional to the LD output current. The CSF_OUT current is converted into voltage by a resistor and compared with the current limit threshold set at system level. 5.3 Power management The STLD1 operates from a single 8-18 V external supply. It directly supplies the power amplifiers and the internal 5 V linear regulator for the analog and control circuitry. The block diagram for the power management is shown in the figure below. Figure 6. Power supply scheme PVCC VCC 8 V to 18 V + 5V Linear Reg. AVDD_5V Power amplifiers PA1_OUT PA2_OUT Internal circuitry AGND PGND DS12339 - Rev 2 page 10/13 STLD1 QFN24L (4x4 mm) package information 6.1 QFN24L (4x4x1 mm) package information Figure 7. QFN24L (4x4 mm) package outline Table 8. QFN24L (4x4 mm) package mechanical data Dim. mm Min. Typ. Max. 0.80 0.90 1.00 A1 0.02 0.05 A2 0.65 1.00 A3 0.20 A b 0.18 0.25 0.30 D 3.85 4.00 4.15 D2 2.50 2.60 2.70 E 3.85 4.00 4.15 E2 2.50 2.60 2.70 e L ddd DS12339 - Rev 2 0.50 0.35 0.40 0.45 0.08 page 11/13 STLD1 Revision history Table 9. Document revision history DS12339 - Rev 2 Date Revision Changes 25-Oct-2017 1 Initial release. 19-Jun-2018 2 Updated Section ● Device summary page 12/13 STLD1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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