STLQ50C50R

STLQ50 50 mA, 3 μA supply current low drop linear regulator Datasheet - production data Description The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environments where very low power consumption is required. SOT323-5L Its very low quiescent current (3 µA) results in extended battery life, making the device suitable for applications which have very long standby time. Features The PMOS pass element allows very good dropout values (200 mV at 25 mA IO and 350 mV at full load) without affecting the consumption characteristics.  2.3 V to 12 V input voltage range  50 mA maximum output current  3 µA quiescent current  Available in 1.8 V, 2.5 V, 3.3 V, 5.0 V and adjustable voltage  200 mV dropout voltage at 25 mA output current Housed in the very small SOT323-5L, it meets space-saving requirements in battery-powered equipment.  Internal thermal protection  Available in SOT323-5L package Applications  Portable/battery-powered equipment  Electronic sensors  Microcontroller power  Real-time clock backup power Table 1. Device summary SOT323-5L (T&R) Output voltage Marking STLQ50C18R 1.8 V Q18 STLQ50C25R 2.5 V Q25 STLQ50C33R 3.3 V Q33 STLQ50C50R 5.0 V Q50 STLQ50C-R Adjustable QAD July 2019 This is information on a product in full production. DocID13205 Rev 7 1/18 www.st.com Contents STLQ50 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 DocID13205 Rev 7 STLQ50 1 Block diagram Block diagram Figure 1. Block diagram (fixed version) 9,1 9287 %LDV JHQHUDWRU &XUUHQW OLPLW 7KHUPDO SURWHFWLRQ 23$03 %DQGJDS UHIHUHQFH *1' Figure 2. Block diagram (adjustable version) 9,1 9287 %LDV JHQHUDWRU &XUUHQW OLPLW 7KHUPDO SURWHFWLRQ 23$03 %DQGJDS UHIHUHQFH )% *1' DocID13205 Rev 7 3/18 18 Pin configuration 2 STLQ50 Pin configuration Figure 3. Pin connections (top view) $'-1&  *1'  1&   287  ,1 Table 2. Pin description Pin n° Note ADJ ADJ pin on the Adjustable version N/C Not connected on fixed version 2 GND Ground 3 N/C Not connected 4 IN 5 OUT 1 4/18 Symbol Input voltage Output voltage DocID13205 Rev 7 STLQ50 3 Maximum ratings Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit VI DC Input voltage -0.3 to +14 V VADJ ADJ pin voltage -0.3 to +7 V ESD Human body model ±2 kV Junction temperature -40 to 150 °C Storage temperature range -55 to 150 °C TJ TSTG Note: Parameter Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient SOT323-5L Unit 331.4 (1) °C/W 1. This value is referred to a 4-layer PCB, JEDEC standard test board. DocID13205 Rev 7 5/18 18 Electrical characteristics 4 STLQ50 Electrical characteristics VI = VO(NOM) +1 V or VI = 2.5 V if VO < 1.5 V; TA= -40 °C to 125 °C; IO = 1 mA; typical values are at TA = 25 °C, CO = 1 µF unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test conditions VI Input voltage range IQ Quiescent current (measured on ground pin, fixed version) VO Typ. Max. IO = 20 mA 2.3 12 IO = 50 mA 2.5 12 VI = 5 V 3.5 5.0 VI = 12 V 4.1 6.0 Unit V µA Output voltage range (STLQ50ADJ) 1.222 11 V Accuracy as percentage of nominal voltage at TJ = 25 °C -2 +2 % 0.7 V VDROP-MAX Max dropout voltage (1) VO Min. IO = 50 mA; 0.4 Load regulation 1 mA < IO < 50 mA 0.15 %/mA VO Line regulation VO = 1.5 V: VO + 1 V < VI < 12 V; VO < 1.5 V: 2.5 V < VI < 12 V; 0.3 %/V SVR Supply voltage rejection VRIPPLE = 0.1 V, IO = 20 mA, f = 120 Hz 30 dB eN Output noise voltage BW from 200 Hz to 100 kHZ; IO = 10 mA 560 µVRMS Th Thermal protection 160 °C 500 mA IOMAX Maximum output current (2) VO = 0 V 1. VI = 2.5 V when VO(NOM) 2.1 V 2. The maximum power dissipation must not be exceeded, see application information for details. 6/18 DocID13205 Rev 7 STLQ50 5 Typical application Typical application Figure 4. Fixed versions Figure 5. Adjustable version DocID13205 Rev 7 7/18 18 Typical characteristics 6 STLQ50 Typical characteristics Figure 6. VO vs. TJ Figure 7. VO vs. VI 1.84 2 1.8 1.6 1.82 VO [V] VO [V] 1.8 1.78 1.76 0.4 0.2 0 1.74 1.72 -50 VI=2.8V, IO=20mA -25 0 25 1.4 1.2 1 0.8 0.6 50 75 100 IO=50mA, VO=1.8V 0 125 1 2 3 Temp [°C] Figure 8. IQ vs. TJ 0.5 3.4 0.45 0.4 VDROP [V] Iq [µA] 3.3 3.2 3.1 3 -50 -25 0 25 50 75 100 0.35 0.3 0.25 0.2 0.15 0.1 0.05 VI=5V, IO=1mA, VO=1.8V 2.8 TA=25°C 0 125 0 10 20 Temp [°C] 0.6 ESR[] VDROP [V] 0.5 0.4 0.3 0.2 VO=2.45V, IO=50mA 0 -25 0 25 50 Temp [°C] 8/18 40 50 Figure 11. Stability 0.7 -50 30 IO [mA] Figure 10. VDROP vs. TJ 0.1 5 Figure 9. VDROP vs. IO 3.5 2.9 4 VI [V] 75 100 125 12 11 10 9 8 7 6 5 4 3 2 1 0 TA=25°C 0 1 2 3 CO[µF] DocID13205 Rev 7 4 5 STLQ50 Typical characteristics Figure 12. S.V.R. vs. Freq. 37 40 38 36 VO=1.8V, IO=20mA 32 27 SVR [dB] SVR [dB] Figure 13. S.V.R. vs. IO 22 17 12 7 2 100 1000 10000 34 32 30 28 26 24 22 20 VO=1.8V, f=120Hz 100000 0 10 Figure 14. Line transient response 30 40 50 Figure 15. Load transient response IO=50mA; CO=10µF; VI=2.8V, VI rise/fall=5ms CO=1µF; VO=1.8V; VI=2.8V, Curr. rise/fall=1µs Figure 16. Short-circuit current Figure 17. Thermal protection 0.6 2 VI=2.8V 1.75 0.5 1.5 VO[V] 0.4 IO [A] 20 IO [mA] Frequency [Hz] 0.3 1.25 1 0.75 0.2 0.5 0.25 0.1 VO=0, TA=25°C 0 0 155 157 159 2 4 6 8 VI [V] 10 12 14 DocID13205 Rev 7 161 163 165 167 169 171 173 175 TJ[°C] 9/18 18 Application information 7 STLQ50 Application information The STLQ50 is a BiCMOS linear regulator specifically designed for operating in environments with very low power consumption requirements. The very low quiescent current of 3 µA is obtained through the use of CMOS technology which makes the device suitable for application that have long standby time. Its very low power consumption allows extended battery life and the tiny packages (SOT323-5L) satisfy the space-saving requirements of battery-powered equipment. Moreover, the STLQ50 provides wide input voltage operation from 2.5 V up to 12 V. The PMOS pass element also permits a very good dropout values of 0.7 V at full load and at 125 °C without affecting consumption characteristics. 7.1 External components The typical application schematic of the STLQ50 is shown in Figure 4 - Figure 5, 1 µF input and output capacitors placed close to the device are required for proper operation. The device is stable with electrolytic and ceramic output capacitors having values higher than 1 µF (see Figure 11 for stability details). In the adjustable version the output voltage is programmed using an external resistor divider, as shown in Figure 5. The output voltage can be adjusted from 1.22 to 11 V and it can be calculated using the following equation: Equation 1 VO = VFB x (1+R1/R2) where VFB = 1.222 V is the internal reference voltage. The sum of the R1 and R2 resistors should be chosen in order to guarantee at least 1 µA of divider current. Lower value resistors improve the noise performance but the quiescent current will increase. Higher value resistors should be avoided because the ADJ leakage current will influence the voltage set by the resistor divider, rendering the formula above no longer valid. The suggested design procedure is to choose R2 = 1 M and then calculate R1 using the following equation: Equation 2 R1 = (VO/VFB-1) x R2 7.2 Power dissipation In order to ensure proper operation, the STLQ50 junction temperature should never exceed 125 °C; this limits the maximum power dissipation the regulator can sustain in any application. The maximum power dissipation can be calculated as: Equation 3 PDMAX = (TJMAX - TA)/RthJA where TJMAX = 125 °C; 10/18 DocID13205 Rev 7 STLQ50 Application information TA is the ambient temperature; RthJA is the junction-to-ambient thermal resistance of the package (seeTable 4 thermal data). The power dissipation can be calculated simply as: Equation 4 PD = (VI - VO) x IO In every application condition, PD must be lower than PDMAX. 7.3 Protection The PMOS pass element has an internal diode with anode connected to VO and cathode to VI. In case VO > VI, the current will flow from output to input without limitation. In this case, a proper limiting network is recommended. The current limitation is automatically provided by the characteristics of the PMOS pass element (see typical characteristics), so the short-circuit current is dependent on the input voltage. When considering short-circuit current, take care in any case not to exceed the maximum sustainable power dissipation of the device. The STLQ50 features an internal thermal protection that linearly reduces the output current when the internal temperature increases. Consequently, at a given load, the output voltage decreases also. The action of the thermal protection starts at 125 °C when the output voltage slightly decreases, while close to 163 °C the output voltage drops to 0 V. Since this is a linear control, sudden overcurrent conditions can quickly raise the chip temperature without giving time for the thermal protection to act, so it cannot be used as a limitation for the output current. DocID13205 Rev 7 11/18 18 Package mechanical data 8 STLQ50 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 12/18 DocID13205 Rev 7 STLQ50 Package mechanical data Figure 18. SOT323-5L drawing BI DocID13205 Rev 7 13/18 18 Package mechanical data STLQ50 Table 6. SOT323-5L mechanical data mm Dim. Min. 14/18 Typ. Max. A 0.80 1.10 A1 0 0.10 A2 0.80 b 0.15 0.30 c 0.10 0.22 D 1.80 2 2.20 E 1.80 2.10 2.40 E1 1.15 1.25 1.35 0.90 e 0.65 e1 1.30 L 0.26  0 DocID13205 Rev 7 0.36 1 0.46 8 STLQ50 9 Packaging mechanical data Packaging mechanical data Figure 19. SOT323-xL tape and reel drawing DocID13205 Rev 7 15/18 18 Packaging mechanical data STLQ50 Table 7. SOT323-xL tape and reel mechanical data mm Dim. Min. Typ. Max. A 175 180 185 C 12.8 13 13.2 D 20.2 N 59.5 60 60.5 T 16/18 14.4 Ao 2.25 Bo 3.17 Ko 1.2 Po 3.9 4.0 4.1 P 3.9 4.0 4.2 DocID13205 Rev 7 STLQ50 10 Revision history Revision history Table 8. Document revision history Date Revision Changes 07-Feb-2007 1 Initial release. 13-Feb-2007 2 Typo in cover page 350 mA ==> 350 mV. 06-Jul-2007 3 Added part number. 14-Nov-2007 4 Added Table 1. 31-Jan-2013 5 – Modified line regulation test condition Table 5 on page 6. – Minor text changes throughout the document. 09-May-2014 6 Part number STLQ50xx changed to STLQ50. Removed SOT23-5L package. Updated Table 1: Device summary, Section 1: Block diagram, Section 2: Pin configuration,Section 3: Maximum ratings, Section 5: Typical application, Section 7: Application information, Section 8: Package mechanical data. Added Section 9: Packaging mechanical data. Minor text changes. 19-Jul-2019 7 Added Marking in Table 1: Device summary on the cover page. DocID13205 Rev 7 17/18 18 STLQ50 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved 18/18 DocID13205 Rev 7