STLVD111

STLVD111 Programmable low voltage 1:10 differential LVDS clock driver Features ■ ■ ■ ■ ■ ■ ■ ■ ■ 100ps part-to part skew 50ps bank skew Differential design Meets LVDS spec. for driver outputs and receiver inputs Reference voltage available output VBB Low voltage VCC range of 2.375V to 2.625V High signalling rate capability (exceeds 622MHz) Support open, short and terminated input failsafe (low output state) Programmable drivers power off control STLVD111 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. TQFP32 Description The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs. The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The Order codes Part number STLVD111BFR May 2007 Temperature range -40 to 85 °C Package TQFP32 (Tape & Reel) Rev. 8 Packaging 2400 parts per reel 1/19 www.st.com 19 STLVD111 Contents 1 2 3 4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Specification of control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 4.2 Programmed mode (EN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standard mode (EN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 6 7 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 STLVD111 Pin configuration 1 Figure 1. Pin configuration Pin connections 3/19 Pin configuration Table 1. Pin description Pin n° 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol CK SI CLK0 CLK0 VBB CLK1 CLK1 EN GND Q9 Q9 Q8 Q8 Q7 Q7 VCC Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 GND Q2 Q2 Q1 Q1 Q0 Q0 VCC Name and function Control register clock Control register serial IN/CLK_SEL Differential input Differential input Output reference voltage Differential input Differential input Device enable/program Ground Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Supply voltage Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Ground Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Differential outputs Supply voltage STLVD111 4/19 STLVD111 Maximum ratings 2 Table 2. Symbol VCC VI VO IOSD ESD Maximum ratings Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Driver short circuit current Electrostatic discharge (HBM 1.5KΩ, 100pF) Value -0.3 to 2.8 -0.2 to (VCC+0.2) -0.2 to (VCC+0.2) Continuous >2 KV Unit V V V Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Recommended operating conditions Parameter Supply voltage Receiver common mode input voltage Operating free-air temperature range Operating junction temperature Min. 2.375 0.5(VID) -40 -40 Typ. Max. 2.625 2-0.5(VID) 85 105 Unit V V °C °C Table 3. Symbol VCC VIC TA TJ Table 4. Symbol RthJC Thermal data Parameter Thermal resistance junction-case Value 13 Unit °C/W 5/19 Electrical characteristics STLVD111 3 Table 5. Symbol VOD ΔVOD VOS ΔVOS IOS Electrical characteristics Driver electrical characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified Note: 1, 2) Parameter Test condition Min. 400 Typ. 500 Max. 600 30 -40 ≤TA ≤85°C 1.05 1.15 1.25 30 VO = 0V VOD = 0V 15 7 30 mA 15 Unit mV mV V V Output differential voltage (Figure 4.) RL = 100 Ω VOD magnitude change Offset voltage VOS magnitude change Output short circuit current Note: 1 2 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated Receiver electrical characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified Note: 1, 2) Parameter Input threshold high Input threshold low Input current VI = 0V VI = 0VCC -100 42 2 100 10 Test condition Min. Typ. Max. 100 Unit mV mV μA Table 6. Symbol VIDH VIDL IIN Note: 1 2 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated 6/19 STLVD111 Electrical characteristics Table 7. Symbol VBB ICCD CIN COUT VIH VIL II Driver electrical characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified Note: 1, 2) Parameter Output reference voltage Power supply current Input capacitance Output capacitance Logic input high threshold Logic input low threshold Logic input current VCC = 2.5 V VCC = 2.5 V VCC = 2.5 V, VIN = VCC or GND 2 0.8 ±10 Test condition VCC = 2.5 V All driver enabled and loaded VI = 0V to VCC Min. 1.15 Typ. 1.25 125 5 5 Max. 1.35 160 Unit V mA pF pF V V µA Note: 1 2 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated LVDS timing characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified) Parameter Transition time Propagation delay time Maximum input frequency Bank skew (Figure 3.) (Figure 4.) (Figure 5.) Test condition RL = 100 Ω CL = 5 pF, , Figure 7., Figure 8.) (Figure 7., Figure 8.) 700 Min. Typ. 220 2 900 50 100 50 ps Max. 300 2.5 Unit ps ns MHz Table 8. Symbol tTLH, tTHL tPHL, tPLH fMAX tSKEW Part to part skew Pulse skew Table 9. Symbol fMAX ts th trem tW Control register timing characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified) Parameter Test condition Min. 100 Typ. 150 2 1.5 1.5 3 Max. Unit MHz ns ns ns ns Maximum frequency of shift register (Figure 9.) Clock to SI setup time Clock to SI hold time Enable to clock removal time Minimum clock pulse width (Figure 9.) (Figure 9.) (Figure 9.) (Figure 9.) 7/19 Specification of control register STLVD111 4 Specification of control register The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides two working modality: 4.1 Programmed mode (EN=1) The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on. The last bit is the clock selection bit. To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register can be configured on time after each reset. 4.2 Standard mode (EN=0) In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The LVDS clock input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth Table below. Table 10. EN L L H H L Truth table of state machine inputs SI L H L H X CK X X Output All output enabled, Clock 0 selected, control register disabled All output enabled, Clock 1 selected, control register disabled First stage stores "L", other stages store the data of previous stage First stage stores "H", other stages store the data of previous stage Reset of the state machine, shift register and control register Table 11. BIT#10 CLK_SEL Serial input sequence BIT#9 Q0 BIT#8 Q1 BIT#7 Q2 BIT#6 Q3 BIT#5 Q4 BIT#4 Q5 BIT#3 Q6 BIT#2 Q7 BIT#1 Q8 BIT#0 Q9 Table 12. Truth table of the control register BIT#10 L H X BIT#(0-9) H H L Qn(0-9) Clock 0 Clock 1 Qn Output Disabled 8/19 STLVD111 Specification of control register Table 13. CK L L L L L L Truth table EN L L L L L L All drivers enable SI L L L H H H CLK 0 L H Open X X X CLK 0 H L Open X X X CLK 1 X X X L H Open CLK 1 X X X H L Open Q (0-9) L H L L H L Q(0-9) H L H H L H 9/19 Diagram STLVD111 5 Figure 2. Diagram Logic diagram 10/19 STLVD111 Diagram Figure 3. Bank skew - tsk(b) (1) 1. BANKSKEW is the magnitude of the time difference between outputs with a single driving input terminal Figure 4. Part to part skew - tsk(PP) (1) 1. PART TO PART SKEW is the magnitude of the difference in propagation delay times between any specific terminals of two devices when both devices operate with the same input signals, the same supply voltages, and the same temperature, and have identical packages and test circuits. 11/19 Diagram STLVD111 Figure 5. Pulse skew - tsk(P) (1) 1. PULSE SKEW is the magnitude of the time difference between the high to low and low to high propagation delay times at an output. Figure 6. Voltage and current definition 12/19 STLVD111 Diagram Figure 7. Test circuit and voltage definition for the differential output signal . Figure 8. Differential receiver to drive propagation delay and drive transition time waveforms 13/19 Diagram STLVD111 Figure 9. Set-Up, hold and the removal time, maximum frequency, minimum pulse width waveforms 14/19 STLVD111 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 15/19 Package mechanical data STLVD111 TQFP32 MECHANICAL DATA mm. DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0° 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 3.5° 7° 0° 0.75 0.018 1.40 0.37 TYP MAX. 1.6 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.0035 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 3.5° 7° 0.030 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.0079 inch D D1 D3 A1 17 16 0.10mm .004 Seating Plane A A2 24 25 E3 E1 B 32 1 8 9 E B C e L1 L K TQFP32 0060661/C 16/19 STLVD111 Package mechanical data Tape & Reel TQFP32 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.5 9.5 2.1 3.9 11.9 12.8 20.2 60 22.4 9.7 9.7 2.3 4.1 12.1 0.374 0.374 0.083 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.382 0.382 0.091 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 17/19 Revision history STLVD111 7 Table 14. Date Revision history Revision history Revision 8 Changes Order codes has been updated and the document has been reformatted. 30-May-2007 18/19 STLVD111 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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