STLVD210

STLVD210 DIFFERENTIAL LVDS CLOCK DRIVER s s s s s s s s s 100ps PART-TO-PART SKEW 50ps BANK SKEW DIFFERENTIAL DESIGN MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS REFERENCE VOLTAGE AVAILABLE OUTPUT VBB LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 700MHz) SUPPORT OPEN, SHORT, AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE) PROGRAMMABLE DRIVERS POWER OFF CONTROL TQFP32 DESCRIPTION The STLVD210 is a low skew programmable 1-to-5 dual differential LVDS driver, designed with clock distribution in mind. The LVDS input signals can be either differential or single-ended if the VBB output is used. The STLVD210 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The ORDERING CODES Type STLVD210BF STLVD210BFR Temperature Range -40 to 85 °C -40 to 85 °C Package STLVD210 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD210 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can be take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. Comments 250 parts per Tray 2400 parts per reel TQFP32 (Tray) TQFP32 (Tape & Reel) December 2002 1/9 STLVD210 PIN CONFIGURATION PIN DESCRIPTION PlN N° 1 2 3, 4, 6, 7 5 8 9, 25 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31 16, 32 SYMBOL CK SI CLKn/CLKn VBB EN GND Qn0:4/Qn0:4 VCC NAME AND FUNCTION Control Register Clock Control Register Serial IN/CLK_SEL LVDS CLK Inputs Reference Voltage Output Device Enable/Program GROUND LVDS Supply Voltage 2/9 STLVD210 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IOSD ESD Supply Voltage Input Voltage Output Voltage Driver Short Circuit Current Electrostatic Discharge (HBM 1.5KΩ, 100pF) Parameter Value -0.3 to 2.8 -0.2 to (VCC+0.2) -0.2 to (VCC+0.2) Continuous >2 KV Unit V V V Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. THERMAL DATA Symbol RTj-c Parameter Thermal Resistance Junction-Case Value 13 Unit °C/W RECOMMENDED OPERATING CONDITIONS Symbol VCC VIC TOPR TJ Supply Voltage Receiver Common Mode Input Voltage Operating Free-Air Temperature Range Operating Junction Temperature Parameter Min 2.375 0.5(VID) -40 -40 TYP Max 2.625 2-0.5(VID) 85 105 Unit V V °C °C 3/9 STLVD210 DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol VOD ∆VOD VOS ∆VOS IOS Parameter Output Differential Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Output Short Circuit Current VO = 0V VOD = 0V 15 7 1.05 1.15 RL = 100 Ω Test Conditions Min. 400 Typ. 500 Max. 600 30 1.25 30 30 15 mV mV V mV mA Unit NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. RECEIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol VIDH VIDL IIN Parameter Input Threshold High Input Threshold Low Input Current VI = 0V VI = VCC -100 42 2 100 10 Test Conditions Min. Typ. Max. 100 mV mV µA Unit NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol VBB ICCD CIN COUT VIH VIL II Parameter Output Reference Voltage Power Supply Current Input Capacitance Output Capacitance Logic Input High Threshold Logic Input Low Threshold Logic Input Current VCC = 2.5 V VCC = 2.5 V VCC = 2.5 V, VIN = VCC or GND 2 0.8 ±10 Test Conditions Min. VCC = 2.5 V IBB = 0.5 mA 1.15 All driver enabled and loaded All driver disabled VI = 0V to VCC Typ. 1.25 125 18 5 5 Max. 1.35 180 25 V mA pF pF V V µA Unit NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 4/9 STLVD210 LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol tTLH tTHL fMAX tSKEW Parameter Transition Time Low to High Transition Time High to Low Maximum Input Frequency Bank Skew Part-to-Part Skew Pulse Skew 700 Test Conditions Min. RL = 100 Ω, CL = 5 pF Typ. 220 220 2 900 50 100 60 Max. 300 300 2.5 ps ps ns MHz ps Unit tPHL, tPLH Propagation Delay to Output NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. SPECIFICATION OF CONTROL REGISTER The STLVD210 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose is to enable or power of each output clock channel. The STLVD210 provides two working modality: PROGRAMMED MODE (EN=1) The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11-clock pulse, another clock pulse loads the configuration into the control register. The first bit on the serial input line enables the outputs Qb4 and Qb4, the second bit enables the outputs Qb3 and Qb3 and so on. The last bit is the fewer significations. To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register can be configured on time after each reset. STANDARD MODE (EN=0) In Standard Mode the STLVD210 isn’t programmable, all the clock outputs are enabled. TRUTH TABLE OF STATE MACHINE INPUTS EN L H H L SI X L H X CK X OUTPUT All Outputs Enable First stage stores "L", other stages store the data of previous stage First stage stores "H", other stages store the data of previous stage Reset of the state machine, Shift register and Control Register SERIAL INPUT SEQUENCE BIT#10 N.A. BIT#9 Qa0 BIT#8 Qa1 BIT#7 Qa2 BIT#6 Qa3 BIT#5 Qa4 BIT#4 Qb0 BIT#3 Qb1 BIT#2 Qb2 BIT#1 Qb3 BIT#0 Qb4 5/9 STLVD210 TRUTH TABLE OF SEQUENCE BIT#10 X X BIT#10 X X BIT#(0-4) L H BIT#(5-9) L H Qb(0-4) OFF ON Qa(0-4) OFF ON TRUTH TABLE CLKa H L CLKb H L CLKa L H CLKb L H Qa (0-4) H L Qb (0-4) H L Qa (0-4) L H Qb (0-4) L H 6/9 STLVD210 TQFP32 MECHANICAL DATA mm. DIM. MIN. A A1 A2 B C D D1 D3 E E E1 E3 L L1 K 0˚ 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 3.5˚ 7˚ 0˚ 0.75 0.018 1.40 0.37 TYP MAX. 1.6 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.0035 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 3.5˚ 7˚ 0.030 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.0079 inch D D1 D3 A1 17 16 0.10mm .004 Seating Plane A A2 24 25 E3 E1 B E 32 1 8 9 B C L K e L1 TQFP32 0060661/C 7/9 STLVD210 Tape & Reel TQFP32 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.5 9.5 2.1 3.9 11.9 12.8 20.2 60 22.4 9.7 9.7 2.3 4.1 12.1 0.374 0.374 0.083 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.382 0.382 0.091 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 8/9 STLVD210 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 9/9