STLVDS105BDR

STLVDS105 4-PORT LVDS AND 4-PORT TTL-TO LVDS REPEATERS s s s s s s s RECEIVER AND DRIVERS MEET OR EXCEED THE REQUIREMENTS OF ANSI EIA/TIA-644 STANDARD: RECEIVERS LOW-VOLTAGE TTL (LVTTL) LEVELS DESIGNED FOR SIGNALING RATES UP TO 630Mbps OPERATES FROM A SINGLE 3.3V SUPPLY LOW VOLTAGE DIFFERENTIAL SIGNALING WITH TYPICAL OUTPUT VOLTAGE OF 350mV AND A 100Ω LOAD PROPAGATION DELAY TIME: 2.2ns (TYP) ELECTRICALLY COMPATIBLE WITH LVDS, PECL, LVPECL, LVTTL, LVCOMOS, GTL, BTL, CTT, SSTL, OR HSTL OUTPUTS WITH EXTERNAL NETWORK BUS TERMINAL ESD (HBM) EXCEEDS 7KV SO AND TSSOP PACKAGING SOP TSSOP DESCRIPTION The STLVDS105 is a differential line receiver and a LVTTL input connected to four differential line drivers that implement the electrical characteristics of low voltage differential signaling, for point to point baseband data transmission over controlled impedance media of approximately 100Ω. The transmission media can be printed-circuit board traces, backplanes, or cable. ORDERING CODES Type STLVDS105BD STLVDS105BDR STLVDS105BTR Temperature Range -40 to 85 °C -40 to 85 °C -40 to 85 °C LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low noise coupling, and switching speed to transmit data at a speed up to 630Mbps at relatively long distances. The drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allow extremely precise timing alignment of the signals repeated from the input. The device allows extremely precise timing alignment of the signal repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. Package SO-16 (Tube) SO-16 (Tape & Reel) TSSOP16 (Tape & Reel) Comments 50parts per tube / 20tube per box 2500 parts per reel 2500 parts per reel May 2003 1/8 STLVDS105 PIN CONFIGURATION FUNCTIONAL DIAGRAM PIN DESCRIPTION PlN N° 1, 2, 3, 8 6 7 9, 11, 13, 15 10, 12, 14, 16 5 4 SYMBOL EN1 to EN4 A NC 1Z to 4Z 1X to 4X GND VCC NAME AND FUNCTION Enable Driver Inputs Receiver Input Not Connected Driver Inputs Driver Inputs Ground Supply Voltage FUNCTIONAL TABLE INPUT A L H Open X X ENABLES #EN H H H L X #Y L H L Z Z OUTPUTS #Z H L H Z Z L=Low level, H=High Level, Z= High Impedance ABSOLUTE MAXIMUM RATINGS Symbol VCC VR ESD Tstg Supply Voltage (Note 1) Voltage Range ESD Protection Voltage (HBM) Storage Temperature Range Enable Inputs A, Y or Z Y, Z, to GND All Pins Parameter Value -0.5 to 4 -0.5 to 6 -0.5 to 4 7 2 -65 to +150 Unit V V V KV KV °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal. 2/8 STLVDS105 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL |VID| VIC TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage Magnitude Of Differential Input Voltage Common Mode Input Voltage Operating Temperature Range 0.1 |VID|/2 -40 Parameter Min. 3.0 2.0 0.8 3.6 24-|VID|/2 VCC-0.8 85 °C Typ. 3.3 Max. 3.6 Unit V V V V V ELECTRICAL CHARACTERISTICS (TA = -40 to 85°C, and VCC = 3.3V ±10% over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C) Symbol |VOD| ∆|VOD| ∆VOC(SS) Parameter Differential Output Voltage Magnitude Change in Differential Output Voltage Magnitude Between Logic State Change in Steady-state Common Mode Output Voltage Between Logic State Steady-state Common Mode Output Voltage Peak to Paek Common mode Output Voltage Supply Current High Level Input Current Low Level Input Current RL = 100Ω Test Conditions VID = ±100mV Min. 247 -50 Typ. 340 Max. 454 50 Unit mV mV -50 50 mV VOC(SS) VOC(PP) ICC IIH IIL IOC IOZ IO(OFF) CIN CO 1.125 1.2 25 1.375 150 28 1 20 10 ± 10 ± 10 ±1 V mV mA mA µA µA mA mA µA µA pF pF Enabled, RL = 100Ω Disabled VIH = 2V VIL = 0.8V VOD = 0 18 0.3 7 3 Short Circuit Output Current VO(Y) or VO(Z) = 0V High Impedance Output Current Power OFF Output Current VO = 0 or 2.4V VCC = 1.5V VO = 2.4V 0.3 5 9.4 ±1 Input Capacitance (A or B VI = 0.4 sin (4e6πt)+0.5V Inputs) Output Capacitance (Y or Z V = 0.4 sin (4e6πt)+0.5V, Disabled I Outputs) 3/8 STLVDS105 SWITCHING CHARACTERISTICS (TA = -40 to 85°C, and VCC = 3.3V unless otherwise noted. All typical values are at TA = 25°C) Symbol tPLH tPHL tr tf tsk(P) tsk(O) tsk(pp) tPZH Parameter Propagation Delay Time, Low to High Output Propagation Delay Time, High to Low Output Differential Output Signal Rise Time Differential Output Signal Fall Time Pulse Skew (|tTHL - tTLH|) Channel-to-channel Output Skew (note1) Part to part Skew (note2) Propagation Delay Time, High Impedance to High Level Output Propagation Delay Time, High Impedance to Low Level Output Propagation Delay Time, High Level to High Impedance Output Propagation Delay Time, Low Level to High Impedance Output RL = 100Ω Test Conditions CL = 10pF Min. 1.7 1.7 0.3 0.3 Typ. 2.2 2.2 0.7 0.7 50 30 Max. 3 3 1.2 1.2 200 100 1.5 5 15 Unit ns ns ns ns ps ps ns ns tPZL 5 15 ns tPHZ 4 15 ns tPLZ 5 15 ns Note 1: tsk(O) is the time difference between the tPLH or tPHL of all drivers of a single device with all their inputs connected together. Note 2: tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuit. 4/8 STLVDS105 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25°C) Figure 1 : Output Current vs Output High Voltage Figure 3 : High to Low Propagation Delay Time Figure 2 : Output Current vs Output Low Voltage Figure 4 : Low to High Propagation Delay Time 5/8 STLVDS105 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 8 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 ˚ (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45˚ (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.008 0.064 0.018 0.010 PO13H 6/8 STLVDS105 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 7/8 STLVDS105 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8