STM32F479xx
Arm®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,
Ethernet, FMC, dual Quad-SPI, Crypto, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI
Datasheet - production data
Features
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone
2.1), and DSP instructions
Memories
– Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
– Up to 384+4 KB of SRAM including 64 KB of
CCM (core coupled memory) data RAM
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR, SDRAM, Flash
NOR/NAND memories
– Dual-flash mode Quad-SPI interface
Graphics
– Chrom-ART Accelerator™ (DMA2D),
graphical hardware accelerator enabling
enhanced graphical user interface with
minimum CPU load
– LCD parallel interface, 8080/6800 modes
– LCD TFT controller supporting up to XGA
resolution
– MIPI® DSI host controller supporting up to
720p 30 Hz resolution
Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
(1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
3× 12-bit, 2.4 MSPS ADC: up to 24 channels and
7.2 MSPS in triple interleaved mode
2× 12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two
32-bit timers up to 180 MHz, each with up to four
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer
May 2021
This is information on a product in full production.
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 × 28 mm)
UFBGA169 (7 × 7 mm)
WLCSP168
UFBGA176 (10 x 10 mm)
TFBGA216 (13 x 13 mm)
Debug mode
– SWD and JTAG interfaces
– Cortex®-M4 Trace Macrocell™
Up to 161 I/O ports with interrupt capability
– Up to 157 fast I/Os up to 90 MHz
– Up to 159 5 V-tolerant I/Os
Up to 21 communication interfaces
– Up to three I2C interfaces (SMBus/PMBus)
– Up to four USARTs and four UARTs
(11.25 Mbit/s, ISO7816 interface, LIN, IrDA,
modem control)
– Up to six SPIs (45 Mbits/s), two with muxed
full-duplex I2S for audio class accuracy via
internal audio PLL or external clock
– 1x SAI (serial audio interface)
– 2× CAN (2.0B Active)
– SDIO interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit parallel camera interface up to
54 Mbytes/s
Cryptographic accelerator
– HW accelerator for AES 128, 192, 256,
Triple DES, HASH (MD5, SHA-1, SHA-2)
and HMAC
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
Table 1. Device summary
Reference
Part numbers
STM32F479xx
STM32F479AI, STM32F479AG, STM32F479BI,
STM32F479BG, STM32F479II, STM32F479IG,
STM32F479NI, STM32F479NG, STM32479VG,
STM32479VI, STM32479ZG, STM32479ZI
DS11118 Rev 7
1/220
www.st.com
Contents
STM32F479xx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1
2
1.1.1
LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.2
LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.3
UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.4
TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1
Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21
2.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21
2.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
2.6
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.10
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.12
DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.13
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
2.15
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.16
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.17
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.18
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.19
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.20
2/220
Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.19.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.19.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.20.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.20.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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STM32F479xx
Contents
2.20.3
3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35
2.21
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35
2.22
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.23
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.4
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.5
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.25
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.26
Universal synchronous/asynchronous receiver transmitters (USART) . . 40
2.27
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.28
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.29
Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.30
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.31
Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.32
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 42
2.33
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 43
2.34
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.35
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 44
2.36
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44
2.37
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.38
Cryptographic accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.39
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.40
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.41
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.42
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.43
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.44
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.45
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Contents
STM32F479xx
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1
4/220
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.2
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.3
Operating conditions at power-up / power-down (regulator ON) . . . . . . 96
5.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 96
5.3.5
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 96
5.3.6
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.12
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 123
5.3.13
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.14
MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.15
MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.16
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.17
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3.18
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132
5.3.19
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.20
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.21
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.22
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.23
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.24
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DS11118 Rev 7
STM32F479xx
6
7
Contents
5.3.25
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.26
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.27
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.28
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.3.29
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.3.30
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.3.31
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 186
5.3.32
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 187
5.3.33
SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 189
5.3.34
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.2
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3
WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.4
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.5
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.6
UFBGA(176+25) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.7
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.8
TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.9
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 217
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
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List of tables
STM32F479xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
6/220
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F479xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STM32F479xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
STM32F479xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 101
Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 103
Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 104
Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 107
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DS11118 Rev 7
STM32F479xx
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
List of tables
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 126
DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 167
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 167
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 169
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172
DS11118 Rev 7
7/220
8
List of tables
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
8/220
STM32F479xx
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190
Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
WLCSP168 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 201
LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 208
LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
TFBGA216 - Recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . 213
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 217
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
DS11118 Rev 7
STM32F479xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM32F479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32F479xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 29
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 34
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 35
STM32F47x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F47x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F47x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32F47x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32F47x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32F47x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32F47x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
STM32F47x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 107
Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 108
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 127
MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
DS11118 Rev 7
9/220
11
List of figures
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
10/220
STM32F479xx
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 161
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 161
12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 166
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 168
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 171
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 180
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 181
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Quad-SPI SDR timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
WLCSP168 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LQFP208 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
LQFP208 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
DS11118 Rev 7
STM32F479xx
Figure 97.
Figure 98.
Figure 99.
Figure 100.
List of figures
LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
TFBGA216 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
DS11118 Rev 7
11/220
11
Description
1
STM32F479xx
Description
The STM32F479xx devices are based on the high-performance Arm®(a) Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F479xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
a true random number generator (RNG), and a cryptographic acceleration cell. They also
feature standard and advanced communication interfaces:
Up to three I2Cs
Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI)
Two CANs
One SAI serial audio interface
An SDMMC host interface
Ethernet and camera interface
LCD-TFT display controller
Chrom-ART Accelerator™
DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a
cryptographic acceleration cell. Refer to Table 2 for the list of peripherals available on each
part number.
The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving mode allows the design of low-power applications.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12/220
DS11118 Rev 7
STM32F479xx
Description
The STM32F479xx devices are offered in eight packages, ranging from 100 to 216 pins.
The set of included peripherals changes with the device chosen, according to Table 2.
These features make the STM32F479xx microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Figure 5 shows the general block diagram of the device family.
Flash memory in Kbytes
SRAM in
Kbytes
System
384(160+32+128+64)
Backup
4
Yes
Quad-SPI
Yes
Ethernet
No
Yes
Generalpurpose
10
Advancedcontrol
2
Basic
2
Random number generator
SPI / I
2S
Yes
4/2(full
duplex)(1)
I2C
USART/UART
STM32F479Nx
1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048
FMC memory controller
Timers
STM32F479Bx
STM32F479Ix
STM32F479Ax
Peripherals
STM32F479Zx
STM32F479Vx
Table 2. STM32F479xx features and peripheral counts
6/2(full duplex)(1)
3
4/3
4/4
Communication USB OTG FS
interfaces
USB OTG HS
Yes
Yes
CAN
2
SAI
1
SDIO
Yes
Camera interface
Yes
DS11118 Rev 7
13/220
47
Description
STM32F479xx
LCD-TFT
Yes
Chrom-ART Accelerator™
(DMA2D)
Yes
Cryptography
Yes
GPIOs
71
12-bit ADC
Number of channels
131
114
14
161
161
20
24
Yes
2
Maximum CPU frequency
180 MHz
1.7 to 3.6V(2)
Operating voltage
Package
131
3
12-bit DAC
Number of channels
Operating temperatures
STM32F479Nx
Yes
STM32F479Bx
MIPI-DSI Host
STM32F479Ix
STM32F479Ax
STM32F479Zx
Peripherals
STM32F479Vx
Table 2. STM32F479xx features and peripheral counts (continued)
Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
Junction temperature: −40 to 105 °C / −40 to 125 °C
LQFP100
LQFP144
UFBGA169 LQFP176
WLCSP168 UFBGA176
LQFP208
TFBGA216
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).
For information on the device errata with respect to the datasheet and reference manual
refer to the errata sheet (ES0321), available from the STMicroelectronics website
www.st.com.
14/220
DS11118 Rev 7
STM32F479xx
1.1
Description
Compatibility throughout the family
STM32F479xx devices are not compatible with other STM32F4xx devices.
Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and
LQFP208 packages (highlighted pins).
The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices,
only few IO port pins are substituted, as shown in Figure 3 and Figure 4.
The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other
STM32F4xx devices.
DS11118 Rev 7
15/220
47
Description
1.1.1
STM32F479xx
LQFP176 package
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
PH11
PH10
PH7
DS11118 Rev 7
PH9
84 85 86 87
PH8
86 87 88
PB15
85
PB14
84
PB13
STM32F4xx
LQFP176
PB12
PI0
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDUSB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
VSSDSI
DSIHOST_D1N
DSIHOST_D1P
VDD12DSI
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDSI
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PH7
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
1. Pins from 85 to 133 are not compatible.
16/220
PI2
135 134 133
135 134 133
STM32F469xx/479xx
LQFP176
PI3
VSS
PI1
PI3
VSS
Figure 1. Incompatible board design for LQFP176 package
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
MS38294V2
STM32F479xx
1.1.2
Description
LQFP208 package
Figure 2. Incompatible board design for LQFP208 package
STM32F469xx/479xx
LQFP208
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
PC6
VDDUSB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
VSSDSI
DSIHOST_D1N
DSIHOST_D1P
VDD12DSI
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDDSI
PD15
PD14
STM32F42x/STM32F43x
LQFP208
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
PC6
VDD
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PK2
PK1
PK0
VSS
VDD
PJ11
PJ10
PJ9
PJ8
PJ7
PJ6
PD15
PD14
MS38295V1
1. Pins from 118 to 128 and pin 137 are not compatible
DS11118 Rev 7
17/220
47
Description
1.1.3
STM32F479xx
UFBGA176 package
Figure 3. UFBGA176 port-to-terminal assignment differences
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
PE3
PE2
PE 1
PE0
PB8
PB5
PG14
PG13
PB 4
PB3
PD7
PC12
PA15
PA14
PA13
B
PE4
PE5
PE 6
PB9
PB7
PB6
PG15
PG12
PG11
PG10
PD6
PD0
PC11
PC10
PA12
C
VBA T
PI7
PI6
PI5
VDD
PDR
_ON
VDD
VDD
VDD
PG9
PD5
PD1
PI3
NC
PA11
D
PC13
PI8
PI9
PI4
VSS
BOO T0
VSS
VSS
VSS
PD4
PD 3
PD2
VDD12
DSI
PI1
PA10
E
PC14
PF0
PI10
PI11
DSI
HOST_
D1P
DSI
HOST_
D1N
PI0
PA 9
F
PC15
VSS
VDD
PH2
VSS
VSS
VSS
VSS
VSS
VSS
VCAP2
PC9
PA 8
G
PH0
VSS
VDD
PH3
VSS
VSS
VSS
VSS
VSS
VSS
VDD
PC8
PC7
H
PH1
PF2
PF1
PH4
VSS
VSS
VSS
VSS
VSS
VSS
DSI
VDD_
USB
PG8
PC6
J
NR ST
PF3
PF4
PH5
VSS
VSS
VSS
VSS
VSS
VDD
DSI
VDD
PG7
PG6
K
PF7
PF6
PF5
VDD
VSS
VSS
VSS
VSS
VSS
VCAP
DSI
PG5
PG4
PG3
DSI
HOST_
CKP
DSI
HOST_
CKN
PD15
PG2
L
PF10
PF9
PF8
BYPASS
_REG
M
VSSA
PC0
PC1
PC2
PC3
PB2
PG1
VSS
VSS
VCAP
_1
PH6
DSI
HOST_
D0P
DSI
HOST_
D0N
PD14
PD13
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
VDD
VDD
VDD
PE13
PH7
PD12
PD11
PD10
P
VREF+
PA2
PA6
PA5
PC5
PF12
PF15
PE 8
PE 9
PE11
PE14
PB 12
PB13
PD9
PD8
VDDA
PA3
PA7
PB1
PB0
PF14
PE7
PF10
PE12
PE15
PB 10
PB11
PB14
PB15
R
PF11
STM32F42xx/3xx
STM32F40xx/41xx
STM32F469xx
STM32F479xx
PD1
PI3
PI2
PD1
PI3
NC
PD2
PH15
PI1
PD2
VDD12
DSI
PI1
PH13
PH14
PI0
DSI
HOST_
D1P
DSI
HOST_
D1N
PI0
VSS
VCAP2
PC9
VSS
VCAP2
PC9
VSS
VDD
PC8
VSS
VDD
PC8
VSS
VDD
PG8
VSS
DSI
VDD_
USB
PG8
VDD
VDD
PG7
VDD
DSI
VDD
PG7
PH12
PG5
PG4
VCAP
DSI
PG5
PG4
DSI
HOST_ PD15
CKN
DSI
HOST_ PD14
D0N
PH11
PH10
PD15
DSI
HOST_
CKP
PH8
PH9
PD14
DSI
HOST_
D0P
MS39403V1
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
18/220
DS11118 Rev 7
STM32F479xx
1.1.4
Description
TFBGA216 package
Figure 4. TFBGA216 port-to-terminal assignment differences
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PE4
PE3
PE2
PG14
PE1
PE0
PB8
PB5
PB4
PB3
PD7
PC12
PA15
PA14
PA13
B
PE5
PE6
PG13
PB9
PB7
PB6
PG15
PG11
PJ13
PJ12
PD6
PD0
PC11
PC10
PA12
C
VBAT
PI8
PI4
PK7
PK6
PK5
PG12
PG10
PJ14
PD5
PD3
PD1
PI3
PI2
PA11
D
PC13
PF0
PI5
PI7
PI10
PI6
PK4
PK3
PG9
PJ15
PD4
PD2
PH15
PI1
PA10
E
PC14
PF1
PI12
PI9
PDR
ON
BOOT0
VDD
VDD
VDD
VDD
VCAP2
PH13
PH14
PI0
PA9
F
PC15
VSS
PI11
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PC9
PA8
G
PH0
PF2
PI13
PI15
VDD
VSS
VSS
PC8
PC7
H
PH1
PF3
PI14
PH4
VDD
VSS
VSS
PG8
PC6
J
NRST
PF4
PH5
PH3
VDD
VSS
VSS
VDD
PG7
PG6
K
PF7
PF6
PF5
PH2
VDD
VSS
VSS
VSS
VSS
VSS
VDD
PD15
PB13
PD10
L
PF10
PF9
PF8
PC3
BYPASS
-REG
VSS
VDD
VDD
VDD
VDD
VCAP1
PD14
PB12
PD9
PD8
M
VSSA
PC0
PC1
PC2
PB2
PF12
PG1
PF15
PJ4
PD12
PD13
PG3
PG2
PJ5
PH12
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
PJ3
PE8
PD11
PG5
PG4
PH7
PH9
PH11
P
VREF+
PA2
PA6
PA5
PC5
PF14
PJ2
PF11
PE9
PE11
PE14
PB10
PH6
PH8
PH10
R
VDDA
PA3
PA7
PB1
PB0
PJ0
PJ1
PE7
PE10
PE12
PE15
PE13
PB11
PB14
PB15
STM32F42xx/3xx
STM32F40xx/41xx
14
15
STM32F469xx
STM32F479xx
VDD
PK1
PL2
VDD
DSI
HOST_
D1P
DSI
HOST_
D1N
VDD
PJ11
PK0
VDDD
USB
VSS
DSI
VDD12
DSI
VDD
PJ8
PJ10
VDD
DSI
DSI
HOST_
CKP
DSI
HOST_
CKN
VDD
PJ7
PJ9
VDD
DSI
HOST_
D0P
DSI
HOST_
D0N
VDD
PJ6
PD15
VDD
VCAP
DSI
PD15
MSv39404V1
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
DS11118 Rev 7
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47
Description
STM32F479xx
Figure 5. STM32F479xx block diagram
CCM data RAM 64 KB
MPUFPU
EXT MEM CTRL (FMC)
NVIC
SRAM, PSRAM, NOR Flash
NAND Flash, SDRAM
D-BUS
USB
OTG HS
AHB BUS MATRIX
PHY
S-BUS
D+, DVDDUSB = 3.0 to 3.6 V
ULPI : CLK, D(7:0),
DIR, STP, NXT
SCL/SDA, INT, ID, VBUS
DMA/
FIFO
8 Streams
GP-DMA2
FIFO
8 Streams
GP-DMA1
Flash 1MB
Flash 1MB
SRAM2 32KB
SRAM3 128KB
AHB2
180MHz
AHB2
180
FIFO
3DES,
AES256
HASH
RNG
SRAM1 160KB
FIFO
LCD-TFT
CLK,
BK1_NCS, BK2_NCS,
D[7:0]
QuadSPI
I-BUS
HSYNC, VSYNC
PIXCK, D(13:0)
CAMERA
ITF
USB
OTG FS
PHY
ARM
Cortex M4
180 MHz
FIFO FIFO
ETM
TRACECK
TRACED(3:0)
CLK, NE[3:0], A[23:0], D[31:0],
NOE, NWEN, NBL[3:0],
SDCLKE[1:0], SDNE[1:0],
NRAS, NCAS, NADV,
NWAIT, INTR
FIFO FIFO
JTAG & SW
ACCEL/
CACHE
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
D+, D-,
VDDUSB = 3.0 to 3.6 V,
SCL, SDA, INT, ID, VBUS
MHz
AHB1 180 MHz
DMA-2D
RC LS
GPIO PORT
USART
2MBpsC
Reset
Int
PLL1,2,3
PF[15:0]
GPIO PORT
USART
2MBpsF
PG[15:0]
USART
GPIO PORT
2MBpsG
PH[15:0]
USART
GPIO PORT
2MBpsH
PI[15:0]
USART
GPIO 2MBps
PORT I
PJ[15:0]
USART
GPIO PORT
2MBpsJ
PK[7:0]
USART
GPIO PORT
2MBpsK
@VDDA @VDD
XTAL OSC
4-26MHz
RESET&
CLOCK
MANAGT
CTRL
DSI
PHI
SDIO / MMC
LS
16b
USART
TIMER 82MBps
/ PWM
1 channel as AF
TIMER10
USART 2MBps
APB1 45 MHz
16b
TIMER
USART92MBps
16b
16b
WWDG
TIMER11
USART 2MBps
1 channel as AF
smcard
RX, TX, SCK,
CTS, RTS as AF
irDA
RX, TX, SCK,
CTS, RTS as AF
smcard
USART USART
2MBps
irDA
USART USART
2MBps 1
6
SPI1/I2S
USART
2MBps
USARTSPI
2MBps
4
MOSI, MISO, SCK,
NSS as AF
USARTSPI5
2MBps
MOSI, MISO, SCK,
NSS as AF
USARTSPI6
2MBps
SD, SCK, FS
MCLK as AF
1
USARTSAI
2MBps
TIMER6
FIFO
MOSI, MISO, SCK,
NSS as AF
TIMER7
16b
V DDREF_ADC
USART
2MBps
TEMP SENSOR
ADC1
8 analog inputs common
to the ADC1 & 2
ADC2
8 analog inputs to ADC3
ADC 3
RTC_TAMP1
RTC_TAMP2
RTC_OUT
RTC_REFIN
RTC_TS
TIM2
32b
4 Channels, ETR as AF
TIM3
16b
4 Channels, ETR as AF
TIM4
16b
4 Channels, ETR as AF
TIM5
32b
4 Channels
TIM12
16b
2 Channels as AF
TIM13
16b
1 Channels as AF
TIM14
16b
1 CH as AF
smcard
USART2
irDA
RX, TX, SCK,
CTS, RTS as AF
smcard
USART3
irDA
RX, TX, SCK
CTS, RTS as AF
UART4
RX, TX as AF
UART5
RX, TX as AF
UART7
RX, TX as AF
UART8
RX, TX as AF
SPI2/I2S
MOSI, MISO, SCK
NSS/WS, MCK as AF
SPI3/I2S
MOSI, MISO, SCK
NSS/WS, MCK as AF
SCL, SDA, SMBA as AF
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
@VDDA
DAC1
IF
4KB BKPRAM
16b
@VDDA
8 analog inputs common
to the 3 ADCs
AWU
Backup Register
OSC32_IN
OSC32_OUT
AHB/APB2 AHB/APB1
16b
TIMER 12MBps
/ PWM
USART
2 channels as AF
MOSI, MISO, SCK,
NSS as AF
DMA1
APB2 90 MHz
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4]ETR),
BKIN as AF
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4]ETR),
BKIN as AF
DMA2
EXT IT.
WKUP
USART
2MBps
APB2 60M Hz
D[7:0]
CMD, CK as AF
XTAL 32kHz
RTC
DSI Host
FIFO
168 AF
VBAT = 1.8 to 3.6 V
@VBAT
CRC
DSIHOST_D0 P/N
DSIHOST_D1 P/N
DSIHOST_CK P/N
VDD12DSI, VDDSI, VSSDSI
VCAPDSI
DSIHOST_TE
OSCIN
OSCOUT
IWDG
Standbyinterface
DAC2
ITF
bxCAN1
bxCAN2
DAC1 as AF
Dig. Filter
USART
GPIO PORT
2MBpsE
VDDA, VSSA,
NRST
PVD
USART
GPIO PORT
2MBpsD
PE[15:0]
SUPPLY
SUPERVISION
POR/PDR/
BOR
DAC2 as AF
FIFO
PD[15:0]
POR
RC HS
GPIO PORT
USART
2MBpsB
LS
PC[15:0]
@VDDA
USART
GPIO PORT
2MBpsA
PCLKx
PB[15:0]
FIFO
HCLKx
PA[15:0]
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
TX, RX
TX, RX
MS38297V1
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
20/220
DS11118 Rev 7
STM32F479xx
Functional overview
2
Functional overview
2.1
Arm® Cortex®-M4 with FPU and embedded Flash and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution. Its single precision FPU (floating point unit) speeds up
software development by using metalanguage development tools, while avoiding saturation.
The STM32F47x line is compatible with all Arm® tools and software.
Figure 5 shows the general block diagram of the STM32F47x line.
Note:
Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.
2.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally require
the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
2.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes
of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS11118 Rev 7
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47
Functional overview
2.4
STM32F479xx
Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
2.5
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.6
Embedded SRAM
All devices embed:
Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.7
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
22/220
DS11118 Rev 7
STM32F479xx
Functional overview
Figure 6. STM32F479xx Multi-AHB matrix
Chrom ART
Accelerator(DMA2D)
DMA2D
LCD-TFT
LCD-TFT_M
ETHERNET_M
USB OTG
HS
USB_HS_M
MAC
Ethernet
DMA_P2
GP
DMA2
DMA_MEM2
DMA_MEM1
DMA_PI
GP
DMA1
S-bus
D-bus
ARM
Cortex-M4
I-bus
64-Kbyte
CCM data RAM
DCODE
ACCEL
ICODE
Flash
memory
SRAM1
160 Kbyte
SRAM2
32 Kbyte
SRAM3
128 Kbyte
AHB2
peripherals
AHB1
peripherals
FMC external
MemCtl
APB1
APB2
QuadSPI
Bus matrix-S
2.8
MS33862V1
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview
STM32F479xx
The DMA can be used with the main peripherals:
2.9
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1
QUADSPI.
Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
The NOR/PSRAM memory controller
The NAND/memory controller
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
24/220
DS11118 Rev 7
STM32F479xx
2.10
Functional overview
Quad-SPI memory interface (QUADSPI)
All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.11
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2.12
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
LTDC interface:
–
Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
–
Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
APB slave interface:
–
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
–
Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
Video mode pattern generator:
–
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
DS11118 Rev 7
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47
Functional overview
STM32F479xx
The DSI Host main features:
Compliant with MIPI Alliance standards
Interface with MIPI D-PHY
Supports all commands defined in the MIPI Alliance specification for DCS:
–
Transmission of all Command mode packets through the APB interface
–
Transmission of commands in low-power and high-speed during Video Mode
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
3D transmission support
Configurable selection of system interfaces:
–
AMBA APB for control and optional support for Generic and DCS commands
–
Video Mode interface through LTDC
–
Adapted Command Mode interface through LTDC
Independently programmable Virtual Channel ID in
–
Video Mode
–
Adapted Command Mode
–
APB Slave
Video Mode interfaces features
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
–
Number of lanes: 2
–
Maximum speed per lane: 500 Mbps
Adapted interface features
26/220
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
DS11118 Rev 7
STM32F479xx
Functional overview
Video mode pattern generator
2.13
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.14
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.
DS11118 Rev 7
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47
Functional overview
2.16
STM32F479xx
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.17
Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
2.18
Note:
28/220
Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3 V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
DS11118 Rev 7
STM32F479xx
Functional overview
The following conditions must be respected:
–
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
VDDUSB rising and falling time rate specifications must be respected.
–
In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
– If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs
powered by VDDUSB are not used, then VDDUSB should be tied to VSS or VDD
(VDDUSB must not be floating).
Figure 7. VDDUSB connected to an external independent power supply
VDDUSB_MAX
USB functional area
VDDUSB
VDDUSB_MIN
USB non
functional
area
VDD = VDDA
Power-on
Operating mode
USB non
functional
area
VDD_MIN
Power-down
time
MS37590V1
The DSI (Display Serial Interface) sub-system uses several power supply pins that are
independent from the other supply pins:
VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI
D-PHY. This supply must be connected to global VDD.
VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected
externally to VDD12DSI.
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.
VSSDSI pin is an isolated supply ground used for DSI sub-system.
If DSI functionality is not used at all, then:
–
VDDDSI pin must be connected to global VDD.
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–
VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
–
VSSDSI pin must be grounded.
2.19
Power supply supervisor
2.19.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On other packages the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.19.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be
connected to VSS, as shown in Figure 8.
Figure 8. Power supply supervisor interconnection with internal reset OFF
VDD
STM32F479xx
Application reset
signal (optional)
VBAT
PDR_ON
VSS
PDR not active : 1.7 V < VDD < 3.6 V
MSv36589V1
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The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages allow to disable the internal reset through the PDR_ON signal when connected
to VSS.
Figure 9. PDR_ON control with internal reset OFF
V DD
PDR = 1.7 V
time
Reset by other source than
power supply supervisor
NRST
PDR_ON
PDR_ON
time
MS19009V7
1. PDR_ON signal to be kept always low.
2.20
Voltage regulator
The regulator has four operating modes:
Regulator ON
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator OFF
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2.20.1
STM32F479xx
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
–
LPR operates in normal mode (default mode when LPR is ON)
–
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Section 2.18 and Table 125.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down mode
-
-
-
Yes
Over-drive
mode(2)
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
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2.20.2
Functional overview
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 10. Regulator OFF
V12
External VCAP_1/2 power
Application reset
supply supervisor
Ext. reset controller active signal (optional)
when VCAP_1/2 < Min V12
VDD
PA0
VDD
NRST
BYPASS_REG
V12
VCAP_1
VCAP_2
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The following conditions must be respected:
Note:
VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between
power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 must be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 can be asserted low externally (see
Figure 12).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application
(see Operating conditions).
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization
VDD
PDR = 1.7 or 1.8 V
V12
Min V12
VCAP_1, VCAP_2
time
NRST
PA0
time
1. This figure is valid whatever the internal reset mode (ON or OFF).
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Functional overview
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization
VDD
PDR = 1.7 or 1.8 V (2)
VCAP_1, VCAP_2
V12
Min V12
time
NRST
PA0
time
ai18492f
1. This figure is valid whatever the internal reset mode (ON or OFF).
2.20.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
2.21
Package
Regulator ON
Regulator OFF
WLCSP168
UFBGA169
LQFP208
Yes
No
LQFP176
UFBGA176
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
Internal reset ON
Internal reset OFF
Yes
Yes
PDR_ON set to VDD PDR_ON set to VSS
Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
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Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
2.22
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5):
–
Normal mode (default mode when MR or LPR is enabled)
–
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Table 5. Voltage regulator modes in stop mode
Voltage regulator
configuration
Main regulator (MR)
Low-power regulator (LPR)
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
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PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.23
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery neither an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.24
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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Table 6. Timer feature comparison
Timer
type
Advanced
control
General
purpose
Basic
Counter Counter Prescaler
Timer
resolution
type
factor
Max
Max
DMA
Capture/
Complementary interface timer
request
compare
output
clock
clock
generation channels
(MHz) (MHz)(1)
TIM1,
TIM8
16-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
Yes
90
180
TIM2,
TIM5
32-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
No
45
90/180
TIM3,
TIM4
16-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
No
45
90/180
TIM9
16-bit
Up
Any integer
between 1
and 65536
No
2
No
90
180
TIM10
,
TIM11
16-bit
Up
Any integer
between 1
and 65536
No
1
No
90
180
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
No
45
90/180
TIM13
,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
45
90/180
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
45
90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the
RCC_DCKCFGR register.
2.24.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
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2.24.2
Functional overview
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F47x devices
(see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F47x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit autoreload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.24.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.24.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.24.5
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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2.24.6
STM32F479xx
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
2.25
a 24-bit downcounter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source.
Inter-integrated circuit interface (I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
The I²C bus interfaces can be served by DMA and support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
Table 7. Comparison of I2C analog and digital filters
Filter
Analog
Digital
Pulse width of suppressed spikes
50 ns
Programmable length, from one to fifteen I2C peripheral clocks
2.26
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
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Table 8. USART feature comparison(1)
Max. baud rate in Mbit/s
Name
SPI
Smartcard
Standard
Modem
LIN
irDA
features (RTS/CTS)
master
(ISO 7816)
APB
Oversampling Oversampling mapping
by 16
by 8
USART1
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
USART2
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
USART3
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
UART4
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
UART5
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
USART6
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
UART7
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
UART8
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
1. X = feature supported.
2.27
Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
2.28
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
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Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note:
For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
2.29
Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
2.30
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
2.31
Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
2.32
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
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The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.33
Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
2.34
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
DS11118 Rev 7
43/220
47
Functional overview
2.35
STM32F479xx
Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
12 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.36
Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
44/220
Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
DS11118 Rev 7
STM32F479xx
2.37
Functional overview
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
2.38
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image black & white.
Cryptographic accelerator
The devices embed a cryptographic accelerator. This cryptographic accelerator provides a
set of hardware acceleration for the advanced cryptographic algorithms usually needed to
provide confidentiality, authentication, data integrity and non repudiation when exchanging
messages with a peer.
These algorithms consists of:
Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64,128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal hash
–
SHA-1 and SHA-2 (secure hash algorithms)
–
MD5
–
HMAC
The cryptographic accelerator supports DMA request generation.
2.39
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
2.40
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
DS11118 Rev 7
45/220
47
Functional overview
STM32F479xx
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
2.41
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.42
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.43
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
46/220
DS11118 Rev 7
STM32F479xx
Functional overview
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.44
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.45
Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F47x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS11118 Rev 7
47/220
47
Pinouts and pin description
3
STM32F479xx
Pinouts and pin description
VDD
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VSS
VDD
VCAP2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 13. STM32F47x LQFP100 pinout
PE2
1
75
PA13
VSS
2
74
PA12
VBAT
3
73
PA11
PC13
4
72
PA10
PC14
5
71
PA9
PC15
6
70
PA8
VSS
7
69
PC9
VDD
8
68
PC8
PH0
9
67
PC7
PH1
10
66
PC6
NRST
11
65
VDDUSB
PC0
12
64
DSIHOST_D1N
PC1
13
63
DSIHOST_D1P
PC2
14
62
VDD12DSI
PC3
15
61
DSIHOST_CKN
VSSA
16
60
DSIHOST_CKP
VREF+
17
59
VSSDSI
VDDA
18
58
DSIHOST_D0N
PA0
19
57
DSIHOST_D0P
PA1
20
56
VCAPDSI
PA2
21
55
VDDDSI
PA3
22
54
PD15
VSS
23
53
PD14
VDD
24
52
PD10
PA4
25
51
PD9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA5
PA6
PA7
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP1
VSS
VDD
PB12
PB13
PB14
PB15
PD8
LQFP100
1. The above figure shows the package top view.
48/220
DS11118 Rev 7
MS40560V1
STM32F479xx
Pinouts and pin description
PE2
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG12
PG11
PG10
PG9
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Figure 14. STM32F47x LQFP144 pinout
PE3
PE4
PE5
PE6
1
2
3
4
108
VCAP2
107
PA13
106
PA12
105
PA11
VBAT
5
104
PA10
PC13
6
103
PA9
PC14
7
PC15
8
102
101
PA8
PC9
PF0
9
100
PC8
PF1
10
99
PC7
PF2
11
PF3
12
98
97
PC6
VDDUSB
PF4
13
96
PG8
PF5
14
95
PG7
VSS
15
94
PG6
VDD
16
93
PG5
PF10
17
92
PG4
PH0
18
91
PG3
PH1
19
90
PG2
NRST
20
89
DSIHOST_D1N
PC0
21
88
DSIHOST_D1P
PC1
22
87
VDD12DSI
PC2
23
86
DSIHOST_CKN
PC3
24
85
DSIHOST_CKP
VDD
25
84
VSSDSI
VSSA
26
83
DSIHOST_D0N
VREF+
27
82
DSIHOST_D0P
VDDA
28
81
VCAPDSI
PA0
29
80
VDDDSI
PA1
30
79
PD15
PA2
31
78
PD14
PA3
32
77
VDD
VSS
33
76
VSS
VDD
34
75
PD12
PA4
35
74
PD11
PA5
36
73
PD10
70
71
72
62
63
PE15
PB10
PD8
PD9
48
49
50
51
52
53
54
55
56
57
58
59
60
61
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
69
47
PF13
PB15
46
VDD
68
45
PF12
PB14
44
PF11
67
43
PB2
PB13
42
PB1
PB12
41
PB0
65
66
40
PC5
64
39
PC4
PB11
38
PA7
VCAP1
VDD
37
PA6
LQFP144
MS40561V2
1. The above figure shows the package top view.
DS11118 Rev 7
49/220
83
Pinouts and pin description
STM32F479xx
Figure 15. STM32F47x WLCSP168 pinout
12
11
10
9
8
7
6
5
4
3
2
1
A
PI7
VDD
PE0
PB7
PB3
VDD
PG12
PD7
VSS
PD1
PA15
PI2
B
PE5
PI6
VSS
PB8
PB5
VSS
PG11
VDD
PD4
PC11
PI3
PH13
C
VBAT
PE4
PI5
PE1
PB4
PG10
PD5
PD2
PC12
PI1
VDD
VSS
D
PC13
PE6
PI4
PDR_
ON
PG15
PG9
PD3
PC10
PA14
PH14
VCAP2
PA13
E
PC15
PC14
PE3
PB9
PG13
PD6
PD0
PI0
PH15
PA10
PA9
PA8
F
VSS
PI11
PI10
PE2
BOOT0
PA11
PA12
PC9
PC8
PC6
VSS
VDD
USB
G
PF2
VDD
PF0
PI9
PB6
PC7
PG8
PG2
PG3
PG6
PG4
PG5
H
PF5
PF3
PF1
NRST
PF15
VSS
PG7
PB12
PD13
DSI
HOST
_D1P
DSI
HOST
_D1N
VSS
DSI
J
VDD
VSS
PF4
PC0
PA7
PF13
PG0
PE14
PD11
DSI
HOST
_D0N
DSI
HOST
_CKN
DSI
HOST
_CKP
K
PH1
PH0
PF10
PA1
PH5
PF11
PE9
PB11
PB13
DSI
HOST
_D0P
VDD12
DSI
VCAP
DSI
L
PC1
VSSA
PA0
PA2
PA5
PF14
PE13
PH9
PD8
PD14
PD15
VDD
DSI
M
VDDA
PH2
PH4
PA4
PF12
PE8
PE12
PH8
PH10
PD10
PD12
VSS
N
PH3
VSS
PA3
PB1
VSS
PE7
PE11
PB10
VCAP1
PH11
PB15
PD9
P
VDD
PA6
PB0
PB2
VDD
PG1
PE10
PE15
VSS
VDD
PH12
PB14
MSv35729V2
1. The above figure shows the package bottom view.
50/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Figure 16. STM32F47x UFBGA169 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PI6
PI5
PE1
PE0
BOOT0
PG13
PG12
PD7
PC12
PA14
PA13
PA12
PA11
B
PI7
PE2
PI4
PB7
PB3
PG11
PD5
PD2
PC11
PAI3
PA15
PI2
PI0
C
PE3
PE4
PDR_
ON
PB9
PB6
PD4
PD1
PD3
PD0
PC10
PI1
PH15
PH14
D
PE5
PE6
VDD
PB8
PB5
PB4
PD6
PA8
PH13
VDD
VSS
VCAP2
PG8
E
PC14
PI9
VSS
PI10
VBAT
PG9
PG10
PA9
PA10
PC8
PG7
PG5
PG4
F
PC15
PI11
PF0
VDD
VSS
PG15
VDD
VSS
PC6
PC7
PG6
PG3
PG2
G
PH1
PH0
PF1
PC13
PF2
PE8
VSS
VDD
VSS
PC9
VDD
USB
DSI
HOST_
D1P
DSI
HOST_
D1N
H
PF10
NRST
PF5
PF3
PF14
PE9
PE10
PH8
PH9
PH12
VSSDSI
DSI
HOST_
CKP
DSI_
HOST
CKN
J
VSS
VSSA
VDDA
VDD
PA0
VSS
VSS
PE13
PH10
VSS
VDD12
DSI
DSI
HOST_
D0P
DSI
HOST_
D0N
K
PA1
PA2
PA3
PA7
PB1
VDD
PE11
PE14
PH11
VDD
VSSDSI
VCAP
DSI
VDD
DSI
L
PH3
PH2
PH5
PF4
PB2
VDD
PE12
PE15
VDD
PD8
PD10
PD14
PD15
M
PC0
PH4
PA5
PF13
PF11
PF15
PG1
PB10
VSS
PD9
PD11
PD13
PD12
N
PC1
PA4
PA6
PB0
PF12
PG0
PE7
PB11
VCAP1
PB12
PB13
PB14
PB15
MSv35730V2
1. The above figure shows the package top view.
DS11118 Rev 7
51/220
83
Pinouts and pin description
STM32F479xx
Figure 17. STM32F47x UFBGA176 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
PE3
PE2
PE 1
PE0
PB8
PB5
PG 14
PG 13
PB 4
PB3
PD7
PC12
PA15
PA14
P A 13
B
PE4
PE5
PE6
PB9
PB7
PB6
PG 15
PG 12
PG 11
PG 10
PD6
PD0
PC11
PC10
PA12
C
VBAT
P I7
P I6
P I5
VDD
PDR
_ON
VDD
VDD
VDD
PG9
PD5
PD1
P I3
NC
PA11
D
P C 13
PI8
P I9
P I4
VSS
BOOT0
VSS
VSS
VSS
PD4
PD 3
PD2
VDD12
DSI
PI1
PA10
E
P C 14
PF0
PI10
P I1 1
DSI
HOST_
D1P
DSI
HOST_
D1N
P I0
PA 9
F
P C 15
VSS
VDD
PH2
VSS
VSS
VSS
VSS
VSS
V SS
VCAP2
PC9
PA 8
G
PH0
VS S
V DD
PH3
VSS
VSS
VSS
VSS
VSS
V SS
VDD
PC8
PC7
H
PH1
PF2
PF1
PH4
VSS
VSS
VSS
VSS
VSS
VSS
DSI
VDD_
USB
PG8
PC6
J
NRST
PF3
P F4
PH5
VSS
VSS
VSS
VSS
VSS
VDD
DSI
VDD
PG7
PG6
K
PF7
PF6
PF5
V DD
VSS
VSS
VSS
VSS
VSS
VCAP
DSI
PG5
PG4
PG3
PF10
PF9
PF8
BYPASS
_REG
DSI
HOST_
CKP
DSI
HOST_
CKN
PD15
M
VSSA
PC0
PC1
PC2
PC3
PB2
PG1
VSS
VSS
VCAP
_1
PH6
DSI
HOST_
D0P
DSI
HOST_
D0N
PD14
PD13
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
V DD
V DD
V DD
PE13
PH7
PD12
PD11
P D 10
VREF+
PA2
PA6
PA5
PC5
PF12
PF15
PE 8
PE 9
P E 11
PE14
PB 1 2
PB13
PD9
PD8
VDDA
PA3
PA7
PB1
PB0
PF11
PF14
PE7
PE10
PE12
PE15
PB10
PB11
P B 14
P B 15
L
P
R
PG2
MS39400V2
1. The above figure shows the package top view.
52/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI1
Figure 18. STM32F47x LQFP176 pinout
LQFP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PI0
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDUSB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
VSSDSI
DSIHOST_D1N
DSIHOST_D1P
VDD12DSI
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDDSI
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PH4
PH5
PA3
BYPASS_REG
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP_1
VDD
PH6
PH7
PB12
PB13
PB14
PB15
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
PH3
MS33870V4
1. The above figure shows the package top view.
DS11118 Rev 7
53/220
83
Pinouts and pin description
STM32F479xx
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PI7
PI6
PI5
PI4
VDD
PDR_ON
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
PK7
PK6
PK5
PK4
PK3
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PJ15
PJ14
PJ13
PJ12
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
PI3
Figure 19. STM32F47x LQFP208 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
LQFP208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PI2
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDDUSB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
VSSDSI
DSIHOST_D1N
DSIHOST_D1P
VDD12DSI
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDDSI
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PA4
PA5
PA6
PA7
PC4
PC5
VDD
VSS
PB0
PB1
PB2
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP1
VSS
VDD
PJ5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
VDD
PB12
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PI12
PI13
PI14
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
PH3
PH4
PH5
PA3
VSS
VDD
MSv33876V5
1. The above figure shows the package top view.
54/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Figure 20. STM32F47x TFBGA216 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PE4
PE3
PE2
PG14
PE1
PE0
PB8
PB5
PB4
PB3
PD7
PC12
PA15
PA14
PA13
B
PE5
PE6
PG13
PB9
PB7
PB6
PG15
PG11
PJ13
PJ12
PD6
PD0
PC11
PC10
PA12
C
VBAT
PI8
PI4
PK7
PK6
PK5
PG12
PG10
PJ14
PD5
PD3
PD1
PI3
PI2
PA11
D
PC13
PF0
PI5
PI7
PI10
PI6
PK4
PK3
PG9
PJ15
PD4
PD2
PH15
PI1
PA10
E
PC14
PF1
PI12
PI9
PDR
ON
BOOT0
VDD
VDD
VDD
VDD
VCAP2
PH13
PH14
PI0
PA9
F
PC15
VSS
PI11
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VDD
DSI
HOST_
D1P
DSI
HOST_
D1N
PC9
PA8
G
PH0
PF2
PI15
VDD
VSS
VSS
VDDD
USB
VSS
DSI
VDD12
DSI
PC8
PC7
H
PH1
PF3
PI14
PH4
VDD
VSS
VSS
VDD
DSI
DSI
HOST_
CKP
DSI
HOST_
CKN
PG8
PC6
J
NRST
PF4
PH5
PH3
VDD
VSS
VSS
VDD
DSI
HOST_
D0P
DSI
HOST_
D0N
PG7
PG6
K
PF7
PF6
PF5
PH2
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VCAP
DSI
PD15
PB13
PD10
L
PF10
PF9
PF8
PC3
BYPASSREG
VSS
VDD
VDD
VDD
VDD
VCAP1
PD14
PB12
PD9
PD8
M
VSSA
PC0
PC1
PC2
PB2
PF12
PG1
PF15
PJ4
PD12
PD13
PG3
PG2
PJ5
PH12
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
PJ3
PE8
PD11
PG5
PG4
PH7
PH9
PH11
P
VREF+
PA2
PA6
PA5
PC5
PF14
PJ2
PF11
PE9
PE11
PE14
PB10
PH6
PH8
PH10
R
VDDA
PA3
PA7
PB1
PB0
PJ0
PJ1
PE7
PE10
PE12
PE15
PE13
PB11
PB14
PB15
PI13
14
15
MSv33871V4
1. The above figure shows the package top view.
DS11118 Rev 7
55/220
83
Pinouts and pin description
STM32F479xx
Table 9. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Notes
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TTa
3.3 V tolerant I/O directly connected to analog parts
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
56/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
(2)
NC
(2)
NC
(2)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
B2
F9
A2
1
1
A3
PE2
I/O
FT
-
1
C1
E10
A1
2
2
A2
PE3
I/O
FT
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
-
-
LQFP208
144
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
LQFP176
Notes
NC
Alternate functions
LQFP144
LQFP100
1
Pin name
(function after
reset)(1)
I/O structures
Table 10. STM32F479xx pin and ball definitions
Pin number
Additional
functions
-
2
C2
C11
B1
3
3
A1
PE4
I/O
FT
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
3
D1
B12
B2
4
4
B1
PE5
I/O
FT
-
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
-
(2)
4
D2
D11
B3
5
5
B2
PE6
I/O
FT
-
TRACED3, TIM9_CH2,
SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
2
-
-
-
-
-
-
G6
VSS
S
-
-
-
-
-
-
-
-
-
-
-
F5
VDD
S
-
-
-
-
3
5
E5
C12
C1
6
6
C1
VBAT
S
-
-
-
-
-
-
-
-
D2
7
7
C2
PI8
I/O
FT
EVENTOUT
RTC_TAMP1/
RTC_TAMP2/
RTC_TS
4
6
G4
D12
D1
8
8
D1
PC13
I/O
FT
EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT
5
7
E1
E11
E1
9
9
E1
PC14-OSC32_IN
(PC14)
I/O
FT
EVENTOUT
OSC32_IN
6
8
F1
E12
F1
10
10
F1
PC15OSC32_OUT
(PC15)
I/O
FT
(4)
EVENTOUT
OSC32_OUT
-
-
-
-
-
-
-
G5
VDD
S
-
-
-
-
-
-
E2
G9
D3
11
11
E4
PI9
I/O
FT
CAN1_RX, FMC_D30,
LCD_VSYNC, EVENTOUT
-
-
-
E4
F10
E3
12
12
D5
PI10
I/O
FT
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
-
-
F2
F11
E4
13
13
F3
PI11
I/O
FT
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
-
-
-
F5
F12
F2
14
14
F2
VSS
S
-
-
-
-
-
-
F4
G11
F3
15
15
F4
VDD
S
-
-
-
-
NC
DS11118 Rev 7
(3)
(4)
(3)
(4)
(3)
(4)
(3)
57/220
83
Pinouts and pin description
STM32F479xx
Table 10. STM32F479xx pin and ball definitions (continued)
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
-
9
F3
G10
E2
16
16
D2
PF0
I/O
FT
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
10
G3
H10
H3
17
17
E2
PF1
I/O
FT
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
11
G5
G12
H2
18
18
G2
PF2
I/O
FT
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
-
-
19
E3
PI12
I/O
FT
LCD_HSYNC, EVENTOUT
-
-
-
-
-
-
-
20
G3
PI13
I/O
FT
LCD_VSYNC, EVENTOUT
-
-
-
-
-
-
-
21
H3
PI14
I/O
FT
-
12
13
H4
L4
H11
J10
J2
J3
19
20
22
23
H2
J2
PF3
PF4
I/O
I/O
Notes
LQFP100
Pin number
Alternate functions
Additional
functions
LCD_CLK, EVENTOUT
-
FT
(5)
FMC_A3, EVENTOUT
ADC3_IN9
FT
(5)
FMC_A4, EVENTOUT
ADC3_IN14
FMC_A5, EVENTOUT
ADC3_IN15
-
14
H3
H12
K3
21
24
K3
PF5
I/O
FT
(5)
7
15
G7
J11
G2
22
25
H6
VSS
S
-
-
-
-
8
16
G8
J12
G3
23
26
H5
VDD
S
-
-
-
-
-
-
-
-
K2
24
27
K2
PF6
I/O
FT
(5)
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
-
-
-
-
K1
25
28
K1
PF7
I/O
FT
(5)
-
-
-
-
L3
26
29
L3
PF8
I/O
FT
(5)
SPI5_MISO, SAI1_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
SPI5_MOSI, SAI1_FS_B,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
-
-
-
-
L2
27
30
L2
PF9
I/O
FT
(5)
-
17
H1
K10
L1
28
31
L1
PF10
I/O
FT
(5)
QUADSPI_CLK,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
9
18
G2
K11
G1
29
32
G1
PH0-OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
10
19
G1
K12
H1
30
33
H1
PH1-OSC_OUT
(PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
11
20
H2
H9
J1
31
34
J1
NRST
I/O
RST
-
12
21
M1
J9
M2
32
35
M2
PC0
I/O
FT
(5)
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
IN10
58/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Table 10. STM32F479xx pin and ball definitions (continued)
Notes
M3
PC1
I/O
FT
14
23
-
-
M4
34
37
M4
PC2
I/O
FT
(5)
SPI2_MISO, I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
ADC123_
IN12
ADC123_
IN13
Pin name
(function after
reset)(1)
Pin types
36
TFBGA216
33
LQFP208
M3
LQFP176
L12
UFBGA176
N1
WLCSP168
22
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, ETH_MDC,
EVENTOUT
UFBGA169
13
(5)
LQFP144
Alternate functions
LQFP100
I/O structures
Pin number
Additional
functions
ADC123_
IN11
15
24
-
-
M5
35
38
L4
PC3
I/O
FT
(5)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
-
25
-
-
-
36
39
J5
VDD
S
-
-
-
-
-
-
-
-
-
-
-
J6
VSS
S
-
-
-
-
16
26
J2
L11
M1
37
40
M1
VSSA
S
-
-
-
-
-
-
-
-
N1
-
-
N1
VREF-
S
-
-
-
-
17
27
-
-
P1
38
41
P1
VREF+
S
-
-
-
-
18
28
J3
M12
R1
39
42
R1
VDDA
S
-
-
-
-
(6)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP
ADC123_IN1
19
29
J5
L10
N3
40
43
N3
PA0-WKUP(PA0)
I/O
FT
20
30
K1
K9
N2
41
44
N2
PA1
I/O
FT
(5)
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
ETH_MII_RX_CLK/ETH_R
MII_REF_CLK, LCD_R2,
EVENTOUT
21
31
K2
L9
P2
42
45
P2
PA2
I/O
FT
(5)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2
-
-
-
L2
M11
F4
43
46
K4
PH2
I/O
FT
-
QUADSPI_BK2_IO0,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
-
L1
N12
G4
44
47
J4
PH3
I/O
FT
-
QUADSPI_BK2_IO1,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
-
-
M2
M10
H4
45
48
H4
PH4
I/O
FT
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
-
DS11118 Rev 7
59/220
83
Pinouts and pin description
STM32F479xx
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
-
-
L3
K8
J4
46
49
J3
PH5
I/O
Notes
LQFP144
Pin name
(function after
reset)(1)
Pin types
LQFP100
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
Alternate functions
Additional
functions
FT
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
-
ADC123_IN3
22
32
K3
N10
R2
47
50
R2
PA3
I/O
FT
(5)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
23
33
J1
N11
-
-
51
K6
VSS
S
-
-
-
-
-
-
-
-
L4
48
-
L5
BYPASS_REG
I
FT
-
-
-
24
34
J4
P12
K4
49
52
K5
VDD
S
-
-
-
-
ADC12_IN4,
DAC_OUT1
25
35
N2
M9
N4
50
53
N4
PA4
I/O
TTa
-
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
26
36
M3
L8
P4
51
54
P4
PA5
I/O
TTa
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_IN5,
DAC_OUT2
(5)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_IN6
ADC12_IN7
27
37
N3
P11
P3
52
55
P3
PA6
I/O
FT
38
K4
J8
R3
53
56
R3
PA7
I/O
FT
(5)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
TIM14_CH1,
QUADSPI_CLK,
ETH_MII_RX_DV/ETH_RMI
I_CRS_DV, FMC_SDNWE,
EVENTOUT
39
-
-
N5
54
57
N5
PC4
I/O
FT
(5)
ETH_MII_RXD0/ETH_RMII
_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
(2)
40
-
-
P5
55
58
P5
PC5
I/O
FT
(5)
ETH_MII_RXD1/ETH_RMII
_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
-
-
-
-
-
-
59
L7
VDD
S
-
-
-
-
-
-
-
-
-
-
60
L6
VSS
S
-
-
-
-
(5)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_IN8
28
NC
(2)
NC
29
41
60/220
N4
P10
R5
56
61
R5
PB0
I/O
DS11118 Rev 7
FT
STM32F479xx
Pinouts and pin description
K5
N9
R4
57
62
R4
PB1
I/O
FT
(5)
31
43
L5
P9
M6
58
63
M5
PB2BOOT1(PB2)
I/O
FT
-
EVENTOUT
-
-
-
-
-
-
-
64
G4
PI15
I/O
FT
-
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
-
-
-
65
R6
PJ0
I/O
FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
-
-
66
R7
PJ1
I/O
FT
-
LCD_R2, EVENTOUT
-
-
-
-
-
-
-
67
P7
PJ2
I/O
FT
-
DSIHOST_TE, LCD_R3,
EVENTOUT
-
-
-
-
-
-
-
68
N8
PJ3
I/O
FT
-
LCD_R4, EVENTOUT
-
-
-
-
-
-
-
69
M9
PJ4
I/O
FT
-
LCD_R5, EVENTOUT
-
-
44
M5
K7
R6
59
70
P8
PF11
I/O
FT
-
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
-
45
N5
M8
P6
60
71
M6
PF12
I/O
FT
-
FMC_A6, EVENTOUT
-
-
-
J6
N8
M8
61
72
K7
VSS
S
-
-
-
-
-
46
K6
P8
N8
62
73
L8
VDD
S
-
-
-
-
-
47
M4
J7
N6
63
74
N6
PF13
I/O
FT
-
FMC_A7, EVENTOUT
-
-
48
H5
L7
R7
64
75
P6
PF14
I/O
FT
-
FMC_A8, EVENTOUT
-
-
49
M6
H8
P7
65
76
M8
PF15
I/O
FT
-
FMC_A9, EVENTOUT
-
-
50
N6
J6
N7
66
77
N7
PG0
I/O
FT
-
FMC_A10, EVENTOUT
-
-
51
M7
P7
M7
67
78
M7
PG1
I/O
FT
-
FMC_A11, EVENTOUT
-
32
52
N7
N7
R8
68
79
R8
PE7
I/O
FT
-
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
33
53
G6
M7
P8
69
80
N9
PE8
I/O
FT
-
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
34
54
H6
K6
P9
70
81
P9
PE9
I/O
FT
-
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
-
55
J7
-
M9
71
82
K8
VSS
S
-
-
-
-
-
56
L6
-
N9
72
83
L9
VDD
S
-
-
-
-
35
57
H7
P6
R9
73
84
R9
PE10
I/O
FT
-
TIM1_CH2N,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
LQFP208
42
LQFP176
30
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
DS11118 Rev 7
Additional
functions
ADC12_IN9
61/220
83
Pinouts and pin description
STM32F479xx
Table 10. STM32F479xx pin and ball definitions (continued)
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Pin number
Alternate functions
36
58
K7
N6
P10
74
85
P10
PE11
I/O
FT
-
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
-
37
59
L7
M6
R10
75
86
R10
PE12
I/O
FT
-
TIM1_CH3N, SPI4_SCK,
FMC_D9, LCD_B4,
EVENTOUT
-
38
60
J8
L6
N11
76
87
R12
PE13
I/O
FT
-
TIM1_CH3, SPI4_MISO,
FMC_D10, LCD_DE,
EVENTOUT
-
39
61
K8
J5
P11
77
88
P11
PE14
I/O
FT
-
TIM1_CH4, SPI4_MOSI,
FMC_D11, LCD_CLK,
EVENTOUT
-
40
62
L8
P5
R11
78
89
R11
PE15
I/O
FT
-
TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT
-
-
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
-
-
41
63
M8
N5
R12
79
90
P12
PB10
I/O
FT
Additional
functions
42
64
N8
K5
R13
80
91
R13
PB11
I/O
FT
-
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DSIHOST_TE,
LCD_G5, EVENTOUT
43
65
N9
N4
M10
81
92
L11
VCAP1
S
-
-
-
-
44
-
M9
P4
-
-
93
K9
VSS
S
-
-
-
-
45
66
L9
P3
N10
82
94
L10
VDD
S
-
-
-
-
-
-
-
-
-
-
95
M14
PJ5
I/O
FT
-
LCD_R6, EVENTOUT
-
-
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
-
-
-
-
M11
83
96
P13
PH6
I/O
FT
-
-
-
-
N12
84
97
N13
PH7
I/O
FT
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1, DCMI_D9,
EVENTOUT
-
-
H8
M5
-
-
98
P14
PH8
I/O
FT
-
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
-
-
H9
L5
-
-
99
N14
PH9
I/O
FT
-
I2C3_SMBA, TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
62/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Table 10. STM32F479xx pin and ball definitions (continued)
UFBGA169
WLCSP168
UFBGA176
LQFP176
Pin types
I/O structures
Notes
-
-
J9
M4
-
-
100 P15
PH10
I/O
FT
-
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
-
-
K9
N3
-
-
101 N15
PH11
I/O
FT
-
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
-
-
-
H10
P2
-
-
102 M15
PH12
I/O
FT
-
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
-
-
-
H7
-
-
-
K10
VSS
S
-
-
-
-
-
66
-
-
-
-
103
K11
VDD
S
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII
_TXD0, OTG_HS_ID,
EVENTOUT
-
-
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII
_TXD1, EVENTOUT
OTG_HS_
VBUS
-
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, I2S2ext_SD,
USART3_RTS,
TIM12_CH1, OTG_HS_DM,
EVENTOUT
-
-
46
47
48
67
68
69
N10
N11
N12
H5
K4
P1
P12
P13
R14
85
86
87
104
TFBGA216
LQFP144
Alternate functions
LQFP208
LQFP100
Pin number
L13
105 K14
106 R14
Pin name
(function after
reset)(1)
PB12
PB13
PB14
I/O
I/O
I/O
FT
FT
FT
Additional
functions
49
70
N13
N2
R15
88
107 R15
PB15
I/O
FT
-
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2, OTG_HS_DP,
EVENTOUT
50
71
L10
L4
P15
89
108
L15
PD8
I/O
FT
-
USART3_TX, FMC_D13,
EVENTOUT
-
51
72
M10
N1
P14
90
109
L14
PD9
I/O
FT
-
USART3_RX, FMC_D14,
EVENTOUT
-
52
73
L11
M3
N15
91
110
K15
PD10
I/O
FT
-
USART3_CK, FMC_D15,
LCD_B3, EVENTOUT
-
-
USART3_CTS,
QUADSPI_BK1_IO0,
FMC_A16/FMC_CLE,
EVENTOUT
-
-
74
M11
J4
N14
92
111
N10
PD11
I/O
DS11118 Rev 7
FT
63/220
83
Pinouts and pin description
STM32F479xx
M13
M2
N13
93
112 M10
PD12
I/O
FT
-
-
-
M12
H4
M15
94
113 M11
PD13
I/O
FT
-
TIM4_CH2,
QUADSPI_BK1_IO3,
FMC_A18, EVENTOUT
-
-
76
J10
M1
-
95
114
J10
VSS
S
-
-
-
-
-
77
K10
-
J13
96
115
J11
VDD
S
-
-
-
-
53
78
L12
L3
M14
97
116
L12
PD14
I/O
FT
-
TIM4_CH3, FMC_D0,
EVENTOUT
-
54
79
L13
L2
L14
98
117
K13
PD15
I/O
FT
-
TIM4_CH4, FMC_D1,
EVENTOUT
-
55
80
K13
L1
J12
99
118
H11
VDDDSI
S
-
-
-
-
-
-
-
-
-
-
-
H10
VSS
S
-
-
-
-
56
81
K12
K1
K12 100
119
K12
VCAPDSI
S
-
-
-
-
-
-
-
K2
D13
-
G13
VDD12DSI
S
-
-
-
-
57
82
J12
K3
M12 101 120
J12
DSIHOST_D0P
I/O
-
-
-
-
58
83
J13
J3
M13 102 121
J13
DSIHOST_D0N
I/O
-
-
-
-
59
84
K11
H1
H12 103 122 G12
VSSDSI
S
-
-
-
-
60
85
H12
J1
L12
104 123 H12
DSIHOST_CKP
I/O
-
-
-
-
61
86
H13
J2
L13
105 124 H13
DSIHOST_CKN
I/O
-
-
-
-
62
87
J11
-
D13 106 125
-
VDD12DSI
S
-
-
-
-
63
88
G12
H3
E12 107 126
F12
DSIHOST_D1P
I/O
-
-
-
-
64
89
G13
H2
E13 108 127
F13
DSIHOST_D1N
I/O
-
-
-
-
-
-
H11
-
H12 109 128
-
VSSDSI
S
-
-
-
-
-
90
F13
G5
L15
110
129 M13
PG2
I/O
FT
-
FMC_A12, EVENTOUT
-
-
91
F12
G4
K15
111
130 M12
PG3
I/O
FT
-
FMC_A13, EVENTOUT
-
-
92
E13
G2
K14
112
131 N12
PG4
I/O
FT
-
FMC_A14/FMC_BA0,
EVENTOUT
-
-
93
E12
G1
K13
113
132 N11
PG5
I/O
FT
-
FMC_A15/FMC_BA1,
EVENTOUT
-
-
94
F11
G3
J15
114
133
PG6
I/O
FT
-
DCMI_D12, LCD_R7,
EVENTOUT
-
-
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
95
64/220
E11
H6
J14
-
115
LQFP208
75
LQFP176
-
TIM4_CH1, USART3_RTS,
QUADSPI_BK1_IO1,
FMC_A17/FMC_ALE,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
134
J15
J14
PG7
I/O
DS11118 Rev 7
FT
Additional
functions
-
STM32F479xx
Pinouts and pin description
D13
G6
H14
116
135 H14
PG8
I/O
FT
-
-
-
G9
F2
G12 117
136 G10
VSS
S
-
-
-
-
65
97
G11
F1
H13
118
137 G11
VDDUSB
S
-
-
-
-
66
98
F9
F3
H15
119
138 H15
PC6
I/O
FT
-
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC, EVENTOUT
-
-
LQFP208
96
LQFP176
-
SPI6_NSS, USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
Additional
functions
-
67
99
F10
G7
G15 120 139 G15
PC7
I/O
FT
-
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
68
100 E10
F4
G14 121 140 G14
PC8
I/O
FT
-
TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
-
-
69
101 G10
F5
F14
122 141
F14
PC9
I/O
FT
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN,
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
70
102
E1
F15
123 142
F15
PA8
I/O
FT
-
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
OTG_FS_SOF, LCD_R6,
EVENTOUT
-
OTG_FS_
VBUS
D8
71
103
E8
E2
E15 124 143 E15
PA9
I/O
FT
-
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
EVENTOUT
72
104
E9
E3
D15 125 144 D15
PA10
I/O
FT
-
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
-
73
105 A13
F7
C15 126 145 C15
PA11
I/O
FT
-
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
-
74
106 A12
F6
B15 127 146 B15
PA12
I/O
FT
-
TIM1_ETR, USART1_RTS,
CAN1_TX, OTG_FS_DP,
LCD_R5, EVENTOUT
-
75
107
A11
D1
A15 128 147 A15
PA13(JTMSSWDIO)
I/O
FT
-
JTMS-SWDIO, EVENTOUT
-
76
108 D12
D2
F13
129 148
E11
VCAP2
S
-
-
-
-
-
109 D11
C1
F12
130 149
F10
VSS
S
-
-
-
-
DS11118 Rev 7
65/220
83
Pinouts and pin description
STM32F479xx
F11
VDD
S
Notes
Pin name
(function after
reset)(1)
Pin types
LQFP208
G13 131 150
TFBGA216
C2
LQFP176
110 D10
UFBGA176
LQFP144
77
WLCSP168
LQFP100
UFBGA169
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
Alternate functions
Additional
functions
-
-
-
-
-
-
D9
B1
-
-
151 E12
PH13
I/O
FT
-
TIM8_CH1N, CAN1_TX,
FMC_D21, LCD_G2,
EVENTOUT
-
-
-
C13
D3
-
-
152 E13
PH14
I/O
FT
-
TIM8_CH2N, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
-
-
C12
E4
-
-
153 D13
PH15
I/O
FT
-
TIM8_CH3N, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
-
-
-
B13
E5
E14 132 154 E14
PI0
I/O
FT
-
TIM5_CH4,
SPI2_NSS/I2S2_WS(7),
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
-
C11
C3
D14 133 155 D14
PI1
I/O
FT
-
SPI2_SCK/I2S2_CK(7),
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
-
-
B12
A1
PI2
I/O
FT
-
TIM8_CH4, SPI2_MISO,
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
-
-
PI3
I/O
FT
-
-
D9
135
F9
VSS
S
-
-
-
-
-
B5
C9
136 158 E10
VDD
S
-
-
-
-
A10
D4
A14 137 159 A14
PA14(JTCKSWCLK)
I/O
FT
-
JTCK-SWCLK, EVENTOUT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
-
-
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
I2S3ext_SD, SPI3_MISO,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
-
B10
B2
78
-
-
-
-
79
111
81
82
B11
113 C10
114
66/220
(2)
156 C14
C13 134 157 C13
-
112
NC
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
80
-
B9
A2
D5
B3
-
A13 138 160 A13
B14 139 161 B14
B13 140 162 B13
PA15(JTDI)
PC10
PC11
I/O
I/O
I/O
DS11118 Rev 7
FT
FT
FT
STM32F479xx
Pinouts and pin description
A9
C4
A12 141 163 A12
PC12
I/O
FT
-
84
116
C9
E6
B12 142 164 B12
PD0
I/O
FT
-
CAN1_RX, FMC_D2,
EVENTOUT
-
85
117
C7
A3
C12 143 165 C12
PD1
I/O
FT
-
CAN1_TX, FMC_D3,
EVENTOUT
-
86
118
B8
C5
D12 144 166 D12
PD2
I/O
FT
-
TRACED2, TIM3_ETR,
UART5_RX, SDIO_CMD,
DCMI_D11, EVENTOUT
-
-
LQFP208
115
LQFP176
83
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
Additional
functions
-
87
119
C8
D6
D11
145 167 C11
PD3
I/O
FT
-
SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
88
120
C6
B4
D10 146 168 D11
PD4
I/O
FT
-
USART2_RTS, FMC_NOE,
EVENTOUT
-
89
121
B7
C6
C11
147 169 C10
PD5
I/O
FT
-
USART2_TX, FMC_NWE,
EVENTOUT
-
-
122
F8
A4
D8
148 170
F8
VSS
S
-
-
-
-
-
123
F7
-
C8
149 171
E9
VDD
S
-
-
-
-
90
124
D7
E7
B11
150 172
B11
PD6
I/O
FT
-
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
-
91
-
A8
A5
A11
151 173
A11
PD7
I/O
FT
-
USART2_CK, FMC_NE1,
EVENTOUT
-
-
-
-
-
-
-
174 B10
PJ12
I/O
FT
-
LCD_G3, LCD_B0,
EVENTOUT
-
-
-
-
-
-
-
175
B9
PJ13
I/O
FT
-
LCD_G4, LCD_B1,
EVENTOUT
-
-
-
-
-
-
-
176
C9
PJ14
I/O
FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
-
-
177 D10
PJ15
I/O
FT
-
LCD_B3, EVENTOUT
-
-
125
E6
D7
C10 152 178
D9
PG9
I/O
FT
-
USART6_RX,
QUADSPI_BK2_IO2,
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT
-
-
126
E7
C7
B10 153 179
C8
PG10
I/O
FT
-
LCD_G3, FMC_NE3,
DCMI_D2, LCD_B2,
EVENTOUT
-
-
127
B6
B6
B9
B8
PG11
I/O
FT
-
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
154 180
DS11118 Rev 7
67/220
83
Pinouts and pin description
STM32F479xx
128
-
-
A6
A6
E8
B8
A8
155 181
156 182
C7
B3
PG12
PG13
Pin types
TFBGA216
LQFP208
LQFP176
UFBGA176
WLCSP168
UFBGA169
A7
Pin name
(function after
reset)(1)
I/O
I/O
FT
FT
Notes
-
LQFP144
LQFP100
Pin number
I/O structures
Table 10. STM32F479xx pin and ball definitions (continued)
Alternate functions
Additional
functions
-
SPI6_MISO,
USART6_RTS, LCD_B4,
FMC_NE4, LCD_B1,
EVENTOUT
-
-
TRACED0, SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_RMII
_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
-
-
-
-
-
A7
157 183
A4
PG14
I/O
FT
-
TRACED1, SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII
_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
129
-
B7
D7
158 184
F7
VSS
S
-
-
-
-
-
130
-
A7
C7
159 185
E8
VDD
S
-
-
-
-
-
-
-
-
-
-
186
D8
PK3
I/O
FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
-
-
187
D7
PK4
I/O
FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
-
-
188
C6
PK5
I/O
FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
-
-
189
C5
PK6
I/O
FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
-
-
190
C4
PK7
I/O
FT
-
LCD_DE, EVENTOUT
-
-
131
F6
D8
B7
160 191
B7
PG15
I/O
FT
-
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
-
92
132
B5
A8
A10 161 192 A10
93
133
D6
C8
A9
94
95
134
135
68/220
D5
C5
B8
G8
A6
B6
162 193
163 194
164 195
A9
A8
B6
PB3(JTDO/TRA
CESWO)
I/O
FT
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
EVENTOUT
PB4(NJTRST)
I/O
FT
-
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
I2S3ext_SD, EVENTOUT
-
-
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10,
LCD_G7, EVENTOUT
-
-
TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
-
PB5
PB6
I/O
I/O
DS11118 Rev 7
FT
FT
STM32F479xx
Pinouts and pin description
Table 10. STM32F479xx pin and ball definitions (continued)
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions
96
136
B4
A9
B5
165 196
B5
PB7
I/O
FT
-
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
DCMI_VSYNC, EVENTOUT
-
97
137
A5
F8
D6
166 197
E6
BOOT0
I
B
-
-
VPP
-
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
ETH_MII_TXD3, SDIO_D4,
DCMI_D6, LCD_B6,
EVENTOUT
-
-
98
138
D4
B9
A5
LQFP208
LQFP100
Pin number
167 198
A7
PB8
I/O
FT
Additional
functions
139
C4
E9
B4
168 199
B4
PB9
I/O
FT
-
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
140
A4
A10
A4
169 200
A6
PE0
I/O
FT
-
TIM4_ETR, UART8_Rx,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
(2)
141
A3
C9
A3
170 201
A5
PE1
I/O
FT
-
UART8_Tx, FMC_NBL1,
DCMI_D3, EVENTOUT
-
-
-
E3
B10
D5
202
F6
VSS
S
-
-
-
-
-
142
C3
D9
C6
171 203
E5
PDR_ON
S
-
-
-
-
100 143
D3
A11
C5
172 204
E7
VDD
S
-
-
-
-
99
NC
(2)
NC
-
-
-
B3
D10
D4
173 205
C3
PI4
I/O
FT
-
TIM8_BKIN, FMC_NBL2,
DCMI_D5, LCD_B4,
EVENTOUT
-
-
-
A2
C10
C4
174 206
D3
PI5
I/O
FT
-
TIM8_CH1, FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
-
-
A1
B11
C3
175 207
D6
PI6
I/O
FT
-
TIM8_CH2, FMC_D28,
DCMI_D6, LCD_B6,
EVENTOUT
-
-
-
B1
A12
C2
176 208
D4
PI7
I/O
FT
-
TIM8_CH3, FMC_D29,
DCMI_D7, LCD_B7,
EVENTOUT
-
1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to “0” in the
output data register to avoid extra current consumption in low power modes.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from www.st.com.
5.
FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
DS11118 Rev 7
69/220
83
Pinouts and pin description
STM32F479xx
6. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active
low).
7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.
70/220
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Table 11. FMC pin definition
Pin name
NOR/PSRAM/SRAM
NOR/PSRAM Mux
NAND16
SDRAM
PF0
A0
-
-
A0
PF1
A1
-
-
A1
PF2
A2
-
-
A2
PF3
A3
-
-
A3
PF4
A4
-
-
A4
PF5
A5
-
-
A5
PF12
A6
-
-
A6
PF13
A7
-
-
A7
PF14
A8
-
-
A8
PF15
A9
-
-
A9
PG0
A10
-
-
A10
PG1
A11
-
-
A11
PG2
A12
-
-
A12
PG3
A13
-
-
PG4
A14
-
-
BA0
PG5
A15
-
-
BA1
PD11
A16
A16
CLE
-
PD12
A17
A17
ALE
-
PD13
A18
A18
-
-
PE3
A19
A19
-
-
PE4
A20
A20
-
-
PE5
A21
A21
-
-
PE6
A22
A22
-
-
PE2
A23
A23
-
-
PG13
A24
A24
-
-
PG14
A25
A25
-
-
PD14
D0
DA0
D0
D0
PD15
D1
DA1
D1
D1
PD0
D2
DA2
D2
D2
PD1
D3
DA3
D3
D3
PE7
D4
DA4
D4
D4
PE8
D5
DA5
D5
D5
PE9
D6
DA6
D6
D6
PE10
D7
DA7
D7
D7
PE11
D8
DA8
D8
D8
DS11118 Rev 7
71/220
83
Pinouts and pin description
STM32F479xx
Table 11. FMC pin definition (continued)
72/220
Pin name
NOR/PSRAM/SRAM
NOR/PSRAM Mux
NAND16
SDRAM
PE12
D9
DA9
D9
D9
PE13
D10
DA10
D10
D10
PE14
D11
DA11
D11
D11
PE15
D12
DA12
D12
D12
PD8
D13
DA13
D13
D13
PD9
D14
DA14
D14
D14
PD10
D15
DA15
D15
D15
PH8
D16
-
-
D16
PH9
D17
-
-
D17
PH10
D18
-
-
D18
PH11
D19
-
-
D19
PH12
D20
-
-
D20
PH13
D21
-
-
D21
PH14
D22
-
-
D22
PH15
D23
-
-
D23
PI0
D24
-
-
D24
PI1
D25
-
-
D25
PI2
D26
-
-
D26
PI3
D27
-
-
D27
PI6
D28
-
-
D28
PI7
D29
-
-
D29
PI9
D30
-
-
D30
PI10
D31
-
-
D31
PD7
NE1
NE1
-
-
PG9
NE2
NE2
NCE
-
PG10
NE3
NE3
-
-
PG11
-
-
-
-
PG12
NE4
NE4
-
-
PD3
CLK
CLK
-
-
PD4
NOE
NOE
NOE
-
PD5
NWE
NWE
NWE
-
PD6
NWAIT
NWAIT
NWAIT
-
PB7
NADV
NADV
-
-
PF6
-
-
-
-
PF7
-
-
-
-
DS11118 Rev 7
STM32F479xx
Pinouts and pin description
Table 11. FMC pin definition (continued)
Pin name
NOR/PSRAM/SRAM
NOR/PSRAM Mux
NAND16
SDRAM
PF8
-
-
-
-
PF9
-
-
-
-
PF10
-
-
-
-
PG6
-
-
-
-
PG7
-
-
INT
-
PE0
NBL0
NBL0
-
NBL0
PE1
NBL1
NBL1
-
NBL1
PI4
NBL2
-
-
NBL2
PI5
NBL3
-
-
NBL3
PG8
-
-
-
SDCLK
PC0
-
-
-
SDNWE
PF11
-
-
-
SDNRAS
PG15
-
-
-
SDNCAS
PH2
-
-
-
SDCKE0
PH3
-
-
-
SDNE0
PH6
-
-
-
SDNE1
PH7
-
-
-
SDCKE1
PH5
-
-
-
SDNWE
PC2
-
-
-
SDNE0
PC3
-
-
-
SDCKE0
PB5
-
-
-
SDCKE1
PB6
-
-
-
SDNE1
DS11118 Rev 7
73/220
83
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
PA0
-
TIM2_CH1/
TIM2_ETR
PA1
-
PA2
DS11118 Rev 7
Port
A
AF9
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
TIM5_CH1
TIM8_ETR
-
-
-
USART2_
CTS
UART4_
TX
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_
RTS
-
TIM2_CH3
TIM5_CH3
TIM9_CH1
-
-
-
PA3
-
TIM2_CH4
TIM5_CH4
TIM9_CH2
-
-
PA4
-
-
-
-
-
PA5
-
TIM2_CH1/
TIM2_ETR
-
TIM8_CH1
N
PA6
-
TIM1_BKIN
TIM3_CH1
PA7
-
TIM1_
CH1N
PA8
MCO1
PA9
AF10
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
-
-
ETH_MII_CRS
-
-
-
EVENT
OUT
UART4_
RX
QUADSPI_
BK1_IO3
-
ETH_MII_RX_
CLK/ETH_RMI
I_REF_CLK
-
-
LCD_R2
EVENT
OUT
USART2_T
X
-
-
-
ETH_MDIO
-
-
LCD_R1
EVENT
OUT
-
USART2_
RX
-
LCD_B2
OTG_HS
_ULPI_D0
ETH_MII_COL
-
-
LCD_B5
EVENT
OUT
SPI1_NSS
SPI3_NSS/
I2S3_WS
USART2_
CK
-
-
-
-
OTG_HS_S
OF
DCMI_HS
YNC
LCD_VSY
NC
EVENT
OUT
-
SPI1_SCK
-
-
-
-
OTG_HS
_ULPI_C
K
-
-
-
LCD_R4
EVENT
OUT
TIM8_BKI
N
-
SPI1_
MISO
-
-
-
TIM13_CH1
-
-
-
DCMI_PIX
CLK
LCD_G2
EVENT
OUT
TIM3_CH2
TIM8_CH1
N
-
SPI1_
MOSI
-
-
-
TIM14_CH1
QUADSPI
_CLK
ETH_MII_RX_
DV/ETH_RMII
_CRS_DV
FMC_SDN
WE
-
-
EVENT
OUT
TIM1_CH1
-
-
I2C3_SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
-
-
-
LCD_R6
EVENT
OUT
-
TIM1_CH2
-
-
I2C3_SMBA
SPI2_SCK/I
2S2_CK
-
USART1_T
X
-
-
-
-
-
DCMI_D0
-
EVENT
OUT
PA10
-
TIM1_CH3
-
-
-
-
-
USART1_
RX
-
-
OTG_FS_
ID
-
-
DCMI_D1
-
EVENT
OUT
PA11
-
TIM1_CH4
-
-
-
-
-
USART1_
CTS
-
CAN1_RX
OTG_FS_
DM
-
-
-
LCD_R4
EVENT
OUT
PA12
-
TIM1_ETR
-
-
-
-
-
USART1_
RTS
-
CAN1_TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENT
OUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
-
-
-
SPI1_NSS
SPI3_NSS/
I2S3_WS
-
-
-
-
-
-
-
-
EVENT
‘OUT
STM32F479xx
AF11
Port
AF8
Pinouts and pin description
74/220
Table 12. Alternate function
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2
N
-
-
-
-
-
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3
N
-
-
-
-
PB2
-
-
-
-
-
-
-
PB3
JTDO /
TRACES
WO
TIM2_CH2
-
-
SPI1_SCK
PB4
NJTRST
-
TIM3_CH1
-
-
PB5
-
-
TIM3_CH2
-
PB6
-
-
TIM4_CH1
DS11118 Rev 7
Port
B
PB7
-
-
PB8
-
PB9
AF9
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
LCD_R3
OTG_HS
_ULPI_D1
ETH_MII_
RXD2
-
-
LCD_G1
EVENT
OUT
-
LCD_R6
OTG_HS
_ULPI_D2
ETH_MII_
RXD3
-
-
LCD_G0
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
SPI3_SCK/
I2S3_CK
-
-
-
-
-
-
-
-
EVENT
OUT
SPI1_MISO
SPI3_MIS
O
I2S3ext
_SD
-
-
-
-
-
-
-
EVENT
OUT
I2C1_SMBA
SPI1_MOSI
SPI3_MOS
I/I2S3_SD
-
CAN2_RX
OTG_HS
_ULPI_D7
ETH_PPS
OUT
FMC_
SDCKE1
DCMI_D10
LCD_G7
EVENT
OUT
-
I2C1_SCL
-
-
USART1
_TX
-
CAN2_TX
QUADSPI
_BK1_NC
S
-
FMC_
SDNE1
DCMI_D5
EVENT
OUT
TIM4_CH2
-
I2C1_SDA
-
-
USART1_
RX
-
-
-
-
FMC_NL
DCMI_VS
YNC
EVENT
OUT
-
TIM4_CH3
TIM10_CH
1
I2C1_SCL
-
-
-
-
CAN1_RX
-
ETH_MII_
TXD3
SDIO_D4
DCMI_D6
LCD_B6
EVENT
OUT
-
-
TIM4_CH4
TIM11_CH
1
I2C1_SDA
SPI2_NSS/I
2S2_WS
-
-
-
CAN1_TX
-
-
SDIO_D5
DCMI_D7
LCD_B7
EVENT
OUT
PB10
-
TIM2_CH3
-
-
I2C2_SCL
SPI2_SCK/I
2S2_CK
-
USART3
_TX
-
QUADSPI_
BK1_NCS
OTG_HS
_ULPI_D3
ETH_MII_RX_
ER
-
-
LCD_G4
EVENT
OUT
PB11
-
TIM2_CH4
-
-
I2C2_SDA
-
USART3
_RX
-
OTG_HS
_ULPI_D4
ETH_MII_TX_
EN/ETH_RMII
_TX_EN
-
DSIHOST_
TE
LCD_G5
EVENT
OUT
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS/I
2S2_WS
-
USART3
_CK
-
CAN2_RX
OTG_HS
_ULPI_D5
ETH_MII_TXD
0/ETH_RMII_T
XD0
OTG_HS_
ID
-
-
EVENT
OUT
PB13
-
TIM1_CH1N
-
-
-
SPI2_SCK/I
2S2_CK
-
USART3
_CTS
-
CAN2_TX
OTG_HS
_ULPI_D6
ETH_MII_TXD
1/ETH_RMII_T
XD1
-
-
-
EVENT
OUT
PB14
-
TIM1_CH2N
-
TIM8_CH2
N
-
SPI2_MISO
I2S2ext_S
D
USART3
_RTS
-
TIM12_CH1
-
-
OTG_HS_
‘DM
-
-
EVENT
OUT
PB15
RTC
_REFIN
TIM1_CH3N
-
TIM8_CH3
N
-
SPI2_MOSI
/I2S2_SD
-
-
-
TIM12_CH2
-
-
OTG_HS_
DP
-
-
EVENT
‘OUT
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
75/220
Pinouts and pin description
AF11
Port
AF8
STM32F479xx
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
PC0
-
-
PC1
TRACE
D0
PC2
DS11118 Rev 7
Port
C
AF9
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
-
-
-
-
-
-
-
-
OTG_HS
_ULPI_ST
P
-
FMC_SDN
WE
-
LCD_R5
EVENT
OUT
-
-
-
-
SPI2_MOSI
/I2S2_SD
SAI1_SD_
A
-
-
-
ETH_MDC
-
-
-
EVENT
OUT
-
-
-
-
-
SPI2_MISO
I2S2ext_S
D
-
-
-
OTG_HS
_ULPI_DI
R
ETH_MII_TXD
2
FMC_SDN
E0
-
-
EVENT
OUT
PC3
-
-
-
-
-
SPI2_MOSI
/I2S2_SD
-
-
-
-
OTG_HS
_ULPI_N
XT
ETH_MII_TX_
CLK
FMC_SDC
KE0
-
-
EVENT
OUT
PC4
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RXD
0/ETH_RMII_R
XD0
FMC_SDN
E0
-
-
EVENT
OUT
PC5
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RXD
1/ETH_RMII_R
XD1
FMC_SDC
KE0
-
-
EVENT
OUT
PC6
-
-
TIM3_CH1
TIM8_CH1
-
I2S2_MCK
-
-
USART6
_TX
-
-
-
SDIO_D6
DCMI_D0
LCD_HSY
NC
EVENT
OUT
PC7
-
-
TIM3_CH2
TIM8_CH2
-
-
I2S3_MCK
-
USART6
_RX
-
-
-
SDIO_D7
DCMI_D1
LCD_G6
EVENT
OUT
PC8
TRACE
D1
-
TIM3_CH3
TIM8_CH3
-
-
-
-
USART6
_CK
-
-
-
SDIO_D0
DCMI_D2
-
EVENT
OUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
-
QUADSPI_
BK1_IO0
-
-
SDIO_D1
DCMI_D3
-
EVENT
OUT
PC10
-
-
-
-
-
-
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_
TX
QUADSPI_
BK1_IO1
-
-
SDIO_D2
DCMI_D8
LCD_R2
EVENT
OUT
PC11
-
-
-
-
-
I2S3ext_SD
SPI3_MIS
O
USART3_
RX
UART4_
RX
QUADSPI_
BK2_NCS
-
-
SDIO_D3
DCMI_D4
-
EVENT
OUT
PC12
TRACE
D3
-
-
-
-
-
SPI3_MOS
I/I2S3_SD
USART3_
CK
UART5_
TX
-
-
-
SDIO_CK
DCMI_D9
-
EVENT
OUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
‘OUT
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
STM32F479xx
AF11
Port
AF8
Pinouts and pin description
76/220
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
PD0
-
-
-
-
-
-
-
-
-
PD1
-
-
-
-
-
-
-
-
PD2
TRACE
D2
-
TIM3_ETR
-
-
-
-
PD3
-
-
-
-
-
SPI2_SCK/I
2S2_CK
PD4
-
-
-
-
-
PD5
-
-
-
-
PD6
-
-
-
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
CAN1_RX
-
-
FMC_D2
-
-
EVENT
OUT
-
CAN1_TX
-
-
FMC_D3
-
-
EVENT
OUT
-
UART5_
RX
-
-
-
SDIO_CMD
DCMI_D11
-
EVENT
OUT
-
USART2_
CTS
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENT
OUT
-
-
USART2_
RTS
-
-
-
-
FMC_NOE
-
-
EVENT
OUT
-
-
-
USART2_T
X
-
-
-
-
FMC_NWE
-
-
EVENT
OUT
-
-
SPI3_MOSI
/I2S3_SD
SAI1_SD_
A
USART2_
RX
-
-
-
-
FMC_NWAI
T
DCMI_D10
LCD_B2
EVENT
OUT
PD7
-
-
-
-
-
-
-
USART2_
CK
-
-
-
-
FMC_NE1
-
-
EVENT
OUT
PD8
-
-
-
-
-
-
-
USART3_T
X
-
-
-
-
FMC_D13
-
-
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_
RX
-
-
-
-
FMC_D14
-
-
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_
CK
-
-
-
-
FMC_D15
-
LCD_B3
EVENT
OUT
PD11
-
-
-
-
-
-
-
USART3_
CTS
-
QUADSPI_
BK1_IO0
-
-
FMC_A16/F
MC_CLE
-
-
EVENT
OUT
PD12
-
-
TIM4_CH1
-
-
-
-
USART3_
RTS
-
QUADSPI_
BK1_IO1
-
-
FMC_A17/F
MC_ALE
-
-
EVENT
OUT
PD13
-
-
TIM4_CH2
-
-
-
-
-
-
QUADSPI_
BK1_IO3
-
-
FMC_A18
-
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
-
-
-
-
FMC_D0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
-
-
-
-
-
-
FMC_D1
-
-
EVENT
‘OUT
DS11118 Rev 7
Port
D
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
77/220
Pinouts and pin description
AF11
Port
AF8
STM32F479xx
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
PE0
-
-
TIM4_ETR
-
-
-
-
-
UART8_
Rx
PE1
-
-
-
-
-
-
-
-
PE2
TRACE
CLK
-
-
-
-
SPI4_SCK
SAI1_
MCLK_A
PE3
TRACE
D0
-
-
-
-
-
PE4
TRACE
D1
-
-
-
-
PE5
TRACE
D2
-
-
TIM9_CH1
PE6
TRACE
D3
-
-
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
-
-
-
FMC_NBL0
DCMI_D2
-
EVENT
OUT
UART8_
Tx
-
-
-
FMC_NBL1
DCMI_D3
-
EVENT
OUT
-
-
QUADSPI_
BK1_IO2
-
ETH_MII_TXD
3
FMC_A23
-
-
EVENT
OUT
SAI1
_SD_B
-
-
-
-
-
FMC_A19
-
-
EVENT
OUT
SPI4_NSS
SAI1
_FS_A
-
-
-
-
-
FMC_A20
DCMI_D4
LCD_B0
EVENT
OUT
-
SPI4_MISO
SAI1
_SCK_A
-
-
-
-
-
FMC_A21
DCMI_D6
LCD_G0
EVENT
OUT
TIM9_CH2
-
SPI4_MOSI
SAI1
_SD_A
-
-
-
-
-
FMC_A22
DCMI_D7
LCD_G1
EVENT
OUT
PE7
-
TIM1_ETR
-
-
-
-
-
-
UART7_
Rx
-
QUADSPI
_BK2_IO0
-
FMC_D4
-
-
EVENT
OUT
PE8
-
TIM1_CH1N
-
-
-
-
-
-
UART7_
Tx
-
QUADSPI
_BK2_IO1
-
FMC_D5
-
-
EVENT
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
QUADSPI
_BK2_IO2
-
FMC_D6
-
-
EVENT
OUT
PE10
-
TIM1_CH2N
-
-
-
-
-
-
-
-
QUADSPI
_BK2_IO3
-
FMC_D7
-
-
EVENT
OUT
PE11
-
TIM1_CH2
-
-
-
SPI4_NSS
-
-
-
-
-
-
FMC_D8
-
LCD_G3
EVENT
OUT
PE12
-
TIM1_CH3N
-
-
-
SPI4_SCK
-
-
-
-
-
-
FMC_D9
-
LCD_B4
EVENT
OUT
PE13
-
TIM1_CH3
-
-
-
SPI4_MISO
-
-
-
-
-
-
FMC_D10
-
LCD_DE
EVENT
OUT
PE14
-
TIM1_CH4
-
-
-
SPI4_MOSI
-
-
-
-
-
-
FMC_D11
-
LCD_CLK
EVENT
OUT
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
FMC_D12
-
LCD_R7
EVENT
‘OUT
DS11118 Rev 7
Port
E
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
STM32F479xx
AF11
Port
AF8
Pinouts and pin description
78/220
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
PF1
-
-
-
-
I2C2_SCL
-
-
-
PF2
-
-
-
-
I2C2_SMBA
-
-
PF3
-
-
-
-
-
-
PF4
-
-
-
-
-
PF5
-
-
-
-
PF6
-
-
-
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
-
-
-
FMC_A0
-
-
EVENT
OUT
-
-
-
-
FMC_A1
-
-
EVENT
OUT
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
TIM10_CH
1
-
SPI5_NSS
SAI1_
SD_B
-
UART7_
Rx
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENT
OUT
PF7
-
-
-
TIM11_CH
1
-
SPI5_SCK
SAI1_
MCLK_B
-
UART7_
Tx
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENT
OUT
PF8
-
-
-
-
-
SPI5_MISO
SAI1_
SCK_B
-
-
TIM13_CH1
QUADSPI
_BK1_IO0
-
-
-
-
EVENT
OUT
PF9
-
-
-
-
-
SPI5_MOSI
SAI1_
FS_B
-
-
TIM14_CH1
QUADSPI
_BK1_IO1
-
-
-
-
EVENT
OUT
PF10
-
-
-
-
-
-
-
-
-
QUADSPI_
CLK
-
-
DCMI_D11
LCD_DE
EVENT
OUT
PF11
-
-
-
-
-
SPI5_MOSI
-
-
-
-
-
-
FMC_SDN
RAS
DCMI_D12
-
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
PF13
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
PF14
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
PF15
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
‘OUT
DS11118 Rev 7
Port
F
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
79/220
Pinouts and pin description
AF11
Port
AF8
STM32F479xx
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
PG0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A12
-
-
EVENT
OUT
PG3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A13
-
-
EVENT
OUT
PG4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A14/F
MC_BA0
-
-
EVENT
OUT
PG5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A15/F
MC_BA1
-
-
EVENT
OUT
PG6
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D12
LCD_R7
EVENT
OUT
PG7
-
-
-
-
-
USART6
_CK
-
-
-
FMC_INT
DCMI_D13
LCD_CLK
EVENT
OUT
PG8
-
-
-
-
-
SPI6_NSS
-
-
USART6
_RTS
-
-
ETH_PPS_OU
T
FMC_SDCL
K
LCD_G7
EVENT
OUT
PG9
-
-
-
-
-
-
-
-
USART6
_RX
QUADSPI_
BK2_IO2
-
-
FMC_NE2/
FMC_NCE
DCMI_VS
YNC
PG10
-
-
-
-
-
-
-
-
LCD_G3
-
-
FMC_NE3
DCMI_D2
LCD_B2
EVENT
OUT
PG11
-
-
-
-
-
-
-
-
-
-
-
ETH_MII
_TX_EN /
ETH_RMII
_TX_EN
-
DCMI_D3
LCD_B3
EVENT
OUT
PG12
-
-
-
-
-
SPI6_MISO
-
-
USART6
_RTS
LCD_B4
-
-
FMC_NE4
-
LCD_B1
EVENT
OUT
PG13
TRACE
D0
-
-
-
-
SPI6_SCK
-
-
USART6
_CTS
-
-
ETH_MII
_TXD0 /
ETH_RMII
_TXD0
FMC_A24
-
LCD_R0
EVENT
OUT
PG14
TRACE
D1
-
-
-
-
SPI6_MOSI
-
-
USART6
_TX
QUADSPI_
BK2_IO3
-
ETH_MII
_TXD1 /
ETH_RMII
_TXD1
FMC_A25
-
LCD_B0
EVENT
OUT
PG15
-
-
-
-
-
-
-
-
USART6
_CTS
-
-
-
FMC_
SDNCAS
DCMI_D13
-
EVENT
‘OUT
Port
DS11118 Rev 7
SAI1
_MCLK_A
Port
G
AF8
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
Pinouts and pin description
80/220
Table 12. Alternate function (continued)
EVENT
OUT
STM32F479xx
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH2
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO0
-
ETH_MII_CRS
FMC_SDC
KE0
-
LCD_R0
EVENT
OUT
PH3
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO1
-
ETH_MII_COL
FMC_SDN
E0
-
LCD_R1
EVENT
OUT
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
OTG_HS
_ULPI_N
XT
-
-
-
LCD_G4
EVENT
OUT
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
-
-
-
-
-
FMC_SDN
WE
-
-
EVENT
OUT
PH6
-
-
-
-
I2C2_SMBA
SPI5_SCK
-
-
-
TIM12_CH1
-
ETH_MII_RXD
2
FMC_SDN
E1
-
-
EVENT
OUT
PH7
-
-
-
-
I2C3_SCL
SPI5_MISO
-
-
-
-
-
ETH_MII_RXD
3
FMC_SDC
KE1
DCMI_D9
-
EVENT
OUT
PH8
-
-
-
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_HS
YNC
LCD_R2
EVENT
OUT
PH9
-
-
-
-
I2C3_SMBA
-
-
-
-
TIM12_CH2
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENT
OUT
PH10
-
-
TIM5_CH1
-
-
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENT
OUT
PH11
-
-
TIM5_CH2
-
-
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENT
OUT
PH12
-
-
TIM5_CH3
-
-
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENT
OUT
PH13
-
-
-
TIM8_CH1
N
-
-
-
-
-
CAN1_TX
-
-
FMC_D21
-
LCD_G2
EVENT
OUT
PH14
-
-
-
TIM8_CH2
N
-
-
-
-
-
-
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENT
OUT
PH15
-
-
-
TIM8_CH3
N
-
-
-
-
-
-
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENT
‘OUT
Port
DS11118 Rev 7
Port
H
AF8
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
STM32F479xx
Table 12. Alternate function (continued)
EVENT
OUT
Pinouts and pin description
81/220
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/I
2S2_WS
-
-
-
-
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENT
OUT
PI1
-
-
-
-
-
SPI2_SCK/I
2S2_CK
-
-
-
-
-
-
FMC_D25
DCMI_D8
LCD_G6
EVENT
OUT
PI2
-
-
-
TIM8_CH4
-
SPI2_MISO
I2S2ext_S
D
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENT
OUT
PI3
-
-
-
TIM8_ETR
-
SPI2_MOSI
/I2S2_SD
-
-
-
-
-
-
FMC_D27
DCMI_D10
PI4
-
-
-
TIM8_BKI
N
-
-
-
-
-
-
-
-
FMC_NBL2
DCMI_D5
LCD_B4
EVENT
OUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
-
-
FMC_NBL3
DCMI_VS
YNC
LCD_B5
EVENT
OUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
FMC_D28
DCMI_D6
LCD_B6
EVENT
OUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
FMC_D29
DCMI_D7
LCD_B7
EVENT
OUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI9
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
FMC_D30
-
LCD_VSY
NC
EVENT
OUT
PI10
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RX_
ER
FMC_D31
-
LCD_HSY
NC
EVENT
OUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS
_ULPI
_DIR
-
-
-
-
EVENT
OUT
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_HSY
NC
EVENT
OUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VSY
NC
EVENT
OUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
EVENT
OUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVENT
‘OUT
Port
AF8
AF9
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
Pinouts and pin description
82/220
Table 12. Alternate function (continued)
EVENT
OUT
DS11118 Rev 7
Port I
EVENT
OUT
STM32F479xx
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
PJ0
-
-
-
-
-
-
-
-
-
PJ1
-
-
-
-
-
-
-
-
PJ2
-
-
-
-
-
-
-
PJ3
-
-
-
-
-
-
PJ4
-
-
-
-
-
PJ5
-
-
-
-
PJ12
-
-
-
PJ13
-
-
PJ14
-
PJ15
AF9
AF12
AF13
AF14
AF15
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST
LCD
SYS
LCD_R7
-
-
-
-
LCD_R1
EVENT
OUT
-
-
-
-
-
-
LCD_R2
EVENT
OUT
-
-
-
-
-
-
DSIHOST
_TE
LCD_R3
EVENT
OUT
-
-
-
-
-
-
-
-
LCD_R4
EVENT
OUT
-
-
-
-
-
-
-
-
-
LCD_R5
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENT
OUT
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENT
OUT
-
-
-
-
-
-
-
LCD_G4
-
-
-
-
LCD_B1
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENT
OUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENT
OUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENT
OUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENT
OUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENT
OUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENT
OUT
USAR CAN1/2/
TIM12/
T6/
13/14/
UART
QUAD
4/5/7/
SPI/LCD
8
AF10
Port
J
DS11118 Rev 7
Port
K
83/220
Pinouts and pin description
AF11
Port
AF8
STM32F479xx
Table 12. Alternate function (continued)
Memory mapping
4
STM32F479xx
Memory mapping
The memory map is shown in Figure 21.
Figure 21. Memory map
0xFFFF FFFF
0xE000 0000
0xDFFF FFFF
Reserved
0xE010 0000 - 0xFFFF FFFF
Cortex®-M4
internal peripheral
0xE000 0000 - 0xE00F FFFF
AHB3
0x6000 0000 - 0xDFFF FFFF
Reserved
0x5006 0C00 - 0x5FFF FFFF
0x5006 0BFF
AHB2
512-Mbyte
Block 7
Cortex®-4
Internal
peripherals
0x5000 0000
Reserved
0x4008 0000 - 0x4FFF FFFF
0x4007 FFFF
512-Mbyte
Block 6
FMC
0xD000 0000
0xCFFF FFFF
AHB1
512-Mbyte
Block 5
FMC and
QUADSPI
0xA000 0000
0x9FFF FFFF
512-Mbyte
Block 4
FMC bank3 and
QUADSPI bank
0x8000 0000
0x7FFF FFFF
0x4002 0000
Reserved
0x4001 7400 - 0x4001 FFFF
0x4001 73FF
512-Mbyte
Block 3
FMC bank1 to
QUADSPI bank 2
0x6000 0000
0x5FFF FFFF
512-Mbyte
Block 2
Peripherals
APB2
0x4000 0000
0x3FFF FFFF
512-Mbyte
Block 1
SRAM
0x2000 0000
0x1FFF FFFF
512-Mbyte
Block 0
SRAM
0x0000 0000
Reserved
SRAM3
(128 KB aliased by bit-banding)
SRAM2
(32 KB aliased by bit-banding)
0x2005 0000 - 0x3FFF FFFF
0x2003 0000 - 0x2004 FFFF
0x2002 8000 - 0x2002 FFFF
SRAM1
(160 KB aliased by bit-banding)
0x2000 0000 - 0x2002 7FFF
Reserved
0x1FFF C008 - 0x1FFF FFFF
Option Bytes
Reserved
System memory
Reserved
Option bytes
0x1FFF C000 - 0x1FFF C00 F
Reserved
CCM data RAM
(64 KB data SRAM)
Reserved
Flash memory
Reserved
Aliased to Flash, system
memory or SRAM depending
on the BOOT pins
Reserved
0x1FFF 7A10 - 0x1FFF 7FFF
0x1FFF 0000 - 0x1FFF 7A0F
0x1FFE C008 - 0x1FFE FFFF
0x1FFE C000 - 0x1FFE C00 F
0x4001 0000
0x4000 8000 - 0x4000 FFFF
0x4000 7FFF
APB1
0x1001 0000 - 0x1FFE BFFF
0x1000 0000 - 0x1000 FFFF
0x0820 0000 - 0x0FFF FFFF
0x0800 0000 - 0x081F FFFF
0x0020 0000 - 0x07FF FFFF
0x4000 0000
0x0000 0000 - 0x001F FFFF
MSv33863V2
84/220
DS11118 Rev 7
STM32F479xx
Memory mapping
Table 13. STM32F479xx register boundary addresses(1)
Bus
Boundary address
-
0xE00F FFFF - 0xFFFF FFFF
Reserved
0xE000 0000 - 0xE00F FFFF
Cortex®-M4 internal peripherals
0xD000 0000 - 0xDFFF FFFF
FMC bank 6
0xC000 0000 - 0xCFFF FFFF
FMC bank 5
®
Cortex -M4
AHB3
-
AHB2
Peripheral
0xA000 1000 - 0xA0001FFF
Quad-SPI control register
0xA000 2000 - 0xBFFF FFFF
Reserved
0xA000 0000- 0xA000 0FFF
FMC control register
0x9000 0000 - 0x9FFF FFFF
Quad-SPI bank
0x8000 0000 - 0x8FFF FFFF
FMC bank 3
0x7000 0000 - 0x7FFF FFFF
FMC bank 2 (reserved)
0x6000 0000 - 0x6FFF FFFF
FMC bank 1
0x5006 0C00- 0x5FFF FFFF
Reserved
0x5006 0800 - 0x5006 0BFF
RNG
0x5006 0400 - 0x5006 07FF
HASH
0x5006 0000 - 0x5006 03FF
CRYP
0x5005 0400 - 0x5005 FFFF
Reserved
0x5005 0000 - 0x5005 03FF
DCMI
0x5004 0000- 0x5004 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USB OTG FS
DS11118 Rev 7
85/220
88
Memory mapping
STM32F479xx
Table 13. STM32F479xx register boundary addresses(1) (continued)
Bus
Boundary address
Peripheral
-
0x4008 0000- 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
USB OTG HS
0x4002 BC00- 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Chrom (DMA2D)
0x4002 9400 - 0x4002 AFFF
Reserved
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
ETHERNET MAC
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
AHB1
86/220
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
Flash interface register
0x4002 3800 - 0x4002 3BFF
RCC
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
GPIOK
0x4002 2400 - 0x4002 27FF
GPIOJ
0x4002 2000 - 0x4002 23FF
GPIOI
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0x4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
DS11118 Rev 7
STM32F479xx
Memory mapping
Table 13. STM32F479xx register boundary addresses(1) (continued)
Bus
APB2
Boundary address
Peripheral
0x4001 7400 - 0x4001 FFFF
Reserved
0x4001 6C00 - 0x4001 73FF
DSI Host
0x4001 6800 - 0x4001 6BFF
LCD-TFT
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
SAI1
0x4001 5400 - 0x4001 57FF
SPI6
0x4001 5000 - 0x4001 53FF
SPI5
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
0x4001 3C00 - 0x4001 3FFF
EXTI
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4
0x4001 3000 - 0x4001 33FF
SPI1
0x4001 2C00 - 0x4001 2FFF
SDIO
0x4001 2400 - 0x4001 2BFF
Reserved
0x4001 2000 - 0x4001 23FF
ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF
Reserved
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0800 - 0x4001 0FFF
Reserved
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
DS11118 Rev 7
87/220
88
Memory mapping
STM32F479xx
Table 13. STM32F479xx register boundary addresses(1) (continued)
Bus
Boundary address
-
0x4000 8000- 0x4000 FFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART8
0x4000 7800 - 0x4000 7BFF
UART7
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PWR
0x4000 6C00 - 0x4000 6FFF
Reserved
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
Reserved
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
I2S3ext
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
I2S2ext
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC & BKP Registers
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
APB1
1. The reserved boundary address are shown in grayed cells
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Peripheral
STM32F479xx
5
5.1
Electrical characteristics
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 22.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 23.
Figure 22. Pin loading conditions
Figure 23. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
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MS19010V2
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Electrical characteristics
5.1.6
STM32F479xx
Power supply scheme
Figure 24. Power supply scheme
VBAT
OUT
GPIOs
2 × 2.2 μF
VCAP_1
VCAP_2
VDD
1/2/...19/20
VSS
1/2/...19/20
20 × 100 nF
+ 1 × 4.7 μF
IN
IO
Logic
Kernel logic
(CPU, digital
& RAM)
Voltage
regulator
BYPASS_REG
VDDUSB
VDDUSB
Level shifter
VBAT = 1.65 to 3.6 V
VDD
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers,
backup RAM)
Power
switch
Flash memory
OTG-FS
PHY
100 nF
VDDDSI
VCAPDSI
VDD12DSI
2.2 μF
DSI
PHY
VSSDSI
PDR_ON
VDD
Reset
controller
VDDA
VREF
100 nF
+ 1 μF
DSI
Voltage
regulator
100 nF
+ 1 μF
VREF+
VREF-
ADC
Analog:
RCs, PLL,..
VSSA
MS38256V1
1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on VCAP_1 and VCAP_2 should be replaced by two 100 nF decoupling
capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA and VSSA must be connected to VDD and VSS, respectively.
Caution:
90/220
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DS11118 Rev 7
STM32F479xx
5.1.7
Electrical characteristics
Current consumption measurement
Figure 25. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14, Table 15, and Table 16
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Table 14. Voltage characteristics
Symbol
VDD–VSS
VIN
Ratings
Min
Max
− 0.3
4.0
Input voltage on FT pins(2)
VSS − 0.3
VDD+4.0
Input voltage on TTa pins
VSS − 0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
VSS
9.0
-
50
-
50
External main supply voltage
(including VDDA, VDD, VDDUSB, VDDDSI and VBAT)(1)
Input voltage on BOOT pin
|VDDx|
|VSSX VSS|
VESD(HBM)
Variations between different VDD power pins
Variations between all the different ground
pins(3)
Electrostatic discharge voltage (human body model)
Unit
V
mV
see Section 5.3.18
1. All main power (VDD, VDDA, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
3. Including VREF- pin
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Table 15. Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into sum of all VDD_x power lines (source)(1)
IVSS
(1)
IVDDUSB
Total current out of sum of all VSS_x ground lines (sink)
290
− 290
Total current into VDDUSB power line (source)
25
IVDD
Maximum current into each VDD_x power line (source)(1)
IVSS
(1)
Maximum current out of each VSS_x ground line (sink)
100
− 100
Output current sunk by any I/O and control pin
IIO
IIO
25
Output current sourced by any I/Os and control pin
− 25
Total output current sunk by sum of all I/O and control pins (2)
120
Total output current sunk by sum of all USB I/Os
25
Total output current sourced by sum of all I/Os and control
Injected current on FT pins
IINJ(PIN) (3)
pins(2)
mA
− 120
(4)
− 5/+0
Injected current on NRST and BOOT0 pins (4)
Injected current on TTa pins(5)
IINJ(PIN)(5)
Unit
Total injected current (sum of all I/O and control
±5
pins)(6)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN 2.4 V, the compensation cell should be used.
Figure 40. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON CL
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.
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Electrical characteristics
5.3.21
STM32F479xx
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Table 61. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
VIN VSS
30
40
50
k
-
-
-
100
VDD > 2.7 V
300
-
-
Internal Reset source
20
-
-
VF(NRST)
(2)
NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
TNRST_OUT
Generated reset pulse duration
ns
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10%).
2. Guaranteed by design.
Figure 41. Recommended NRST pin protection
VDD
External
reset circuit (1)
NRST (2)
RPU
Internal Reset
Filter
0.1 μF
STM32F
ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58. Otherwise the reset is not taken into account by the device.
140/220
DS11118 Rev 7
STM32F479xx
5.3.22
Electrical characteristics
TIM timer characteristics
The parameters given in Table 62 are guaranteed by design. Refer to Section 5.3.20 for
details on the input/output alternate function characteristics (output compare, input capture,
external clock, PWM output).
Table 62. TIMx characteristics(1)(2)
Symbol
tres(TIM)
fEXT
ResTIM
tMAX_COUNT
Conditions(3)
Parameter
Min
Max
Unit
AHB/APBx prescaler =
1 or 2 or 4,
fTIMxCLK = 180 MHz
1
-
tTIMxCLK
AHB/APBx prescaler > 4,
fTIMxCLK = 90 MHz
1
-
tTIMxCLK
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 180 MHz
0
fTIMxCLK/2
MHz
Timer resolution
-
16/32
bit
-
65536 ×
65536
tTIMxCLK
Timer resolution time
Maximum possible count
with 32-bit counter
-
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
5.3.23
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): bit rate up to 100 kbit/s
Fast-mode (Fm): bit rate up to 400 kbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0386 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Refer to
Section 5.3.20 for more details on the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter, whose characteristics are detailed in
Table 63.
Table 63. I2C analog filter characteristics(1)
Symbol
tAF
Parameter
Maximum pulse width of spikes
suppressed by the analog filter
Min
Max
Unit
50(2)
150(3)
ns
1. Guaranteed based on test during characterization.
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Electrical characteristics
STM32F479xx
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 64 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
output speed set to OSPEEDRy[1:0] = 10
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
Table 64. SPI dynamic characteristics(1)
Symbol
fSCK
1/tc(SCK)
Duty(SCK)
142/220
Parameter
SPI clock frequency
Duty cycle of SPI
clock frequency
Min
Typ
Max(2)
Master mode,
2.7 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6,
-
-
45
Master mode,
1.71 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6
-
-
22.5
Master transmitter mode,
1.7 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6
-
-
45
Slave full duplex mode,
2.7 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6
-
-
45
Slave transmitter mode,
1.71 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6
-
-
33
Slave transmitter mode,
2.7 V ≤ VDD ≤ 3.6 V,
SPI1,4,5,6
-
-
45
Slave mode,
1.71 V ≤ VDD ≤ 3.6 V,
SPI2,3
-
-
22.5
30
50
70
Conditions
Slave mode
DS11118 Rev 7
Unit
MHz
%
STM32F479xx
Electrical characteristics
Table 64. SPI dynamic characteristics(1) (continued)
Min
Typ
Max(2)
Master mode, SPI presc = 2
TPCLK−1.5
TPCLK
TPCLK+1.5
NSS setup time
Slave mode, SPI presc = 2
4 TPCLK
NSS hold time
Slave mode, SPI presc = 2
2 TPCLK
-
-
Symbol
Parameter
tw(SCKH)
tw(SCKL)
SCK high and low time
tsu(NSS)
th(NSS)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
Conditions
Master mode
2
-
-
Slave mode
3
-
-
Master mode
4
-
-
Slave mode
2
-
-
ta(SO)
Data output access time Slave mode, SPI presc = 2
7
-
21
tdis(SO)
Data output disable time Slave mode
5
-
12
Slave mode,
2.7 V ≤ VDD ≤ 3.6 V
-
11
15
Slave mode,
1.71 V ≤ VDD ≤ 3.6 V
-
11
11.5
tv(SO)
Data output valid time
th(SO)
Data output hold time
Slave mode
6
-
-
tv(MO)
Data output valid time
Master mode
-
4.5
5
th(MO)
Data output hold time
Master mode
2
-
-
Unit
ns
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
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Electrical characteristics
STM32F479xx
Figure 42. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 43. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
th(SO)
tv(SO)
ta(SO)
MISO
OUTPUT
MSB OUT
BIT6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
tsu(SI)
MOSI
INPUT
th(NSS)
tc(SCK)
MSB IN
BIT 1 IN
LSB IN
ai14135b
144/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Figure 44. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
DS11118 Rev 7
145/220
191
Electrical characteristics
STM32F479xx
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 65 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
output speed set to OSPEEDRy[1:0] = 10
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CK, SD, WS).
Table 65. I2S dynamic characteristics(1)
Symbol
Parameter
Conditions
Min
Max
fMCK
I2S main clock output
-
256x8K
256xFs(2)
fCK
I2S clock frequency
Master data
-
64xFs
Slave data
-
64xFs
30
70
DCK
I2S clock frequency duty cycle Slave receiver
tv(WS)
WS valid time
Master mode
0
5
th(WS)
WS hold time
Master mode
0
-
Slave mode
3.5
-
tsu(WS)
WS setup time
Slave mode
PCM short pulse mode(3)
3.5
-
Slave mode
0.5
-
th(WS)
WS hold time
Slave mode
PCM short pulse mode(3)
1
-
Master receiver
5
-
Slave receiver
1.5
-
Master receiver
5
-
Slave receiver
1.5
-
Slave transmitter (after enable edge)
-
19
Master transmitter (after enable edge)
-
2.50
Slave transmitter (after enable edge)
5
-
Master transmitter (after enable edge)
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Unit
MHz
%
ns
1. Guaranteed based on test during characterization.
2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
Note:
Refer to the I2S section of RM0386 reference manual for more details on the sampling
frequency (FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior, source clock precision
might slightly change the values. The values of these parameters might be slightly impacted
by the source clock precision. DCK depends mainly on the value of ODD bit. The digital
146/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of
(I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition.
Figure 45. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB transmit
th(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
MSB receive
Bitn receive
LSB receive
ai14881b
1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 46. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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191
Electrical characteristics
STM32F479xx
SAI characteristics
Unless otherwise specified, the parameters given in Table 66 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
output speed set to OSPEEDRy[1:0] = 10
capacitive load C=30 pF
measurement points at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics (SCK, SD, WS).
Table 66. SAI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
fMCKL
SAI main clock output
-
256 x 8K
256xFs
fCK
SAI clock frequency(2)
Master data: 32 bits
-
128xFs(3)
Slave data: 32 bits
-
128xFs
Master mode,
2.7 V ≤ VDD ≤ 3.6 V
-
17
Master mode,
1.71 V ≤ VDD ≤ 3.6 V
-
23
tv(FS)
FS valid time
tsu(FS)
FS setup time
Slave mode
10
-
th(FS)
FS hold time
Slave mode
0
-
Master receiver
1
-
Slave receiver
2
-
Master receiver
6
-
Slave receiver
1
-
Slave transmitter (after enable edge),
2.7 V ≤ VDD ≤ 3.6 V
-
14
Slave transmitter (after enable edge),
1.71 V ≤ VDD ≤ 3.6 V
-
23
Slave transmitter (after enable edge)
9
-
Master transmitter (after enable edge),
2.7 V ≤ VDD ≤ 3.6 V
-
20
Master transmitter (after enable edge),
1.71 V ≤ VDD ≤ 3.6 V
-
26
Master transmitter (after enable edge)
10
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
th(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
1. Guaranteed based on test during characterization.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 kHz.
148/220
DS11118 Rev 7
Unit
MHz
ns
STM32F479xx
Electrical characteristics
Figure 47. SAI master timing waveforms
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output)
tv(FS)
th(SD_MT)
tv(SD_MT)
SAI_SD_X
(transmit)
Slot n
tsu(SD_MR)
SAI_SD_X
(receive)
Slot n+2
th(SD_MR)
Slot n
MS32771V1
Figure 48. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X)
SAI_FS_X
(input)
tw(CKL_X)
tsu(FS)
th(FS)
th(SD_ST)
tv(SD_ST)
SAI_SD_X
(transmit)
Slot n
tsu(SD_SR)
SAI_SD_X
(receive)
Slot n+2
th(SD_SR)
Slot n
MS32772V1
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Electrical characteristics
STM32F479xx
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 67. USB OTG full speed startup time
Symbol
Parameter
tSTARTUP(1)
Max
Unit
1
µs
USB OTG full speed transceiver startup time
1. Guaranteed by design.
Table 68. USB OTG full speed DC electrical characteristics
Symbol
Conditions
USB OTG full speed
transceiver operating
voltage
Min.(1) Typ. Max.(1) Unit
-
3.0(2)
-
3.6
VDI(3) Differential input sensitivity
I(USB_FS_DP/DM,
USB_HS_DP/DM)
0.2
-
-
VCM(3)
Differential common mode
range
Includes VDI range
0.8
-
2.5
VSE(3)
Single ended receiver
threshold
-
1.3
-
2.0
VOL
Static output level low
RL of 1.5 kΩ to 3.6 V(4)
-
-
0.3
2.8
-
3.6
17
21
24
0.65
1.1
2.0
VDD
Input
levels
Parameter
Output
levels
RPD
RPU
VOH
Static output level high
RL of 15 kΩ to
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VSS(4)
V
VIN = VDD
kΩ
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
VIN = VSS
1.5
1.8
2.1
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS
0.25
0.37
0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics, which are degraded in the 2.7 to 3.0 V VDD voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.
Note:
150/220
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Figure 49. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
Table 69. USB OTG full speed electrical characteristics(1)
Driver characteristics
Symbol
tr
tf
trfm
Parameter
Rise time(2)
Fall
time(2)
Conditions
Min
Max
CL = 50 pF
4
20
CL = 50 pF
4
20
t r / tf
90
110
%
-
1.3
2.0
V
Driving
high or low
28
44
Rise/ fall time matching
VCRS
Output signal crossover voltage
ZDRV
Output driver impedance(3)
Unit
ns
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 72 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 71
and VDD supply voltage conditions summarized in Table 70, with the following configuration:
output speed set to OSPEEDRy[1:0] = 11, unless otherwise specified
capacitive load C = 20 pF / 15 pF, unless otherwise specified
measurement points at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 70. USB HS DC electrical characteristics
Symbol
Input level
Parameter
VDD
USB OTG HS operating voltage
Min.(1)
Max.(1)
Unit
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
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Electrical characteristics
STM32F479xx
Table 71. USB HS clock timing parameters(1)
Symbol
Parameter
Min
Typ
Max
-
fHCLK value to guarantee proper operation of
USB HS interface
30
-
-
FSTART_8BIT
Frequency (first transition)
54
60
66
FSTEADY
Frequency (steady state) ±500 ppm
59.97
60
60.03
DSTART_8BIT
Duty cycle (first transition)
40
50
60
DSTEADY
Duty cycle (steady state) ±500 ppm
49.975
50
50.025
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition
-
-
1.4
Peripheral
-
-
5.6
Host
-
-
-
-
-
-
tSTART_DEV
tSTART_HOST
Clock startup time after the
de-assertion of SuspendM
8-bit ±10%
8-bit ±10%
PHY preparation time after the first transition
of the input clock
tPREP
Unit
MHz
%
ms
ms
µs
1. Guaranteed by design.
Figure 50. ULPI timing diagram
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
tSC
tHC
tSD
tHD
data In
(8-bit)
tDC
Control out
(ULPI_STP)
tDC
tDD
data out
(8-bit)
ai17361c
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DS11118 Rev 7
STM32F479xx
Electrical characteristics
Table 72. Dynamic characteristics: USB ULPI(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
tSC
Control in (ULPI_DIR, ULPI_NXT)
setup time
-
2.0
-
-
tHC
Control in (ULPI_DIR, ULPI_NXT)
hold time
-
1.5
-
-
tSD
Data in setup time
-
1.0
-
-
tHD
Data in hold time
-
1.0
-
-
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
7.5
9.0
2.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 125°C
-
7.5
12.0
1.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 90°C
-
7.5
11.5
tDC/tDD Data/control output delay
Unit
ns
1. Guaranteed based on test during characterization.
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 73, Table 74 and Table 75 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency and VDD supply voltage conditions summarized in Table 17, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 73 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 51 shows the corresponding timing diagram.
Figure 51. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
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Electrical characteristics
STM32F479xx
Table 73. Dynamics characteristics: Ethernet MAC signals for SMI(1)
Symbol
tMDC
Parameter
MDC cycle time(2.38 MHz)
Min
Typ
Max
400
400
403
Td(MDIO)
Write data valid time
THCLK - 1
THCLK
THCLK + 1.5
tsu(MDIO)
Read data setup time
12.5
-
-
th(MDIO)
Read data hold time
0
-
-
1. Guaranteed based on test during characterization.
Table 74 gives the list of Ethernet MAC signals for the RMII and Figure 52 shows the
corresponding timing diagram.
Figure 52. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667
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DS11118 Rev 7
Unit
ns
STM32F479xx
Electrical characteristics
Table 74. Dynamics characteristics: Ethernet MAC signals for RMII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2.5
-
-
tih(RXD)
Receive data hold time
2.0
-
-
tsu(CRS)
Carrier sense setup time
0.5
-
-
tih(CRS)
Carrier sense hold time
1.5
-
-
td(TXEN)
Transmit enable valid delay time
5.5
6.5
11
td(TXD)
Transmit data valid delay time
6.0
6.5
11
Unit
ns
1. Guaranteed based on test during characterization.
Table 75 gives the list of Ethernet MAC signals for MII and Figure 52 shows the
corresponding timing diagram.
Figure 53. Ethernet MII timing diagram
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668
Table 75. Dynamics characteristics: Ethernet MAC signals for MII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
1
-
-
tih(RXD)
Receive data hold time
3
-
-
tsu(DV)
Data valid setup time
0
-
-
tih(DV)
Data valid hold time
2.5
-
-
tsu(ER)
Error setup time
0
-
-
tih(ER)
Error hold time
2
-
-
td(TXEN)
Transmit enable valid delay time
0
7
13
td(TXD)
Transmit data valid delay time
0
7
13
Unit
ns
1. Guaranteed based on test during characterization.
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Electrical characteristics
STM32F479xx
CAN (controller area network) interface
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CANx_TX and CANx_RX).
5.3.24
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 76. ADC characteristics
Symbol
Min
Typ
Max
Power supply
1.7(1)
-
3.6
VREF+
Positive reference voltage
1.7(1)
-
VDDA
VREF-
Negative reference voltage
-
0
-
0.6
15
18
VDDA = 2.4 to 3.6 V
0.6
30
36
fADC = 30 MHz,
12-bit resolution
-
-
1764
kHz
-
-
-
17
1/fADC
-
0
(VSSA or VREFtied to ground)
-
VREF+
V
Details in Equation 1
-
-
50
k
Sampling switch resistance
-
-
-
6
k
Internal sample and hold
capacitor
-
-
4
7
pF
-
-
0.100
µs
1/fADC
VDDA
fADC
fTRIG(2)
VAIN
RAIN(2)
RADC
(2)(4)
CADC(2)
Parameter
ADC clock frequency
External trigger frequency
Conversion voltage range(3)
External input impedance
Conditions
VDDA VREF+ < 1.2 V
VDDA =
1.7(1)
to 2.4 V
Unit
V
MHz
tlat(2)
Injection trigger conversion
latency
fADC = 30 MHz
-
-
-
3(5)
tlatr(2)
Regular trigger conversion
latency
fADC = 30 MHz
-
-
0.067
µs
-
-
2(5)
1/fADC
tS(2)
Sampling time
fADC = 30 MHz
0.100
-
16
µs
-
3
-
480
1/fADC
tSTAB(2)
Power-up time
-
-
2
3
µs
156/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Table 76. ADC characteristics (continued)
Symbol
tCONV(2)
Parameter
Total conversion time
(including sampling time)
Conditions
Min
Typ
Max
fADC = 30 MHz
12-bit resolution
0.50
-
16.40
fADC = 30 MHz
10-bit resolution
0.43
-
16.34
fADC = 30 MHz
8-bit resolution
0.37
-
16.27
fADC = 30 MHz
6-bit resolution
0.30
-
16.20
Unit
µs
9 to 492
1/fADC
(tS for sampling +n-bit resolution for successive approximation)
Sampling rate
fS(2)
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
Single ADC
-
-
2
12-bit resolution
Interleave Dual ADC
mode
-
-
3.75
12-bit resolution
Interleave Triple ADC
mode
-
-
6
Msps
IVREF+(2)
ADC VREF
DC current consumption in
conversion mode
-
-
300
500
µA
IVDDA(2)
ADC VDDA
DC current consumption in
conversion mode
-
-
1.6
1.8
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Based on test during characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 76.
Equation 1: RAIN max formula
k – 0.5
R AIN = ------------------------------------------------------------------------- – R ADC
N+2
f ADC C ADC ln 2
The above formula (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
DS11118 Rev 7
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191
Electrical characteristics
STM32F479xx
Table 77. ADC static accuracy at fADC = 18 MHz(1)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA VREF < 1.2 V
Typ
Max(2)
±3
±4
±2
±3
±1
±3
±1
±2
±2
±3
Unit
LSB
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
Table 78. ADC static accuracy at fADC = 30 MHz(1)
a
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC = 30 MHz,
RAIN < 10 k,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA VREF < 1.2 V
Typ
Max(2)
±2
±5
±1.5
±2.5
±1.5
±3
±1
±2
±1.5
±3
Unit
LSB
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
Table 79. ADC static accuracy at fADC = 36 MHz(1)
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC =36 MHz,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA VREF < 1.2 V
Typ
Max(2)
±4
±7
±2
±3
±3
±6
±2
±3
±3
±6
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
158/220
DS11118 Rev 7
Unit
LSB
STM32F479xx
Electrical characteristics
Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to-noise and distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.3
10.4
-
bits
64
64.2
-
64
65
-
− 67
− 72
-
dB
1. Guaranteed based on test during characterization.
Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to noise and distortion ratio
SNR
Signal-to noise ratio
THD
Total harmonic distortion
fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.6
10.8
-
bits
66
67
-
64
68
-
− 70
− 72
-
dB
1. Guaranteed based on test during characterization.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in
Section 5.3.20 does not affect the ADC accuracy.
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191
Electrical characteristics
STM32F479xx
Figure 54. ADC accuracy characteristics
[1LSB IDEAL =
V REF+
4096
(or
V DDA
4096
depending on package)]
EG
4095
4094
4093
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
1L SBIDEAL
1
0
1
2
3
456
7
V SSA
4093 4094 4095 4096
VDDA
ai14395c
1. See also Table 78.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 55. Typical connection diagram using the ADC
STM32F
VDD
RAIN(1) AINx
VAIN
Cparasitic
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
VT
0.6 V
IL±1 μA
12-bit
converter
C ADC(1)
ai17534
1. Refer to Table 76 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
160/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 56 or Figure 57,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F
VREF+(1)
1 μF // 10 nF
VDDA
1 μF // 10 nF
VSSA/VREF+(1)
MS38278V1
1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP176 and LQFP208. When VREF+ and VREF– are not available, they are internally connected to VDDA
and VSSA.
Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA(1)
1 μF // 10 nF
VREF-/VDDA(1)
MS38279V1
1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP176 and LQFP208. When VREF+ and VREF– are not available, they are internally connected to VDDA
and VSSA.
DS11118 Rev 7
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191
Electrical characteristics
5.3.25
STM32F479xx
Temperature sensor characteristics
Table 82. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VSENSE linearity with temperature
-
1
2
°C
Average slope
-
2.5
-
mV/°C
Voltage at 25 °C
-
0.76
-
V
tSTART(2)
Startup time
-
6
10
TS_temp(2)
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
-
TL(1)
Avg_Slope
(1)
V25(1)
µs
1. Based on test during characterization.
2. Guaranteed by design.
Table 83. Temperature sensor calibration values
Symbol
Parameter
Memory address
TS_CAL1
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V
0x1FFF 7A2E - 0x1FFF 7A2F
5.3.26
VBAT monitoring characteristics
Table 84. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
K
R
Resistor bridge for VBAT
-
50
-
Q
Ratio on VBAT measurement
-
4
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
5
-
-
µs
Er(1)
TS_vbat(2)(2)
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
5.3.27
Reference voltage
The parameters given in Table 85 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 85. internal reference voltage
Symbol
VREFINT
TS_vrefint(1)
VRERINT_s(2)
162/220
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.18
1.21
1.24
V
10
-
-
µs
-
3
5
mV
ADC sampling time when reading the
internal reference voltage
Internal reference voltage spread over the
temperature range
VDD = 3V 10mV
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Table 85. internal reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TCoeff(2)
Temperature coefficient
-
30
50
ppm/°C
tSTART(2)
Startup time
-
6
10
µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design
Table 86. Internal reference voltage calibration values
Symbol
Parameter
VREFIN_CAL
5.3.28
Memory address
Raw data acquired at temperature of 30 °C VDDA = 3.3 V
0x1FFF 7A2A - 0x1FFF 7A2B
DAC electrical characteristics
Table 87. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
-
VDDA
Analog supply voltage
1.7(1)
-
3.6
V
VREF+
Reference supply voltage
1.7(1)
-
3.6
V
VSSA
Ground
0
-
0
V
-
RLOAD(2)
Resistive load with buffer ON
5
-
-
k
-
RO(2)
Impedance output with buffer
OFF
-
-
15
k
When the buffer is OFF, the Minimum
resistive load between DAC_OUT and
VSS to have a 1% accuracy is 1.5 M
Capacitive load
-
-
50
pF
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
DAC_OUT Lower DAC_OUT voltage
with buffer ON
min(2)
0.2
-
-
V
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
-
-
VDDA −
0.2
V
DAC_OUT Lower DAC_OUT voltage
with buffer OFF
min(2)
-
0.5
-
mV
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
-
-
VREF+ −
1LSB
V
-
170
240
CLOAD(2)
IVREF+(4)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
µA
-
50
75
DS11118 Rev 7
VREF+ VDDA
It gives the maximum output excursion of
the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
It gives the maximum output excursion of
the DAC.
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
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Electrical characteristics
STM32F479xx
Table 87. DAC characteristics (continued)
Symbol
Min
Typ
Max
Unit
Comments
-
280
380
µA
With no load, middle code (0x800) on the
inputs
-
475
625
µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
±0.5
LSB Given for the DAC in 10-bit configuration.
-
-
±2
LSB Given for the DAC in 12-bit configuration.
-
-
±1
LSB Given for the DAC in 10-bit configuration.
INL(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-
-
±4
LSB Given for the DAC in 12-bit configuration.
-
-
±10
mV Given for the DAC in 12-bit configuration
Offset(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
-
-
±3
LSB
Given for the DAC in 10-bit at VREF+ =
3.6 V
-
-
±12
LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
Gain error
-
-
±0.5
%
Given for the DAC in 12-bit configuration
-
3
6
µs
CLOAD 50 pF,
RLOAD 5 k
IDDA(4)
DNL(4)
Gain
error(4)
Parameter
DAC DC VDDA current
consumption in quiescent
mode(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
(4)
tSETTLING
highest input codes when
DAC_OUT reaches final
value ±4LSB
THD(4)
Total Harmonic Distortion
Buffer ON
-
-
-
dB
CLOAD 50 pF,
RLOAD 5 k
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-
-
1
MS/s
CLOAD 50 pF,
RLOAD 5 k
Wakeup time from off state
tWAKEUP(4) (Setting the ENx bit in the
DAC Control register)
-
6.5
10
µs
CLOAD 50 pF, RLOAD 5 k
input code between lowest and highest
possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC
measurement)
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed based on test during characterization.
164/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Figure 58. 12-bit buffered/non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
DAC_OUTx
12-bit
digital to
analog
converter
CL
ai17157V2
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
5.3.29
FMC characteristics
Unless otherwise specified, the parameters given in Tables 88 through 101 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.
Asynchronous waveforms and timings
Figures 59 through 62 represent asynchronous waveforms, and Tables 88 through 95
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capacitive load CL = 30 pF
DS11118 Rev 7
165/220
191
Electrical characteristics
STM32F479xx
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE)
FMC_A[25:0]
t h(A_NOE)
Address
tv(BL_NE)
t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE)
th(Data_NOE)
t su(Data_NE)
Data
FMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FMC_NADV
(1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
166/220
DS11118 Rev 7
STM32F479xx
Electrical characteristics
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings(1)
Symbol
Min
Max
2THCLK − 0.5
2 THCLK+0.5
0
1
2THCLK
2THCLK+ 0.5
FMC_NOE high to FMC_NE high hold time
0
-
FMC_NEx low to FMC_A valid
-
2
th(A_NOE)
Address hold time after FMC_NOE high
0
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
2
th(BL_NOE)
FMC_BL hold time after FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK + 2.5
-
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
tsu(Data_NOE)
Data to FMC_NOEx high setup time
THCLK +2
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
FMC_NADV low time
-
THCLK +1
tw(NADV)
Unit
ns
1. Based on test during characterization.
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
timings(1)
Symbol
Min
Max
FMC_NE low time
7THCLK+0.5
7THCLK+1
FMC_NWE low time
5THCLK − 1.5
5THCLK +2
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5THCLK+1.5
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4THCLK+1
-
tw(NE)
tw(NOE)
Parameter
Unit
ns
1. Based on test during characterization.
DS11118 Rev 7
167/220
191
Electrical characteristics
STM32F479xx
Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FMC_NWE
tv(A_NE)
FMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FMC_D[15:0]
t v(NADV_NE)
FMC_NADV (1)
tw(NADV)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
th(A_NWE)
Address hold time after FMC_NWE high
tv(BL_NE)
FMC_NEx low to FMC_BL valid
Max
3THCLK
3THCLK+1
THCLK − 0.5
THCLK+ 0.5
THCLK
THCLK+ 0.5
THCLK +1.5
-
-
0
THCLK+0.5
-
-
1.5
THCLK+0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
tv(Data_NE)
Data to FMC_NEx low to Data valid
-
THCLK+ 2
th(Data_NWE)
Data hold time after FMC_NWE high
THCLK+0.5
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0.5
FMC_NADV low time
-
THCLK+ 0.5
tw(NADV)
1. Based on test during characterization.
168/220
Min
DS11118 Rev 7
Unit
ns
STM32F479xx
Electrical characteristics
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
timings(1)
Symbol
tw(NE)
tw(NWE)
Parameter
Min
Max
FMC_NE low time
8THCLK+1
8THCLK+2
FMC_NWE low time
6THCLK − 1
6THCLK+2
6THCLK+1.5
-
4THCLK+1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
Unit
ns
1. Based on test during characterization.
Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FMC_ NE
tv(NOE_NE)
t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
th(A_NOE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NOE)
FMC_ NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
FMC_ AD[15:0]
tsu(Data_NOE)
th(Data_NOE)
Data
Address
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS11118 Rev 7
169/220
191
Electrical characteristics
STM32F479xx
Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
tw(NE)
tv(NOE_NE)
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
3THCLK − 1
3THCLK+0.5
2THCLK − 0.5
2THCLK
THCLK − 1
THCLK+1
FMC_NOE high to FMC_NE high hold time
1
-
FMC_NEx low to FMC_A valid
-
2
FMC_NEx low to FMC_NADV low
0
2
THCLK − 0.5
THCLK+0.5
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
FMC_NADV low time
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high)
0
-
th(A_NOE)
Address hold time after FMC_NOE high
THCLK − 0.5
-
th(BL_NOE)
FMC_BL time after FMC_NOE high
0
-
FMC_NEx low to FMC_BL valid
-
2
tv(BL_NE)
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK+1.5
-
tsu(Data_NOE)
Data to FMC_NOE high setup time
THCLK+1
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
Unit
ns
1. Based on test during characterization.
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol
tw(NE)
tw(NOE)
Parameter
Min
Max
FMC_NE low time
8THCLK+0.5
8THCLK+2
FMC_NWE low time
5THCLK − 1
5THCLK +1.5
5THCLK +1.5
-
4THCLK+1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
1. Based on test during characterization.
170/220
DS11118 Rev 7
Unit
ns
STM32F479xx
Electrical characteristics
Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FMC_NWE
th(A_NWE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NWE)
FMC_ NBL[1:0]
NBL
t v(A_NE)
t v(Data_NADV)
Address
FMC_ AD[15:0]
th(Data_NWE)
Data
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 94. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
Min
Max
4THCLK
4THCLK+0.5
THCLK − 1
THCLK+0.5
FMC_NWE low time
2THCLK
2THCLK+0.5
FMC_NWE high to FMC_NE high hold time
THCLK
-
-
0
0.5
1
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV)
FMC_NADV low time
FMC_AD (address) valid hold time
th(AD_NADV)
after FMC_NADV high
Unit
THCLK − 0.5 THCLK+ 0.5
THCLK − 2
-
th(A_NWE)
Address hold time after FMC_NWE high
THCLK
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
THCLK − 2
-
-
2
-
THCLK +1.5
THCLK +0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
tv(Data_NADV) FMC_NADV high to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
ns
1. Based on test during characterization.
DS11118 Rev 7
171/220
191
Electrical characteristics
STM32F479xx
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
Symbol
tw(NE)
tw(NWE)
Parameter
Min
Max
FMC_NE low time
9THCLK
9THCLK+0.5
FMC_NWE low time
7THCLK
7THCLK+2
6THCLK+1.5
-
4THCLK–1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
Unit
ns
1. Based on test during characterization.
Synchronous waveforms and timings
Figures 63 through 66 represent synchronous waveforms and Table 96 through Table 99
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
BurstAccessMode = FMC_BurstAccessMode_Enable;
MemoryType = FMC_MemoryType_CRAM;
WriteBurst = FMC_WriteBurst_Enable;
CLKDivision = 1;
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period:
172/220
For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
For 1.71 V≤ VDD
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