STM32C562CEU6

STM32C562xx Datasheet Arm® Cortex®-M33 32-bit MCU with FPU, 144 MHz, 593 CoreMark®, 512‑Kbyte dual‑bank flash memory, 128-Kbyte RAM, cryptography Features Includes ST state-of-the-art patented technology. LQFP32 (7 x 7 mm) LQFP48 (7 x 7 mm) LQFP64 (10 x 10 mm) LQFP80 (12 x 12 mm) LQFP100 (14 x 14 mm) UFQFPN32 (5 x 5 mm) UFQFPN48 (7 x 7 mm) Core • 32-bit Arm® Cortex®-M33 CPU with FPU, frequency up to 144 MHz, MPU, and DSP instructions Benchmarks • Product status STM32C562xx STM32C562CE, STM32C562KE, STM32C562ME, STM32C562RE, STM32C562VE 593 CoreMark® (4.12 CoreMark®/MHz) ART Accelerator • 8-Kbyte instruction cache enables 0-wait-state execution from flash memory at the CPU's maximum speed Memories • • • • 512‑Kbyte flash memory with ECC, 2 banks read-while-write 128-Kbyte SRAM including 64-Kbyte with ECC 64-Kbyte flash memory area for software EEPROM emulation 4.5-Kbyte OTP (one-time programmable) Clock, reset, and supply management • • • • • • 2.7 V to 3.6 V application supply and I/O POR, PDR, and PVD Embedded regulator (LDO) Internal oscillators: 144 MHz HSI (with +/- 1% accuracy over temperature range [-20 °C : 130°C]), 160/144/100 MHz PSI, 32 kHz LSI External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE Low-power modes: Sleep, Stop, and Standby DMA controller to offload the CPU • 2 x LPDMA with 12 channels (8 + 4) Analog • • • 2 × 12-bit ADC (19 external channels and 2 internal), up to 2.25 MSPS, or up to 4.5 MSPS in dual interleaved mode 1 × 12-bit DAC (with output buffer) 1 × comparator (with configurable set of inputs) Up to 15 timers • 9 × 16-bit (including 2 × 16-bit advanced motor control, 1 × low-power 16-bit timer available in Stop mode) and 2 × 32-bit timers DS14927 - Rev 1 - February 2026 For further information, contact your local STMicroelectronics sales office. www.st.com STM32C562xx • • • 2 × watchdogs 1 × SysTick timer RTC with hardware calendar, alarms, and calibration Communication interfaces • • • • • • Up to 2 × I2C FM + interfaces (SMBus/PMBus) 1 × I3C Up to 3 × USARTs (ISO7816 interface, LIN, IrDA, modem control, SPI mode), 2 × UARTs, and 1 × LPUART Up to 3 × SPIs with muxed with full‑duplex I2S for audio class accuracy via external clock and up to 3 × additional SPIs from 3 × USARTs when configured in synchronous mode 1 × FDCAN 1 × USB 2.0 full-speed host and device Low-power modes • Sleep, Stop, and Standby modes Up to 86 I/O ports with interrupt capability HASH (SHA-1, SHA-224, SHA-256), HMAC AES accelerator • 128-bit and 256-bit key length Mathematical coprocessor • CORDIC for trigonometric functions acceleration 1 × True random number generator Bootloader support on USART, FDCAN, USB, and SPI interfaces Flexible life-cycle scheme with RDP and password-protected regression 96-bit unique ID All packages are ECOPACK2 compliant. DS14927 - Rev 1 page 2/130 STM32C562xx Introduction 1 Introduction This document provides information on STM32C562xx devices, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging and ordering information. For information on the Arm® Cortex®-M33 core, refer to the Arm® Cortex®-M33 Processor Technical Reference Manual, available from the www.arm.com website. Note: DS14927 - Rev 1 Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. page 3/130 STM32C562xx Description 2 Description The STM32C562xx devices are general purpose microcontrollers family (STM32C5 Series) based on the high‑performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 144 MHz. The Cortex®-M33 core features a single‑precision floating‑point unit (FPU), that supports all the Arm® single‑precision data‑processing instructions and all the data types. The Cortex®-M33 core also implements a full set of digital signal processing (DSP) instructions and a memory protection unit (MPU) that enhances the application security. The devices embed high‑speed memories (512‑Kbyte flash memory and 128‑Kbyte SRAM), and an extensive range of enhanced I/Os, peripherals connected to three APB buses, three AHB buses, and a 32‑bit multi‑AHB bus matrix. The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, and hide protection areas. The devices embed several peripherals reinforcing security: • • • HASH hardware accelerator True random number generator AES coprocessor The devices offer two 12‑bit ADCs, one DAC channel, one comparator, a low‑power RTC, two 32‑bit general‑purpose timers, two 16‑bit PWM timers dedicated to motor control, four 16‑bit general‑purpose timers, two 16‑bit basic timers, and one 16‑bit low‑power timer. The devices also feature standard and advanced communication interfaces such as: • Two I2Cs • • • • • One I3C shared with I2C Three SPIs with muxed full-duplex I2S Three USARTs, two UARTs, and one low‑power UART One FDCAN One USB full‑speed The devices operate in the –40 to +125 °C (+140 °C junction) temperature ranges from a 2.7 to 3.6 V power supply. A comprehensive set of power‑saving modes allows the design of low‑power applications. The devices offer multiple packages from 32 to 100 pins. See Table 1 for the list of peripherals available for each part number. Flash memory (Kbytes) SRAM (Kbytes) STM32C562VET 128 (including 64 with ECC) 8 Flash memory area for EEPROM Emulation (Kbytes) 64 One-time-programmable (Kbytes) 4.5 DS14927 - Rev 1 STM32C562MET 512 ICACHE (Kbytes) Timers STM32C562RET STM32C562CEU STM32C562CET STM32C562KEU Peripherals STM32C562KET Table 1. Device features and peripheral counts General purpose 6 Advanced‑control 2 Basic 2 page 4/130 STM32C562xx Timers Low‑power 1 SysTick 1 Window watchdog STM32C562VET 3 (3) I2C 2 I3C 1 USART 3 UART 2 LPUART 1 USB 1 FDCAN 1 TRACE No Yes CORDIC Yes RTC Yes (without LSE) Yes 2 3 Tamper pins True random number generator (RNG) Yes HASH Yes AES Yes GPIOs 25 Wake-up pins 27 3 12-bit ADC channels External 9 10 Internal 2 2 2 38 52 66 86 4 6 6 7 11 17 18 19 2 2 2 LQFP80 LQFP100 2 12-bit DAC channels 1 Analog comparator 1 Maximum CPU frequency (MHz) 144 Operating voltage 2.7 V - 3.6 V Operating temperature Packages STM32C562MET 2 SPI (with I2S) Communication interfaces STM32C562RET STM32C562CEU STM32C562CET STM32C562KET Peripherals STM32C562KEU Description Junction temperature range: −40 to +140 °C LQFP32 UFQFPN32 LQFP48 UFQFPN48 LQFP64 Figure 1 shows the general block diagram of the device family. DS14927 - Rev 1 page 5/130 STM32C562xx Description Figure 1. STM32C562xx block diagram MPU ETM NVIC Arm Cortex-M33 C-BUS 144 MHz FPU S-BUS RNG AES Flash memory (up to 512 Kbytes) HASH @VDDA AHB bus-matrix SRAM1 (64 Kbytes) LPDMA1 LPDMA2 ITF RAMCFG ITF CRC VDD @VDD PB[15:0] GPIO port B PC[15:0] GPIO port C PD[15:0] GPIO port D PE[15:0] GPIO port E Reset TIM1/PWM 3 compl. channels (TIM8_CH[1:3]N), 6 channels (TIM8_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM8/PWM VDD, VSS, NRST IWDG PSI XTAL OSC 4- 50 MHz Reset and clock control PCLKx HCLKx OSC_IN OSC_OUT Standby interface CRS TIM2 32b TIM5 32b WKUPx (x=1 to 7) 4 channels, ETR as AF 4 channels, ETR as AF 16b EXTI 16b 1 channel, 1 compl. channel, BKIN as AF TIM16 16b 1 channel, 1 compl. channel, BKIN as AF TIM17 16b AHB/APB1 APB2 144 MHz TIM15 AHB/APB2 smcard USART1 irDA WWDG SPI1/I2S1 IWDG APB1 144 MHz (max) 16b 2 channels, 1 compl. channel, BKIN as AF MOSI, MISO, SCK, NSS as AF VDD = 2.7 to 3.6 V VSS PVD Int LSI FCLK 3 compl. channels (TIM1_CH[1:3]N), 6 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF RX, TX, CK,CTS, RTS as AF @VDD Supply supervision GPIO port H PH[15:0] 19xIN @VDD Power management HSI AHB3 144 MHz AHB1 144 MHz GPIO port A @VDDA ADC1 Voltage regulator LDO EXT IT. WKP PA[15:0] DAC1_OUT1 ADC2 AHB2 144 MHz CORDIC 16 AF DAC1 SRAM2 (64 Kbytes) smcard USART2 irDA RX, TX, CK, CTS, RTS as AF smcard USART3 irDA RX, TX, CK, CTS, RTS as AF UART4 RX, TX, CTS, RTS as AF UART5 RX, TX, CTS, RTS as AF SPI2/I2S2 MOSI, MISO, SCK, NSS as AF SPI3/I2S3 MOSI, MISO, SCK, NSS as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF FIFO TRACECLK, TRACED[3:0] JTAG/ SW ICACHE (8 Kbytes) NJTRST, JTDI, JTCK/SWCLK, JTMS/SWDIO, JTDO TX, RX as AF TIM6 16b AHB/APB3 TIM7 16b Temperature monitoring TAMP_IN[1:3] IN1, IN2, CH1, CH2, ETR as AF RX, TX, CTS, RTS_DE as AF @VRTC XTAL 32k RTC TAMP LPTIM1 SBS APB3 144 MHz RTC_OUT1, RTC_OUT2, RTC_REFIN, RTC_TS VDDUSB power domain FDCAN1 TIM12 16b I3C1 2 channels, ETR as AF SCL, SDA VDDA power domain @VDDA ITF COMP1 INPx, INMx, OUTx VDD power domain DT76077V1 USB FS FIFO DP DM PHY @VDDUSB LPUART1 VRTC power domain DS14927 - Rev 1 page 6/130 STM32C562xx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M33 with FPU The Cortex®-M33 is a highly energy-efficient processor designed for microcontrollers and deeply embedded applications, especially those requiring efficient security. The Cortex® processor delivers a high‑computational performance with low‑power consumption and an advanced response to interrupts. It features: • • Memory protection units (MPUs) supporting eight regions Floating-point arithmetic functionality with support for single-precision arithmetic The processor supports a set of DSP instructions that allows an efficient signal processing and a complex algorithm execution. The Cortex®-M33 processor features: • • System AHB bus: The system AHB (S-AHB) bus interface is used for any instruction fetch and data access to the memory‑mapped SRAM, peripheral, or Vendor_SYS regions of the Armv8‑M memory map. Code AHB bus: The code AHB (C-AHB) bus interface is used for any instruction fetch and data access to the code region of the Armv8‑M memory map. Refer to Figure 1. STM32C562xx block diagram for more details. DS14927 - Rev 1 page 7/130 STM32C562xx Functional overview 3.2 Instruction cache (ICACHE) The instruction cache (ICACHE) is introduced on the C-AHB code bus of the Cortex®‑M33 processor to improve performance when fetching instructions and data from internal memories. Some specific features, like hit‑under‑miss and critical-word‑first refill policy, allow close to zero‑wait‑state performance in most use cases. The ICACHE main features are: • Bus interface: One 32-bit AHB slave port, the execution port (input from Cortex®‑M33 C‑AHB code interface) One 128-bit AHB master port: master1 port (output to Fast bus of the main AHB bus matrix) One 32-bit AHB slave port for control (input from AHB peripherals interconnect, for ICACHE registers access) Cache access: – – – • – – • Zero wait-state on hits Hit-under-miss capability: ability to serve processor requests (access to cached data) during an ongoing line refill due to a previous cache miss – Optimal cache line refill thanks to WRAPw bursts of the size of the cache line (32-bit word size, w, aligned on cache line size) – n-way set-associative default configuration with the possibility to configure as 1‑way, meaning direct‑mapped cache, for applications needing a very‑low‑power consumption profile Memory address remap: – • Possibility to remap input addresses falling into up to four memory regions (used to remap aliased code in SRAM memories to the code region, for execution from the C‑AHB code interface) Replacement and refill: – • • pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree), algorithm with the best complexity/performance balance – Critical-word-first refill policy, minimizing processor stalls – Possibility to configure burst type of AHB memory transaction for remapped regions: INCRw or WRAPw (size w aligned on cache line size) Performance counters: The ICACHE implements two performance counters: – Hit monitor counter (32-bit) – Miss monitor counter (16-bit) Error management: – • Possibility to detect an unexpected cacheable write access, to flag an error, and optionally to raise an interrupt Maintenance operation: – 3.3 Cache invalidate: full cache invalidation, fast command, noninterruptible Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to the memory. It also prevents one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to eight protected areas. The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. An RTOS (real-time operating system) usually manages the MPU. If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed. 3.4 3.4.1 Memories Embedded flash memory The devices feature 512 Kbytes embedded flash memory that is available for storing programs and data. DS14927 - Rev 1 page 8/130 STM32C562xx Functional overview The flash memory interface features: • • Dual-bank operating modes Read-while-write (RWW) This allows a read operation to be performed from one bank while an erase or program operation is performed to the other bank. Each bank contains 32 pages of 8 Kbytes. The flash memory embeds 4.5-Kbyte OTP (one-time programmable) for user data. Enhanced flash memory protection mechanisms are available. These mechanisms can be activated by option bytes: • • • RDP states for protecting memory content from debug access Page group write-protection (WRPG) One hide protection area (HDP) per bank that provides temporal isolation for startup code The whole nonvolatile memory embeds the error correction code (ECC) feature supporting: • • • Single-error detection and correction Double-error detection ECC fail address report 3.4.1.1 User data flash memory The device features 64 Kbytes of user data flash memory split in two banks of 16 × 2‑Kbyte sectors offering perfect space for storing EEPROM emulation data. 3.4.2 Embedded SRAMs Two SRAMs are embedded in the STM32C562xx devices. These SRAMs are made of several blocks that can be powered down in Stop mode to reduce consumption: • • 3.5 SRAM1: 64 Kbytes SRAM2: 64 Kbytes with optional ECC Boot modes At startup, the BOOT0 pin allows the system to boot either from the user Flash or from the bootloader. When boot from user Flash is selected, BOOTADD defines the boot address. This address can be locked thanks to BOOT_LOCK. The embedded bootloader is located in the system memory, programmed by STMicroelectronics during production. It is used to reprogram the flash memory by using USART, SPI, FDCAN, or USB in device mode through the device firmware upgrade (DFU). Refer to the application note STM32 microcontroller system memory boot mode (AN2606) for more details. 3.6 Power supply management The power controller (PWR) main features are: DS14927 - Rev 1 • Power supplies and supply domains • – Core domain (VCORE) – VDD domain – RTC domain – Analog domain (VDDA) System supply voltage regulation • – Voltage regulator (LDO) Power supply supervision • – POR/PDR monitor – PVD monitor Power management • – Low-power modes Privileged protection page 9/130 STM32C562xx Functional overview 3.6.1 Power supply schemes The devices require a 2.7 V to 3.6 V VDD operating voltage supply. • • • VDD = 2.7 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator, and the system analog such as reset, power management, and internal clocks. It is provided externally through the VDD pins. VDDA = VDD VDDA is the analog power supply for ADCs, DACs, and comparator. VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DAC. VREF+ can be grounded when ADCs and DAC are not active. VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively. The STM32C562xx devices embed a LDO regulator to provide the VCORE supply for digital peripherals, SRAM1, SRAM2, and embedded flash memory. The LDO generates this voltage on VCAP pin connected to an external capacitor of 2.2 μF typical. The LDO regulator can operate in Stop modes where it may provide two different voltages (voltage scaling). Figure 2. STM32C562xx power supply overview VDDA domain A/D converters D/A converter Comparator USB transceiver VDD domain VDDIO I/O ring Core domain Reset block Internal RC oscillators VSS VDD Core Standby circuitry (Wake-up logic, IWDG) SRAM1 SRAM2 Voltage regulator VCORE VCAP Digital peripherals LDO regulator Flash memory DS14927 - Rev 1 DT74255V2 RTC domain (VRTC) LSE crystal 32 kHz oscillator Backup registers RCC_RTC register RTC TAMP page 10/130 STM32C562xx Functional overview 3.6.2 Power supply supervisor The devices have an integrated power‑on reset (POR) / power‑down reset (PDR) circuitry: • Power-on reset (POR) The POR supervisor monitors the VDD power supply and compares it to a fixed threshold. The devices remain in reset mode when VDD is below this threshold. • Power-down reset (PDR) The PDR supervisor monitors the VDD power supply. A reset is generated when VDD drops below a fixed threshold. Programmable voltage detector (PVD) The PVD monitors the VDD power supply by comparing it with a threshold fixed by hardware. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the device into a safe state. The software enables the PVD. • 3.6.3 Low-power modes By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low‑power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PSI, the HSI, and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). The system clock when exiting Stop mode is HSI 144 MHz. Stop 0 mode maintains the regulator output at a nominal voltage of 1.2 V. Stop 1 mode reduces power consumption by lowering VCORE to 0.95 V, which results in a longer wake-up time and fewer wake-up sources compared to Stop 0 mode. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The PSI, the HSI, and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The state of each I/O during Standby mode can be retained. After entering Standby mode, SRAMs and register contents are lost except for registers in the RTC domain and Standby circuitry. The device exits Standby mode in the following cases: – – – – An external reset with NRST pin An IWDG reset A WKUP pin event (configurable rising or falling edge) An RTC event occurs (alarm, periodic wake-up, timestamp), or in a tamper detection. The tamper detection can be raised either due to external pins or due to an internal failure detection. The system clock after wake-up is HSI at 144 MHz. 3.6.4 Reset mode To improve the consumption under reset, the I/O state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). 3.7 Peripheral interconnect matrix Several peripherals have direct connections between them. These connections allow autonomous communication between them and support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency. Depending on the peripherals, these interconnections can operate in Run and Sleep modes. DS14927 - Rev 1 page 11/130 STM32C562xx Functional overview 3.8 Reset and clock controller (RCC) The clock controller distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low‑power modes and ensures the clock robustness. It features: • • • • Clock prescaler: in order to get the best trade‑off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Clock security system: clock sources can be changed safely on the fly in Run mode through a configuration register. Clock management: in order to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals, or memory. System clock source: four different clock sources can be used to drive the master clock SYSCLK: – • 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE). The HSE can also be configured in bypass mode for an external clock. – 144 MHz or 48 MHz on high-speed internal RC oscillator (HSI), trimmable by software – 144 MHz programmable-speed internal oscillator (PSI) Auxiliary clock source: two ultra‑low‑power clock sources that can be used to drive the real-time clock: – • • • • 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. Peripheral clock sources: several peripherals have their own independent clock whatever the system clock. Two dividers, each with a large scale of configurable division factors, can generate independent clocks for the ADCS, USARTx, UARTx, SPIx, I2Cx, I3C1, and FDCANx. Startup clock: after reset, the microcontroller restarts by default with an internal 144 MHz clock (HSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): this feature can be enabled by software. If an HSE clock failure occurs, the master clock automatically switches to HSI and a software interrupt is generated if enabled. LSE failure can also be detected and generates an interrupt. Clock-out capability: – – MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application. LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes. Several prescalers allow AHB and APB frequencies configuration. The maximum frequency of the AHB and the APB clock domains is 144 MHz. 3.9 Clock recovery system (CRS) The devices embed a special block that allows automatic trimming of the internal 144 MHz oscillator to guarantee its optimal accuracy over the whole device‑operational range. This automatic trimming is based on the external synchronization signal. This signal is either derived from USB_SOF signalization, from an LSE oscillator, from an external signal on the CRS_SYNC pin or generated by user software. For faster lock-in during startup, automatic‑trimming and manual‑trimming action can be combined. 3.10 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push‑pull or open‑drain), as input (with or without pull‑up or pull‑down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. After reset, all GPIOs are in Analog mode to reduce power consumption. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.11 Multi-AHB bus matrix A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, LPDMA1, LPDMA2) and the slave peripherals (flash memory, SRAMs, AHB, and APB). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DS14927 - Rev 1 page 12/130 STM32C562xx Functional overview 3.12 Low-power direct memory access controller (LPDMA) The low-power direct memory access (LPDMA) controller is a bus master and system peripheral. The LPDMA is used to perform programmable data transfers between memory‑mapped peripherals and/or memories via linked‑lists, under the control of an off‑loaded CPU. The LPDMA main features are: • • Single bidirectional AHB master Memory-mapped data transfers from a source to a destination: • – Peripheral to memory – Memory to peripheral – Memory to memory – Peripheral to peripheral Transfers arbitration based on a 4-grade programmed priority at the channel level: – – • • One high-priority traffic class for time-sensitive channels (queue 3) Three low-priority traffic classes with a weighted round‑robin allocation for non‑time‑sensitive channels (queues 0, 1, 2) Per channel event generation on any of the following events: transfer complete, half transfer complete, data transfer error, user setting error, link transfer error, completed suspension, and trigger overrun 12 concurrent LPDMA channels (8‑channel LPDMA1, 4‑channel LPDMA2): – • Intrachannel LPDMA transfers chaining via programmable linked‑list into memory, supporting two execution modes: run‑to‑completion and link step mode – Intrachannel and interchannel LPDMA transfers chaining via programmable LPDMA input triggers connection to LPDMA task completion events Per linked-list item within a channel: – – • Separately programmed source and destination transfers Programmable data handling between source and destination: byte‑based padding or truncation, sign extension, and left/right realignment – Programmable number of data bytes to be transferred from the source, defining the block level – Linear source and destination addressing: either fixed or contiguously incremented addressing, programmed at a block level, between successive single transfers – Programmable LPDMA request and trigger selection – Programmable LPDMA half-transfer and transfer-complete events generation – Pointer to the next linked-list item and its data structure in memory, with automatic update of the LPDMA linked-list control registers Debug: • – Channel suspend and resume support – Channel status reporting and event flags Privileged/unprivileged support: – – Support for privileged and unprivileged LPDMA transfers, independently at the channel level Privileged-aware AHB slave port Table 2. LPDMA1 channels implementation and usage Channel x Hardware parameters Features dma_fifo_size[x] dma_addressing[x] Channel x (x = 0 to 7) is implemented with: x = 0 to 7 0 0 • • DS14927 - Rev 1 no FIFO. Only a single source transfer cell is internally registered. fixed/contiguously incremented addressing page 13/130 STM32C562xx Functional overview Table 3. LPDMA2 channels implementation and usage Hardware parameters Channel x dma_fifo_size[ x] Features dma_addressi ng[x] Channel x (x = 0 to 3) is implemented with: x = 0 to 3 0 0 • • no FIFO. Only a single source transfer cell is internally registered. fixed/contiguously incremented addressing Table 4. LPDMA1 and LPDMA2 autonomous mode and wake-up in low-power modes Feature Low-power modes Wake-up LPDMA1/2 in Sleep mode 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) • • • • • 81 maskable interrupt channels (not including the 16 Cortex®‑M33 with FPU interrupt lines) 16 programmable priority levels (4 bits of interrupt priority used) Low-latency exception and interrupt handling Power management control Implementation of system control registers The NVIC and the processor core interface are closely coupled, enabling low‑latency interrupt processing and efficient processing of late‑arriving interrupts. All interrupts, including the core exceptions, are managed by the NVIC. 3.13.2 Extended interrupt and event controller (EXTI) The extended interrupts and event controller (EXTI) manages the individual CPU and system wake‑up through configurable and direct event inputs. It provides wake‑up requests to the power control and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU, an additional event generation block (EVG) is needed to generate the CPU event signal. The EXTI wake-up requests allow the system to wake up from Stop modes. The interrupt request and event request generation can also be used in Run modes. The EXTI also includes the EXTI mux I/O port selection. The EXTI main features are the following: • • • • 35 input events are supported. All event inputs allow the possibility to wake up the system. Events that do not have an associated wake‑up flag in the peripheral have a flag in the EXTI and generate an interrupt to the CPU from the EXTI. Events can be used to generate a CPU wake‑up event. The asynchronous event inputs are classified into two groups: DS14927 - Rev 1 page 14/130 STM32C562xx Functional overview • Configurable events (signals from I/Os or peripherals able to generate a pulse), with the following features: – – – • Selectable active trigger edge Interrupt pending status register bits independent for the rising and falling edge Individual interrupt and event generation mask, used for conditioning the CPU wake‑up, interrupt, and event generation – Software trigger possibility – EXTI I/O port selection Direct events (interrupt and wake-up sources from peripherals having an associated flag which requires to be cleared in the peripheral), with the following features: – – – – 3.14 Fixed rising edge active trigger No interrupt pending status register bit in the EXTI (the interrupt pending status flag is provided by the peripheral generating the event) Individual interrupt and event generation mask, used to condition the CPU wake‑up and event generation No software trigger possibility Cyclic redundancy check calculation unit (CRC) The cyclic redundancy check calculation unit (CRC) calculation unit is used to get a CRC code from 8‑, 16‑, or 32‑bit data word and a generator polynomial. Among other applications, CRC‑based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 3.15 Analog-to-digital converter (ADC) The devices embed up to two analog-to-digital converters (ADC). • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is the master). Each ADC consists of one 12-bit successive approximation analog-to-digital converter. Each ADC has up to 14 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan, or discontinuous mode. The result of the ADC is stored in a left‑aligned or right‑aligned (default configuration) 32‑bit data register. The ADCs are mapped on the AHB bus to allow fast data handling. The analog watchdog features allow the application to detect if the input voltage goes outside the user‑defined high or low thresholds. A built-in hardware oversampler improves analog performance while off‑loading the related computational burden from the CPU. An efficient low‑power mode is implemented to allow very low consumption at low frequency. The ADC main features are: DS14927 - Rev 1 page 15/130 STM32C562xx Functional overview • High-performance features: – • Up to two ADCs which can operate in dual mode ◦ ADC1 is connected to 12 external channels and two internal channels. ◦ ADC2 is connected to 14 external channels. – 12, 10, 8, or 6-bit configurable resolution – ADC conversion time independent from the AHB bus clock frequency – Faster conversion time by lowering resolution – AHB slave bus interface to allow fast data handling – Channel-wise programmable sampling time – Flexible sampling time control – Fixed latency for a trigger to start of sampling – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable) – Data alignment with in-built data coherency – Data can be managed by DMA for regular channel conversions – Four dedicated data registers for the injected channels Low-power features: – – – • Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency Allows slow bus frequency application while keeping optimum ADC performance Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (autodelayed mode) Oversampler: • – 32-bit data register – Oversampling ratio adjustable from 2 to 1024 – Programmable data right and left shifts Data preconditioning: • – Gain compensation – Offset compensation Analog input channels: • – – External analog inputs (per ADC): up to 14 GPIO pads One channel for the internal reference voltage (VREFINT) – One channel for the internal temperature sensor (VSENSE) Start-of-conversion can be initiated: – – • • • • DS14927 - Rev 1 By software for both regular and injected conversions By hardware triggers with configurable polarity (internal timer events or GPIO input events) for both regular and injected conversions Conversion modes: – Each ADC can convert a single channel or can scan a sequence of channels – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2, or 3, or overrun events Three analog watchdogs per ADC ADC input range: VSSA ≤ VIN ≤ VREF+ page 16/130 STM32C562xx Functional overview Table 5. ADC features ADC modes/features Resolution 3.15.1 ADC1 ADC2 12 bits Maximum sampling-speed 2.25 Msps Hardware-offset calibration X Single-ended inputs X Injected channel conversion X Oversampling up to x1024 Data register 32 bits DMA support X Offset compensation X Gain compensation X Number of analog watchdogs 3 Analog temperature sensor The STM32C562xx embed an analog temperature sensor that generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC input channel that is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory‑calibrated by STMicroelectronics. The temperature sensor factory calibration data are stored by STMicroelectronics in the system memory area, accessible in read‑only mode. 3.15.2 Internal voltage reference (VREFINT) The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparator. It is internally connected to ADC input channel. The precise voltage of VREFINT is individually measured for each part by STMicroelectronics during production test and stored in the system memory area. It is accessible in read‑only mode. 3.16 Digital to analog converter (DAC) The DAC module is a 12‑bit, voltage output digital‑to‑analog converter. The DAC can be configured in 8‑ or 12‑bit mode and can be used in conjunction with the DMA controller. In 12‑bit mode, the data may be left‑aligned or right‑aligned. An input reference pin, VREF+ (shared with others analog peripherals) is available for better resolution. The DAC_OUT1 pin can be used as general-purpose input/output (GPIO) when the DAC output is disconnected from the output pad and connected to the on chip peripheral. The DAC output buffer can be optionally enabled to allow a high drive output current. An individual calibration can be applied DAC output channel. The DAC output channels support a low-power mode, the sample and hold mode. DS14927 - Rev 1 page 17/130 STM32C562xx Functional overview The DAC main features are:: • • • • • • • • • • • • 3.17 Left or right data alignment in 12-bit mode Synchronized update capability Noise-wave and triangular-wave generation DMA capability for each channel including DMA underrun error detection Double-data DMA capability to reduce the bus activity External triggers for conversion DAC output-channel buffered/unbuffered modes Buffer offset calibration DAC output can be disconnected from the DAC_OUTx output pin DAC output connection to on chip peripherals Sample and hold mode for low-power operation in Stop mode Voltage reference input from VREF+ pin Low-power comparator (COMP) The device embeds a low-power comparator (COMP). It can be used for a variety of functions including: • • • Wake-up from low-power mode triggered by an analog signal Analog signal conditioning Cycle-by-cycle current control loop when combined with a PWM output from a timer The COMP main features are: • Selectable inverting analog inputs: – – – 3.18 • • • • • I/O pins DAC channel output Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by the scaler (buffered voltage divider) I/O pins selectable as noninverting analog inputs Programmable hysteresis Programmable speed/consumption Mapping of outputs to I/Os Redirection of outputs to timer inputs for triggering: • • • – Capture events – OCREF_CLR events (for cycle-by-cycle current control) – Break events for fast PWM shutdowns Blanking of comparator outputs Interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller) Direct interrupt output to the CPU True random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32‑bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a nondeterministic random bit generator (NDRBG). The RNG can be certified NIST SP800-90B. It has also been tested using the German BSI statistical tests of AIS-31 (T0 to T8). The RNG main features are the following: DS14927 - Rev 1 page 18/130 STM32C562xx Functional overview • • • • • • 3.19 The RNG delivers 32-bit true random numbers, produced by an analog entropy source conditioned by a NIST SP800-90B approved conditioning stage. It can be used as the entropy source to construct a nondeterministic random bit generator (NDRBG). In the default configuration, it produces four 32-bit random samples every 412 AHB clock cycles if fAHB < fthreshold (256 RNG clock cycles otherwise). It embeds startup and NIST SP800-90B approved continuous health tests (repetition count and adaptive proportion tests), associated with specific error management. It can be disabled to reduce power consumption, or enabled with an automatic low power mode (default configuration). It has an AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only (else an AHB bus error is generated, and the write accesses are ignored). AES hardware accelerator (AES) The AES hardware accelerator (AES) encrypts or decrypts data in compliance with the advanced encryption standard (AES) defined by NIST. AES supports ECB, CBC, CTR, GCM, GMAC, and CCM chaining modes for key sizes of 128 or 256 bits. The peripheral supports DMA single transfers for incoming and outgoing data (two DMA channels are required). The AES main features are: • • Compliant with NIST FIPS publication 197 “Advanced encryption standard (AES)” (November 2001) Encryption and decryption with multiple chaining modes: • – Electronic codebook (ECB) mode – Cipher block chaining (CBC) mode – Counter (CTR) mode – Galois counter mode (GCM) – Galois message authentication code (GMAC) mode – Counter with CBC-MAC (CCM) mode 128-bit data block processing, supporting cipher key lengths of 128‑bit and 256‑bit – • • • • • • • • 51 or 75 clock cycle latency in ECB mode for processing one 128‑bit block with, respectively, 128‑bit or 256‑bit key Integrated key scheduler to compute the last round key for ECB/CBC decryption 256-bit write-only registers for storing cryptographic keys (eight 32‑bit registers) 128-bit registers for storing initialization vectors (four 32‑bit registers) 32-bit buffer for data input and output Automatic data flow control supporting two direct memory access (DMA) channels, one for incoming data, one for processed data. Only single transfers are supported. Data-swapping logic to support 1-, 8-, 16-, or 32-bit data AMBA AHB slave peripheral, accessible through 32-bit word single accesses only. Other access types generate an AHB error, and other than 32‑bit writes may corrupt the register content. Software (in CPU mode only, not in DMA mode) can suspend a message if AES needs to process another message with a higher priority, then resume the original message. Table 6. AES features Modes or features(1) ECB, CBC chaining X CTR, CCM, GCM chaining X AES 128-bit ECB encryption in cycles 51 DHUK and BHK key selection - Resistant to side-channel attacks - Shared key between SAES and AES X Key sizes in bits DS14927 - Rev 1 AES 128/256 page 19/130 STM32C562xx Functional overview 1. X = supported. 3.20 HASH processor (HASH) The hash processor is a fully compliant implementation of the secure hash algorithm (SHA‑1, SHA‑2 family) and the HMAC (keyed‑hash message authentication code) algorithm. HMAC is suitable for applications requiring message authentication. The hash processor computes FIPS (Federal Information Processing Standards) approved digests of lengths of 160, 224, and 256 bits for messages of any length less than 2 × 64 bits (for SHA‑1, SHA‑224, and SHA‑256). The HASH main features are: • Suitable for data authentication applications, compliant with: – • Federal Information Processing Standards Publication FIPS PUB 180‑4, Secure Hash Standard (SHA‑1 and SHA‑2 family) – Federal Information Processing Standards Publication FIPS PUB 186-4, Digital Signature Standard (DSS) – Internet Engineering Task Force (IETF) Request For Comments RFC 2104, HMAC: Keyed-Hashing for Message Authentication and Federal Information Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message Authentication Code (HMAC) Fast computation of SHA-1, SHA2-224, SHA2-256: – • • 82 (respectively 66) clock cycles for processing one 512-bit block of data using SHA‑1 (respectively SHA‑256) algorithm Support for HMAC mode with all supported algorithms Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message. – • • • • • • • Automatic 32-bit word swapping to comply with the internal little‑endian representation of the input bit‑string – Supported word swapping format: bits, bytes, half-words, and 32-bit words Single 32-bit, write-only, input register associated with an internal input FIFO, corresponding to a 64‑byte block size (16 × 32 bits) Automatic padding to complete the input bit string to fit the digest minimum block size AHB slave peripheral, accessible by 32-bit words only (else an AHB error is generated) 8 × 32-bit words (H0 to H15) for output message digest Automatic data flow control supporting direct memory access (DMA) using one channel Support for both single and fixed DMA burst transfers of four words Interruptible message digest computation, on a per‑block basis – – DS14927 - Rev 1 Reloadable digest registers Hashing computation suspend/resume mechanism, including DMA page 20/130 STM32C562xx Functional overview 3.21 Timers and watchdogs The devices include two advanced control timers, up to eleven general‑purpose timers, two basic timers, two low‑power timers, two watchdog timers, and one SysTick timer. The table below compares the features of the advanced control, general‑purpose and basic timers. Table 7. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture / compare channels Complementary outputs Advanced control TIM1, TIM8 16 bits Up, down, Up/ down Any integer between 1 and 65536 Yes 4 4 TIM2, TIM5 32 bits Up, down, Up/ down Yes 4 No TIM12 16 bits Up No 2 No TIM15 16 bits Up, down, Up/ down 2 1 1 No 0 No Generalpurpose Basic 3.21.1 TIM16, TIM17 16 bits Up, down, Up/ down TIM6, TIM7 16 bits Up Any integer between 1 and 65536 Yes Any integer between 1 and 65536 Yes Advanced-control timers (TIM1/TIM8) The advanced-control timers (TIM1/TIM8) consist of a 16-bit autoreload counter driven by a programmable prescaler. They may be used for various purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. TIM1/TIM8 timer features include: • • DS14927 - Rev 1 • 16-bit up, down, up/down autoreload counter 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency by any factor from 1 to 65536 Seven independent channels for: • • • • • – Input capture (except channels 5, 6, and 7) – Output compare – PWM generation (edge- and center-aligned mode) – One-pulse mode output Complementary outputs with programmable dead-time Synchronization circuit to control the timer with external signals and to interconnect several timers together Repetition counter to update the timer registers only after a given number of cycles of the counter Two break inputs to put the timer’s output signals in a safe user‑selectable configuration Interrupt/DMA generation on the following events: • • • – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization, or count by internal/external trigger) – Input capture – Output compare Incremental encoders, quadrature encoders, and hall‑sensors support Trigger input for external clock or cycle-by-cycle current management ADC synchronization for jitter-free sampling points page 21/130 STM32C562xx Functional overview 3.21.2 General-purpose timers (TIM2/TIM5/TIM12/TIM15/TIM16/TIM17) The general-purpose timers (TIMx) consist of a 16-bit or 32-bit autoreload counter driven by a programmable prescaler. They can be used for various purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. General-purpose TIMx timer features include: • • 3.21.3 • 16-bit or 32-bit up, down, up/down autoreload counter 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 Up to four independent channels for: • • – Input capture – Output compare – PWM generation (edge- and center-aligned modes) – One-pulse mode output Synchronization circuit to control the timer with external signals and to interconnect several timers Interrupt/DMA generation on the following events: • • • – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization, or count by internal/external trigger) – Input capture – Output compare Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes Trigger input for external clock or cycle-by-cycle current management ADC synchronization for jitter-free sampling points Basic timers (TIM6/TIM7) The basic timers (TIM6/TIM7) consist of a 16-bit autoreload counter driven by a programmable prescaler. They can be used as generic timers for time-base generation. The basic timer can also be used for triggering the digital-to-analog converter. This is done with the trigger output of the timer. The timers are completely independent and do not share any resources. Basic timer (TIM6/TIM7) features include: • • • • • 3.21.4 16-bit autoreload upcounter 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 Synchronization circuit to trigger the DAC Interrupt/DMA generation on the update event: counter overflow ADC synchronization for jitter-free sampling points Low-power timers (LPTIM1) The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM can keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a pulse counter, which can be useful in some applications. The LPTIM capability to wake up the system from low‑power modes makes it suitable to realize timeout functions with extremely low-power consumption. DS14927 - Rev 1 page 22/130 STM32C562xx Functional overview The low-power timer supports the following features: • • • 16-bit up counter with 16-bit auto reload register 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128) Selectable clock – – • • • • • • • • • • Internal clock sources: LSE, LSI, HSI, or APB clock External clock source over LPTIM input (working with no LP oscillator running, used by pulse counter application) 16-bit ARR auto reload register 16-bit capture/compare register Continuous/one-shot mode Selectable software/hardware input trigger Programmable digital glitch filter Configurable output: pulse, PWM Configurable I/O polarity Encoder mode Repetition counter Up to two independent channels for: • • – Input capture – PWM generation (edge-aligned mode) – One-pulse mode output Interrupt generation on ten events DMA request generation on the following events: – – 3.21.5 Update event Input capture Independent watchdog (IWDG) The independent watchdog (IWDG) peripheral offers a high safety level due to its capability to detect malfunctions caused by software or hardware failures. The IWDG is clocked by an independent clock and remains active even if the main clock fails. Additionally, the watchdog function is performed in the VDD voltage domain, allowing the IWDG to remain functional even in low‑power modes. The IWDG main features are: • • • • • 12-bit down-counter Dual voltage domain, thus enabling operation in low-power modes Independent clock Early wake-up interrupt generation Reset generation: – – 3.21.6 In case of timeout In case of refresh outside the expected window Window watchdog (WWDG) The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates a reset on the expiry of a programmed time period unless the program refreshes the contents of the down-counter before the T6 bit is cleared. A reset is also generated if the 7‑bit down‑counter value (in the control register) is refreshed before the down-counter reaches the window register value. This implies that the counter must be refreshed in a limited window. The WWDG clock is prescaled from the APB clock and has a configurable time window that can be programmed to detect abnormally late or early application behavior. The WWDG is best suited for applications requiring the watchdog to react within an accurate timing window. The WWDG main features are: DS14927 - Rev 1 page 23/130 STM32C562xx Functional overview • • • 3.21.7 Programmable free-running down-counter Conditional reset: – Reset (if watchdog activated) when the down-counter value becomes lower than 0x40 – Reset (if watchdog activated) if the down-counter is reloaded outside the window Early wake-up interrupt (EWI): triggered (if enabled and the watchdog activated) when the down‑counter is equal to 0x40 SysTick timer The Cortex®-M33 embeds one SysTick timer. This timer is dedicated to real‑time operating systems, but can also be used as a standard down counter. It features: • • • • 3.22 3.22.1 A 24-bit down counter Auto reload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source Real-time clock (RTC), tamper and backup registers Real-time clock (RTC) The real-time clock (RTC) supports the following features: • • • • • • • • • • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date, month, year, in BCD (binary‑coded decimal) format Binary mode with 32-bit free-running counter Automatic correction for 28, 29 (leap year), 30, and 31 days of the month Two programmable alarms On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a controller clock. Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy Timestamp feature that can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable resolution and period Privilege protection support: – Alarm A, alarm B, wake-up timer, and timestamp individual privileged protection The RTC is functional in all low-power modes when it is clocked by the LSE. All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up the device from the low‑power modes. 3.22.2 Tamper and backup registers (TAMP) The antitamper detection circuit is used to protect sensitive data from external attacks. Thirty-two 32‑bit backup registers are retained in all low-power modes. The backup registers, as well as other secrets in the device, are protected by this antitamper detection circuit with three tamper pins and six internal tampers. The external tamper pins can be configured for edge detection or level detection with or without filtering. The TAMP main features are: DS14927 - Rev 1 page 24/130 STM32C562xx Functional overview • 3.23 • • A tamper detection can optionally erase the backup registers, SRAM2, ICACHE, and cryptographic peripherals. The device resources protected by tamper are named “device secrets”. 32 × 32‑bit backup registers Up to three tamper pins for three external tamper detection events: • • – Passive tampers: Ultralow-power edge or level detection with internal pull-up hardware management – Configurable digital filter Six internal tamper events to protect against transient attacks Each tamper can be configured in two modes: • • – Confirmed mode: immediate erase of secrets on tamper detection, including backup registers erase – Potential mode: most of the secrets erase following a tamper detection are launched by software Any tamper detection can generate an RTC timestamp event Tamper configuration and backup registers privilege protection Inter-integrated circuit interface (I2C) The device embeds two I2C interfaces. Refer to Table 8 for feature implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus‑specific sequencing, protocol, arbitration, and timing. It supports Standard-mode (Sm), Fast-mode (Fm), and Fast-mode Plus (Fm+). The I2C peripheral is also system management bus (SMBus) and power management bus (PMBus®) compatible. It can use DMA to reduce the CPU load. The I²C peripheral supports: • I²C-bus specification rev03 compatibility: • • • – Controller and target modes – Multicontroller capability – Standard-mode (up to 100 kHz) – Fast-mode (up to 400 kHz) – Fast-mode Plus (up to 1 MHz) – 7-bit and 10-bit addressing mode – Multiple 7-bit target addresses (2 addresses, 1 with configurable mask) – All 7-bit addresses acknowledge mode – General call – Programmable setup and hold times – Easy-to-use event management – Clock stretching (optional) 1-byte buffer with DMA capability Programmable analog and digital noise filters SMBus specification rev 3.0 compatibility: • • • – Hardware PEC (packet error checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and device support – SMBus alert – Timeouts and idle condition detection PMBus rev 1.3 standard compatibility Independent clock Wake-up from Stop mode on address match Table 8. I2C implementation Features(1) Standard-mode (up to 100 Kbit/s) DS14927 - Rev 1 I2C1 I2C2 X X page 25/130 STM32C562xx Functional overview Features(1) I2C1 I2C2 Fast mode (up to 400 Kbit/s) X X Fast mode plus (Fm+) with 20 mA output drive I/Os (up to 1 Mbit/s) X X Programmable analog and digital noise filters X X SMBus/PMBus hardware support X X Independent clock X X Wake-up capability X X 1. X = supported. 3.24 Improved inter-integrated circuit interface (I3C) The I3C interface handles communication between this device and others, such as sensors and the host processor, connected on an I3C bus. An I3C bus is a two-wire, serial single-ended, multidrop bus, intended to improve a legacy I2C bus. The I3C SDR-only peripheral implements all the features required by the MIPI® I3C specification v1.1. It can control all I3C bus-specific sequencing, protocol, arbitration, and timing, and can act as a controller (formerly known as master) or as a target (formerly known as slave). When acting as a controller, the I3C peripheral improves the features of the I2C interface while preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast mode (Fm) or legacy I2C fast mode plus (Fm+), provided that the latter does not perform clock stretching. The I3C peripheral can be used with DMA to offload the CPU. The I3C peripheral supports: DS14927 - Rev 1 page 26/130 STM32C562xx Functional overview • MIPI® I3C specification v1.1, as: • • • – I3C SDR-only primary controller – I3C SDR-only secondary controller – I3C SDR-only target I3C SCL bus clock frequency up to 12.5 MHz Registers configuration from the host application via the APB target port Queued data transfers: • – Transmit FIFO (TX-FIFO) for data bytes/words to be transmitted on the I3C bus – Receive FIFO (RX-FIFO) for received data bytes/words on the I3C bus – For each FIFO, optional DMA mode with a dedicated DMA channel Queued control/status transfers, when controller: • – Control FIFO (C-FIFO) for control words to be sent on the I3C bus – Optional status FIFO (S-FIFO) for status words as received on the I3C bus – For each FIFO, optional DMA mode with a dedicated DMA channel Messages: • – Legacy I²C read/write messages to legacy I2C targets in Fm/Fm+ – I3C SDR read/write private messages – I3C SDR broadcast CCC messages – I3C SDR read/write direct CCC messages Frame-level management, when controller: • – Optional C-FIFO and TX-FIFO preload – Multiple messages encapsulation – Optional arbitrable header generation on the I3C bus – HDR exit pattern generation on the I3C bus for error recovery Programmable bus timing, when controller: • – SCL high and low period – SDA hold time – Bus free (minimum) time – Bus available/idle condition time – Clock stall time Target-initiated requests management: – – • • Simultaneous support up to four targets, when controller In-band interrupts, with programmable IBI payload (up to four bytes), with pending read notification support – Bus control request, with recovery flow support and hand-off delay – Hot-join mechanism HDR exit pattern detection, when target Bus error management: • – CEx with x = 0, 1, 2, 3 when controller – TEx with x = 0, 1, ... , 6 when target – Bus control switch error and recovery – Target reset Individual programmable event-based management: – – – DS14927 - Rev 1 Per-event identification with flag reporting and clear control Host application notification via flag polling, and/or via interrupt with a per-event programmable enable Error type identification page 27/130 STM32C562xx Functional overview • Wake-up from Stop mode(s), as controller: • – On an in-band interrupt without payload – On a hot-join request – On a controller-role request Wake-up from Stop mode(s), as target: • – On a reset pattern – On a missed start Multiclock domain management: – – Separate APB clock and kernel clock, driven from independently programmed clock sources via the RCC, in addition to SCL clock Minimum operating frequency for the kernel clock and the APB clock vs. the application-driven SCL clock Table 9. I3C peripheral controller/target features versus MIPI® v1.1 Features(1) I3CSDR message I2C MIPI® I3C v1.1 I3C peripheral when controller I3C peripheral when target X X X Mandatory when controller and the I3C bus is mixed with (external) legacy I2C target(s). Optional in MIPI v1.1 when target. Comments X X - HDR DDR message X - - HDR-TSL/TSP, HDR-BT X - - Dynamic address assignment X X X - Static address X X - No (intended) support of I3C peripheral as a target on an I2C bus. Grouped addressing X X - Optional in MIPI v1.1 CCCs X X X Mandatory CCCs and some optional CCCs are supported. Error detection and recovery X X X - In-band interrupt (with MDB) X X X - Secondary controller X X X - Hot-join mechanism X X X - Target reset X X X - Synchronous timing control X X - Asynchronous timing control 0 X X - Asynchronous timing control 1, 2, 3 X - - Device-to-device tunneling X X - Multilane data transfer X X - Monitoring device early termination X - - Legacy message (Fm/Fm+) Optional in MIPI v1.1 Optional in MIPI v1.1 1. X = supported. DS14927 - Rev 1 page 28/130 STM32C562xx Functional overview 3.25 Universal synchronous/asynchronous receiver transmitter (USART/UART) and low-power universal asynchronous receiver transmitter (LPUART) The devices have four embedded universal synchronous receiver transmitters (USART1/2/3), three universal asynchronous receiver transmitters (UART4/5), and one low‑power universal asynchronous receiver transmitter (LPUART1). Table 10. USART, UART, and LPUART features Features(1) USART1/2/3 UART4/5 LPUART1 Hardware flow control for modem X X X Continuous communication using DMA X X X Multiprocessor communication X X X Synchronous mode (controller/target) X - - Smartcard mode X - - Single-wire half-duplex communication X X X IrDA SIR ENDEC block X X - LIN mode X X - X(2) X(2) X(2) Receiver timeout interrupt X X X Modbus communication X X X Autobaud rate detection X X X Driver enable X X X Dual-clock domain and wake-up from Stop mode USART data length Tx/Rx FIFO Tx/Rx FIFO size 7, 8, and 9 bits X X X 8 bytes 1. X = supported. 2. Wake‑up supported from Stop mode. 3.25.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) The USART offers a flexible means to perform full‑duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. A very wide range of baud rates can be achieved through a fractional baud rate generator. The USART supports both synchronous one-way and half-duplex single-wire communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA (infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS). Multiprocessor communications are also supported. High-speed data communications are possible by using the DMA (direct memory access) for multibuffer configuration. The USART main features are: DS14927 - Rev 1 page 29/130 STM32C562xx Functional overview • • • • • • • • • • • • • • • • • • • • • • • Full-duplex asynchronous communication NRZ standard format (mark/space) Configurable oversampling method by 16 or 8 to achieve the best compromise between speed and clock tolerance Baud rate generator systems Two internal FIFOs for transmit and receive data Each FIFO can be enabled/disabled by software and come with a status flag. A common programmable transmit and receive baud rate Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK Auto baud rate detection Programmable data word length (7, 8, or 9 bits) Programmable data order with MSB-first or LSB-first shifting Configurable stop bits (one or two stop bits) Synchronous controller/target mode and clock output/input for synchronous communications SPI controller transmission underrun error flag Single-wire half-duplex communications Continuous communications using DMA Received/transmitted bytes are buffered in reserved SRAM using centralized DMA Separate enable bits for transmitter and receiver Separate signal polarity control for transmission and reception Swappable Tx/Rx pin configuration Hardware flow control for modem and RS-485 transceiver Communication control/error detection flags Parity control: • • • • – Transmits parity bit – Checks parity of received data byte Interrupt sources with flags Multiprocessor communications: wake-up from Mute mode by idle line detection or address mark detection Wake-up from Stop capability LIN controller synchronous break send capability and LIN target break detection capability • • – 13-bit break generation and 10/11-bit break detection when USART is hardware configured for LIN IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode Smartcard mode – • Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in the ISO/ IEC 7816‑3 standard – 0.5 and 1.5 stop bits for Smartcard operation Support for Modbus communication – – 3.25.2 Timeout feature CR/LF character recognition Low-power universal asynchronous receiver transmitter (LPUART) The LPUART is a UART, which enables bidirectional UART communications with a limited power consumption. Only a 32.768 kHz LSE clock is required to enable UART communications up to 9600 bauds. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock. Even when the microcontroller is in low-power mode, the LPUART can wait for an incoming UART frame while having an extremely low energy consumption. The LPUART includes all necessary hardware support to make asynchronous serial communications possible with minimum power consumption. It supports half-duplex single-wire communications and modem operations (CTS/RTS). It also supports multiprocessor communications. The direct memory access (DMA) can be used for data transmission/reception. The LPUART main features are: DS14927 - Rev 1 page 30/130 STM32C562xx Functional overview • • • • • • 3.26 • • • • • • • • • • • • Full-duplex asynchronous communications NRZ standard format (mark/space) Programmable baud rate From 300 bauds to 9600 bauds using a 32.768 kHz clock source Higher baud rates can be achieved by using a higher frequency clock source Two internal FIFOs to transmit and receive data Each FIFO can be enabled/disabled by software and come with status flags for FIFOs states. Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK Programmable data word length (7 or 8 or 9 bits) Programmable data order with MSB‑first or LSB‑first shifting Configurable stop bits (one or two stop bits) Single-wire half-duplex communications Continuous communications using DMA Received/transmitted bytes are buffered in reserved SRAM using centralized DMA Separate enable bits for transmitter and receiver Separate signal polarity control for transmission and reception Swappable Tx/Rx pin configuration Hardware flow control for modem and RS‑485 transceiver Transfer detection flags: • – Receive buffer full – Transmit buffer empty – Busy and end of transmission flags Parity control: • – Transmits parity bit – Checks parity of received data byte Four error detection flags: • • • – Overrun error – Noise detection – Frame error – Parity error Interrupt sources with flags Multiprocessor communications: wake-up from Mute mode by idle line detection or address mark detection Wake-up from Stop mode Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) The devices embed three serial peripheral interfaces (SPI) that can be used to communicate with external devices while using the specific synchronous protocol. The SPI protocol supports half‑duplex, full‑duplex, and simplex synchronous, serial communication with external devices. Table 11. SPI features SPI2S1, SPI2S2, SPI2S3 (full feature set instances) SPI feature DS14927 - Rev 1 Data size Configurable from 4 to 32-bit CRC computation CRC polynomial length configurable from 5 to 32‑bit Size of FIFOs 16 × 8-bit Number of transferred data Unlimited, expandable I2S feature Yes page 31/130 STM32C562xx Functional overview The serial peripheral interface (SPI) can be used to communicate with external devices while using the specific synchronous protocol. The SPI protocol supports half-duplex, full-duplex, and simplex synchronous, serial communication with external devices. The interface can be configured as master or slave and can operate in multimaster or multislave configurations. The device configured as master provides a communication clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied optionally just to set up communication with a specific slave and to ensure it handles the data flow properly. The Motorola® data format is used by default, but some other specific modes are supported as well. The SPI main features are: • • • • • • • • • • • • • • • • • • • • • • • Full-duplex synchronous transfers on three lines Half-duplex synchronous transfer on two lines (with bidirectional data line) Simplex synchronous transfers on two lines (with unidirectional data line) From 4-bit up to 32-bit data size selection Multimaster or multislave mode capability Dual clock domain, the peripheral kernel clock is independent from the APB bus clock Baud rate prescaler up to kernel frequency/2 or bypass from RCC in master mode Protection of configuration and setting Hardware or software management of SS for both master and slave Adjustable minimum delays between data and between SS and data flow Configurable SS signal polarity and timing, MISO × MOSI swap capability Programmable clock polarity and phase Programmable data order with MSB-first or LSB-first shifting Programmable number of data within a transaction to control SS and CRC Dedicated transmission and reception flags with interrupt capability SPI Motorola and TI format support Hardware CRC can verify the integrity of the communication at the end of a transaction by: – Adding CRC value in Tx mode – Automatic CRC error checking for Rx mode Error detection with interrupt capability in case of data overrun, CRC error, data underrun, mode fault, and frame error, depending on the operating mode Two 8-bit width embedded Rx and Tx FIFOs (FIFO size depends on instance) Configurable FIFO thresholds (data packing) Capability to handle data streams by system DMA controller Configurable behavior at slave underrun condition (support of cascaded circular buffers) Optional status pin RDY signaling that the slave device is ready to handle the data flow The I2S main features are: DS14927 - Rev 1 page 32/130 STM32C562xx Functional overview • • • • • • • • • • Full duplex communication Simplex communication (only transmitter or receiver) Master or slave operations 8-bit programmable linear prescaler Data length can be 16, 24, or 32 bits Channel length can be 16 or 32 in master, any value in slave Programmable clock polarity Error flags signaling for improved reliability: Underrun, overrun, and frame errors Embedded Rx and Tx FIFOs Supported I2S protocols: • • • – I2S Philips standard – MSB-justified standard (left-justified) – LSB-justified standard (right-justified) – PCM standard (with short and long frame synchronization) Data ordering programmable (LSB or MSB first) DMA capability for transmission and reception Master clock can be output to drive an external audio component: – – 3.27 FMCK = 256 × FWS for all I2S modes FMCK = 128 × FWS for all PCM modes Controller area network (FDCAN) The controller area network (CAN) subsystem consists of one CAN module, a shared message RAM memory, and a configuration block. The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs, and transmits FIFOs. The FDCAN main features are: • • • • • • • • • • • • • 3.28 Conform with CAN protocol version 2.0 part A, B, and ISO 11898-1: 2015, -4 CAN FD with maximum 64 data bytes supported CAN error logging AUTOSAR and J1939 support Improved acceptance filtering Two receive FIFOs of three payloads each (up to 64 bytes per payload) Separate signaling on reception of high priority messages Configurable transmit FIFO/queue of three payloads (up to 64 bytes per payload) Configurable transmit event FIFO Programmable loop-back test mode Maskable module interrupts Two clock domains: APB bus interface and CAN core kernel clock Power-down support Universal serial bus full-speed host/device interface (USB) The USB peripheral implements an interface between a full‑speed USB 2.0 bus and the APB2 bus. USB suspend and resume are supported, which permits stopping the device clocks for low‑power consumption. The USB main features are: DS14927 - Rev 1 page 33/130 STM32C562xx Functional overview • • • • • • • • • • • • USB specification version 2.0 full-speed compliant Supports both host and device modes Configurable number of endpoints from 1 to 8 Dedicated packet buffer memory (SRAM) of 2048 bytes Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted (NRZI) encoding/ decoding, and bit‑stuffing Isochronous transfers support Double-buffered bulk/isochronous endpoint/channel support USB suspend and resume operations Frame-locked clock pulse generation USB 2.0 link power management support (device mode only) Battery charging specification revision 1.2 support (device mode only) USB connect/disconnect capability (controllable embedded pull-up resistor on USB_DP line) 3.29 Development support 3.29.1 Serial-wire/JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded and is a combined JTAG and serial‑wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG‑DP and SW‑DP. 3.29.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ (ETM) provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The ETM operates with third party debugger software tools. DS14927 - Rev 1 page 34/130 STM32C562xx Pinouts/ballouts, pin description, and alternate functions 4 Pinouts/ballouts, pin description, and alternate functions 4.1 Pinout/ballout schematics Figure 3. LQFP32 pinout VSS PB8-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 32 31 30 29 28 27 26 25 Package top view VDD 1 24 PA14 PH0-OSC_IN/PC14 2 23 PA13 PH1-OSC_OUT 3 22 PA12 NRST 4 21 PA11 VREF+ 5 20 PA9 PA0 6 19 PA8 PA1 7 18 PB15 PA2 8 17 VDD 11 12 13 14 15 16 PA5 PA6 PA7 PB0 VCAP VSS DT74257V2 10 9 PA3 PA4 LQFP32 Figure 4. UFQFPN32 pinout PB8 PH2-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 32 31 30 29 28 27 26 25 Package top view VDD 1 24 PA14 PH0-OSC_IN/PC14 2 23 PA13 PH1-OSC_OUT 3 22 PA12 NRST 4 21 PA11 VREF+ 5 20 PA9 PA0 6 19 PA8 PA1 7 18 PB15 PA2 8 17 VDD Note: DS14927 - Rev 1 16 VSS DT74256V2 VCAP 15 PB1 14 PB0 13 PA7 12 PA6 11 PA5 10 PA4 PA3 9 UFQFPN32 There is an exposed die pad on the underside of the UFQFPN package. This backside pad must be connected and soldered to PCB ground. page 35/130 STM32C562xx Pinouts/ballouts, pin description, and alternate functions Figure 5. LQFP48 pinout VDD VSS PB9 PB8 PH2-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Package top view PE2 1 36 VDD PC13 2 35 VSS PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH1-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VREF- 8 29 PA8 VREF+ 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 14 15 16 17 18 19 20 21 22 23 24 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 VCAP VSS VDD DT74258V1 13 PA3 LQFP48 Figure 6. UFQFPN48 pinout VDD VSS PB9 PB8 PH2-BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 48 47 46 45 44 43 42 41 40 39 38 37 Package top view PE2 1 36 VDD PC13 2 35 VSS PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT 4 33 PA12 PH0-OSC_IN 5 32 PA11 PH1-OSC_OUT 6 31 PA10 NRST 7 30 PA9 VREF- 8 29 PA8 VREF+ 9 28 PB15 PA0 10 27 PB14 PA1 11 26 PB13 PA2 12 25 PB12 24 23 22 21 20 19 18 17 16 15 14 13 UFQFPN48 Note: DS14927 - Rev 1 DT74259V1 VDD VSS VCAP PB10 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 VSS There is an exposed die pad on the underside of the UFQFPN package. This backside pad must be connected and soldered to PCB ground. page 36/130 STM32C562xx Pinouts/ballouts, pin description, and alternate functions Figure 7. LQFP64 pinout PC11 PC10 PA15 PA14 52 51 50 49 PD2 PC12 PB3 55 53 PB4 56 54 PB6 PB5 57 59 58 PH2-BOOT0 PB7 60 PB9 PB8 61 VSS 63 62 VDD 64 Package top view PE2 1 48 VDD PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VREF- 12 37 PC6 VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 DT74260V1 32 31 VSS VDD 30 29 PB10 VCAP 28 PB2 27 PB1 25 26 PB0 PC5 24 23 PA7 PC4 22 20 PA4 21 19 VDD PA5 18 PA6 17 PA3 VSS LQFP64 Figure 8. LQFP80 pinout DS14927 - Rev 1 PB9 PB8 PH2-BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PE2 1 60 VDD PE3 2 59 VSS PC13 3 58 PA13 PC14-OSC32_IN 4 57 PA12 PC15-OSC32_OUT 5 56 PA11 VSS 6 55 PA10 PA9 VDD 7 54 PH0-OSC_IN 8 53 PA8 PH1-OSC_OUT 9 52 PC9 NRST 10 PC0 11 LQFP80 51 PC8 50 PC7 35 36 37 38 39 40 PE9 PB10 VCAP VSS VDD 34 PE8 PE10 33 PB12 PE7 41 32 20 31 PB13 PA2 PB2 42 PB1 19 30 PB14 PA1 29 43 PB0 18 PC5 PB15 PA0 28 44 27 17 PA7 PD12 PH5 PC4 45 26 16 PA6 PD13 VREF+ 25 46 PA5 15 24 PD14 VREF- PA4 47 23 14 VDD PD15 PC3 22 PC6 48 21 49 13 PA3 12 VSS PC1 PC2 DT74261V1 PE1 PE0 77 VSS 79 78 VDD 80 Package top view page 37/130 STM32C562xx Pinouts/ballouts, pin description, and alternate functions Figure 9. LQFP100 pinout DS14927 - Rev 1 VSS PE1 PE0 PB9 PB8 PH2-BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 PH3 PE5 4 72 PA13 PE6 5 71 PA12 PH15 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 PH4 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 PH5 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VCAP VSS VDD LQFP100 DT74262V1 VDD 100 Package top view page 38/130 DS14927 - Rev 1 4.2 Pin description Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name. I Pin type I/O Input-only pin Input/output pin S Supply pin FT 5 V-tolerant I/O TT 3.6 V-tolerant I/O RST Bidirectional reset pin with embedded weak pull‑up resistor Options for TT and FT I/Os(1) I/O structure Notes _a I/O with analog switch function supplied by VDDA _t Tamper I/O _f I/O fm+ capable _u I/O with USB function Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 1. The related I/O structures in the table below are a concatenation of various options. Examples: FT, TT_a. STM32C562xx page 39/130 Pinouts/ballouts, pin description, and alternate functions Pin functions Definition Pin number UFQFPN32 LQFP48 UFQFPN48 LQFP64 LQFP80 LQFP100 Pin name (function after reset) LQFP32 DS14927 - Rev 1 Table 13. STM32C562xx pin/ball definition - - 1 1 1 1 1 PE2 I/O FT - TRACECLK, LPTIM1_IN2, SPI3_SCK/I2S3_CK, EVENTOUT - - - - - - 2 2 PE3 I/O FT - TRACED0, TIM15_BKIN, USART1_RX, EVENTOUT - - - - - - - 3 PE4 I/O FT - TRACED1, TIM15_CH1N, SPI3_NSS/I2S3_WS, USART1_TX, EVENTOUT - - - - - - - 4 PE5 I/O FT - TRACED2, TIM15_CH1, SPI3_MISO/I2S3_SDI, USART1_CK, EVENTOUT - WKUP3 Pin type I/O structure Notes Alternate functions Additional functions - - - - 5 PE6 I/O FT - - - - - - - 6 PH15 I/O FT - USART1_RTS, EVENTOUT - - - 2 2 2 3 7 PC13 I/O FT_t (1)(2) FDCAN1_TX, EVENTOUT TAMP_IN1, RTC_OUT1/ RTC_TS, WKUP4 2 2 3 3 3 4 8 PC14-OSC32_IN (OSC32_IN) I/O FT (1) TIM12_CH1, FDCAN1_RX, EVENTOUT OSC32_IN - - 4 4 4 5 9 PC15OSC32_OUT (OSC32_OUT) I/O FT (1) TIM12_CH2, EVENTOUT OSC32_OUT - - - - - 6 10 VSS S - - - - - - - - - 7 11 VDD S - - - - 2 2 5 5 5 8 12 PH0-OSC_IN (PH0) I/O FT_f - I2C1_SDA, EVENTOUT OSC_IN 3 3 6 6 6 9 13 PH1-OSC_OUT (PH1) I/O FT_f - I2C1_SCL, EVENTOUT OSC_OUT 4 4 7 7 7 10 14 NRST I/O RST - - - - - - - 8 11 15 PC0 I/O FT_a - SPI2_RDY, TIM16_BKIN, EVENTOUT ADC1_IN8 STM32C562xx - Pinouts/ballouts, pin description, and alternate functions page 40/130 - TRACED3, TIM1_BKIN2, TIM15_CH2, SPI3_MOSI/ I2S3_SDO, USART1_CTS/ USART1_NSS, EVENTOUT LQFP48 UFQFPN48 LQFP64 LQFP80 LQFP100 - - - - 9 12 16 PC1 I/O FT_ta - TRACED0, SPI2_MOSI/ I2S2_SDO, EVENTOUT ADC1_IN9, ADC2_IN9, TAMP_IN2, WKUP6 - - - - 10 13 17 PC2 I/O FT_a - PWR_CSLEEP, TIM17_CH1, SPI2_MISO/I2S2_SDI, EVENTOUT ADC1_IN10, ADC2_IN10 - - - - 11 14 18 PC3 I/O FT_a - PWR_CSTOP, LPUART1_TX, SPI2_MOSI/I2S2_SDO, EVENTOUT ADC1_IN11, ADC2_IN11 - - - - - - 19 PH4 I/O FT_a - EVENTOUT ADC2_IN12 - - 8 8 12 15 20 VREF- S - - - - 5 5 9 9 13 16 21 VREF+ S - - - - - - - - - 17 22 PH5 I/O FT_a - EVENTOUT ADC2_IN13 - TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI2_RDY, SPI3_RDY, USART2_CTS/USART2_NSS, UART4_TX, SPI2_NSS/I2S2_WS, TIM2_ETR, EVENTOUT ADC1_IN0, ADC2_IN0, COMP1_INP1, TAMP_IN2, WKUP1 - TIM2_CH2, TIM5_CH2, TIM8_BKIN, TIM15_CH1N, LPTIM1_IN1, USART2_RTS, UART4_RX, EVENTOUT ADC1_IN1, ADC2_IN1, TAMP_IN3 - TIM2_CH3, TIM5_CH3, LPUART1_RX, TIM15_CH1, LPTIM1_IN2, USART2_TX, EVENTOUT ADC1_IN2, ADC2_IN2, TAMP_IN3, WKUP2 ADC1_IN3, ADC2_IN3 6 7 8 6 7 8 10 11 12 10 11 12 14 15 16 18 19 20 23 24 25 PA0 PA1 PA2 Pin type I/O structure Notes I/O I/O I/O FT_ta FT_ta FT_ta Alternate functions Additional functions 9 13 13 17 21 26 PA3 I/O FT_a - - - - - 18 22 27 VSS S - - - - - - - - 19 23 28 VDD S - - - - - TIM5_ETR, SPI3_MOSI/ I2S3_SDO, SPI1_NSS/I2S1_WS, SPI3_NSS/ I2S3_WS, USART2_CK, EVENTOUT ADC1_IN4, DAC1_OUT1 10 10 14 14 20 24 29 PA4 I/O TT_a STM32C562xx page 41/130 9 TIM2_CH4, TIM5_CH4, LPUART1_TX, TIM15_CH2, SPI2_NSS/I2S2_WS, SPI3_MOSI/ I2S3_SDO, USART2_RX, COMP1_OUT, EVENTOUT Pinouts/ballouts, pin description, and alternate functions UFQFPN32 Pin name (function after reset) LQFP32 DS14927 - Rev 1 Pin number 11 12 11 12 15 16 15 16 21 22 25 26 LQFP100 LQFP80 LQFP64 UFQFPN48 LQFP48 UFQFPN32 LQFP32 DS14927 - Rev 1 Pin number 30 31 Pin name (function after reset) PA5 PA6 Alternate functions Additional functions - TIM2_CH1, TIM1_CH3, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI2_SCK/I2S2_CK, USART1_CTS/ USART1_NSS, TIM2_ETR, EVENTOUT ADC1_IN5, COMP1_INM3 - TIM1_BKIN, TIM5_CH1, TIM8_BKIN, SPI1_MISO/ I2S1_SDI, USART1_TX, LPUART1_RTS, EVENTOUT ADC1_IN6 ADC1_IN7 Pin type I/O structure Notes I/O I/O FT_a FT_a 13 17 17 23 27 32 PA7 I/O FT_a - - - - - 24 28 33 PC4 I/O FT_a - TIM2_CH4, TIM8_BKIN, I2S1_MCK, USART3_RX, TIM16_CH1, EVENTOUT ADC2_IN4, COMP1_INM1 - - - - 25 29 34 PC5 I/O FT_a - TIM1_CH4N, TIM8_BKIN2, TIM16_CH1N, COMP1_OUT, EVENTOUT ADC2_IN5 14 14 18 18 26 30 35 PB0 I/O FT_a - TIM1_CH2N, TIM5_CH3, TIM8_CH2N, SPI3_MISO/ I2S3_SDI, USART2_TX, UART4_CTS, EVENTOUT ADC2_IN6, COMP1_INP2 - 15 19 19 27 31 36 PB1 I/O FT_a - TIM1_CH3N, TIM5_CH4, TIM8_CH3N, SPI3_SCK/I2S3_CK, SPI2_NSS/I2S2_WS, USART3_RX, COMP1_OUT, EVENTOUT ADC2_IN7, COMP1_INM2 ADC2_IN8, COMP1_INP3, LSCO - 20 20 28 32 37 PB2 I/O FT_a - - - - - - 33 38 PE7 I/O FT - TIM1_ETR, EVENTOUT - - - - - - 34 39 PE8 I/O FT - TIM1_CH1N, EVENTOUT - - - - - - 35 40 PE9 I/O FT - TIM1_CH1, EVENTOUT - - - - - - 36 41 PE10 I/O FT - TIM1_CH2N, EVENTOUT - - - - - - - 42 PE11 I/O FT - TIM1_CH2, SPI1_RDY, EVENTOUT - STM32C562xx page 42/130 - RTC_OUT2, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SPI2_SCK/I2S2_CK, SPI3_MOSI/ I2S3_SDO, EVENTOUT Pinouts/ballouts, pin description, and alternate functions 13 TIM1_CH1N, TIM5_CH2, TIM8_CH1N, TIM15_CH1, SPI1_MOSI/I2S1_SDO, SPI2_MISO/ I2S2_SDI, USART1_RX, LPUART1_CTS, EVENTOUT LQFP48 UFQFPN48 LQFP64 LQFP80 LQFP100 - - - - - 43 PE12 I/O FT - TIM1_CH3N, COMP1_OUT, EVENTOUT - - - - - - - 44 PE13 I/O FT - TIM1_CH3, EVENTOUT - - - - - - - 45 PE14 I/O FT - TIM1_CH4, EVENTOUT - - - - - - - 46 PE15 I/O FT - TIM1_BKIN, TIM1_CH4N, EVENTOUT - - - 21 21 29 37 47 PB10 I/O FT_f - TIM2_CH3, TIM8_CH1, LPTIM1_IN1, I2C2_SCL, SPI2_SCK/ I2S2_CK, USART3_TX, EVENTOUT - 15 16 22 22 30 38 48 VCAP S - - - - 16 - 23 23 31 39 49 VSS S - - - - 17 17 24 24 32 40 50 VDD S - - - - - TIM1_BKIN, TIM8_CH3, I2C2_SDA, SPI2_NSS/I2S2_WS, USART3_CK, FDCAN1_RX, UART5_RX, EVENTOUT - - TIM1_CH1N, TIM8_CH2, LPTIM1_CH1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/ USART3_NSS, LPUART1_RX, FDCAN1_TX, UART5_TX, EVENTOUT - - TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS, UART4_RTS, EVENTOUT - - - - - - - - 25 26 27 25 26 27 33 34 35 41 42 43 51 52 53 PB12 PB13 PB14 I/O I/O I/O FT_f FT FT Alternate functions Additional functions page 43/130 18 18 28 28 36 44 54 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/ I2S2_SDO, SPI1_MOSI/ I2S1_SDO, SPI3_MOSI/ I2S3_SDO, UART4_CTS, UART5_RX, EVENTOUT - - - - - - 55 PD8 I/O FT - USART3_TX, EVENTOUT - - - - - - - 56 PD9 I/O FT - USART3_RX, EVENTOUT - STM32C562xx - Pin type I/O structure Notes Pinouts/ballouts, pin description, and alternate functions UFQFPN32 Pin name (function after reset) LQFP32 DS14927 - Rev 1 Pin number LQFP48 UFQFPN48 LQFP64 LQFP80 LQFP100 - - - - - 57 PD10 I/O FT - MCO2, LPTIM1_CH2, USART3_CK, EVENTOUT - - - - - - - 58 PD11 I/O FT - LPTIM1_IN2, USART3_CTS/ USART3_NSS, UART4_RX, EVENTOUT - - - - - - 45 59 PD12 I/O FT - LPTIM1_IN1, TIM8_CH1N, I3C1_SCL, USART3_RTS, UART4_TX, EVENTOUT - - - - - - 46 60 PD13 I/O FT - LPTIM1_CH1, TIM8_CH2N, I3C1_SDA, EVENTOUT - - - - - - 47 61 PD14 I/O FT - TIM8_CH3N, EVENTOUT - - - - - - 48 62 PD15 I/O FT - TIM8_CH4N, EVENTOUT - - - - - 37 49 63 PC6 I/O FT - TIM5_CH1, TIM8_CH1, I2S2_MCK, EVENTOUT - - - - - 38 50 64 PC7 I/O FT - TIM5_CH2, TIM8_CH2, I2S3_MCK, EVENTOUT - - - - - 39 51 65 PC8 I/O FT - TRACED1, TIM5_CH3, TIM8_CH3, UART5_RTS, EVENTOUT - - - - - 40 52 66 PC9 I/O FT_f - MCO2, TIM5_CH4, TIM8_CH4, AUDIOCLK, UART5_CTS, I2C1_SDA, EVENTOUT - - MCO1, TIM1_CH1, I3C1_SDA, TIM8_BKIN2, TIM15_CH2, SPI1_RDY, SPI2_MOSI/ I2S2_SDO, USART1_CK, TIM5_CH4, I2C1_SCL, TIM2_CH4, EVENTOUT - - - 19 19 29 29 41 53 67 PA8 I/O FT_f Alternate functions Additional functions 20 20 30 30 42 54 68 PA9 I/O FT - MCO2, TIM1_CH2, I3C1_SCL, LPUART1_TX, TIM15_CH1N, SPI2_SCK/I2S2_CK, USART1_TX, TIM5_ETR, I2C1_SMBA, TIM8_CH2N, EVENTOUT - - 31 31 43 55 69 PA10 I/O FT - TIM1_CH3, LPUART1_RX, USART1_RX, EVENTOUT page 44/130 STM32C562xx - Pin type I/O structure Notes Pinouts/ballouts, pin description, and alternate functions UFQFPN32 Pin name (function after reset) LQFP32 DS14927 - Rev 1 Pin number 21 21 32 32 44 56 LQFP100 LQFP80 LQFP64 UFQFPN48 LQFP48 UFQFPN32 LQFP32 DS14927 - Rev 1 Pin number 70 Pin name (function after reset) PA11 Alternate functions Additional functions - TIM1_CH4, LPUART1_CTS, USART2_TX, SPI2_NSS/ I2S2_WS, UART4_RX, USART1_CTS/ USART1_NSS, I2C2_SCL, FDCAN1_RX, EVENTOUT USB_DM USB_DP Pin type I/O structure Notes I/O FT_fu 22 33 33 45 57 71 PA12 I/O FT_fu - 23 23 34 34 46 58 72 PA13 (JTMS/ SWDIO) I/O FT (3) JTMS/SWDIO, COMP1_OUT, EVENTOUT - - - - - - - 73 PH3 I/O FT - EVENTOUT - - - 35 35 47 59 74 VSS S - - - - - - 36 36 48 60 75 VDD S - - - - 24 24 37 37 49 61 76 PA14 (JTCK/ SWCLK) I/O FT (3) JTCK/SWCLK, EVENTOUT - - 25 38 38 50 62 77 PA15(JTDI) I/O FT (3) - - - - 51 63 78 PC10 I/O FT - TIM8_CH1N, I3C1_SCL, SPI3_SCK/ I2S3_CK, USART3_TX, UART4_TX, EVENTOUT - - - - - 52 64 79 PC11 I/O FT - TIM8_CH2N, I3C1_SDA, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, EVENTOUT - - - - - 53 65 80 PC12 I/O FT - TRACED3, TIM15_CH1, TIM8_CH3N, SPI3_MOSI/ I2S3_SDO, USART3_CK, UART5_TX, EVENTOUT - - - - - - 66 81 PD0 I/O FT - TIM8_CH4N, UART4_RX, FDCAN1_RX, EVENTOUT - STM32C562xx page 45/130 25 JTDI, TIM2_CH1, TIM1_CH2N, LPTIM1_ETR, I2C2_SMBA, SPI1_NSS/I2S1_WS, SPI3_NSS/ I2S3_WS, USART2_CK, UART4_RTS, USART1_TX, TIM8_CH4N, TIM2_ETR, EVENTOUT Pinouts/ballouts, pin description, and alternate functions 22 TIM1_ETR, LPUART1_RTS, USART2_RX, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, I2C2_SDA, FDCAN1_TX, EVENTOUT LQFP48 UFQFPN48 LQFP64 LQFP80 LQFP100 - - - - 67 82 PD1 I/O FT - UART4_TX, FDCAN1_TX, EVENTOUT - - - - - 54 68 83 PD2 I/O FT - TRACED2, TIM15_BKIN, UART5_RX, EVENTOUT WKUP7 - - - - - - 84 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS/ USART2_NSS, EVENTOUT - - - - - - - 85 PD4 I/O FT - USART2_RTS, EVENTOUT - - - - - - - 86 PD5 I/O FT - TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, EVENTOUT - - - - - - - 87 PD6 I/O FT - SPI3_MOSI/I2S3_SDO, USART2_RX, EVENTOUT - - - - - - - 88 PD7 I/O FT - SPI1_MOSI/I2S1_SDO, SPI3_MISO/ I2S3_SDI, USART2_CK, EVENTOUT - (3) JTDO/TRACESWO, TIM2_CH2, TIM5_CH3, I2C2_SDA, SPI1_SCK/ I2S1_CK, SPI3_SCK/I2S3_CK, LPUART1_TX, I2C2_SCL, CRS_SYNC, USART3_TX, TIM8_CH1, UART5_RTS, EVENTOUT - (3) NJTRST, TIM5_CH1, I3C1_SCL, LPTIM1_CH2, SPI1_MISO/ I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, LPUART1_CTS, I2C2_SDA, TIM16_BKIN, USART3_RX, TIM8_CH2, UART5_CTS, EVENTOUT - - TIM17_BKIN, TIM5_CH2, I3C1_SDA, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, SPI3_MOSI/ I2S3_SDO, LPUART1_RTS, FDCAN1_RX, USART3_CK, TIM8_CH3, UART5_RX, EVENTOUT - 26 27 28 26 27 28 39 40 41 39 40 41 55 56 57 69 70 71 89 90 91 PB3 (JTDO/ TRACESWO) PB4 (NJTRST) PB5 I/O I/O I/O FT_f FT_f FT Alternate functions Additional functions page 46/130 STM32C562xx - Pin type I/O structure Notes Pinouts/ballouts, pin description, and alternate functions UFQFPN32 Pin name (function after reset) LQFP32 DS14927 - Rev 1 Pin number 29 29 42 42 58 72 LQFP100 LQFP80 LQFP64 UFQFPN48 LQFP48 UFQFPN32 LQFP32 DS14927 - Rev 1 Pin number 92 Pin name (function after reset) PB6 Alternate functions Additional functions - I3C1_SCL, I2C1_SCL, SPI3_MISO/ I2S3_SDI, USART1_TX, LPUART1_TX, FDCAN1_TX, TIM16_CH1N, USART3_CTS/ USART3_NSS, TIM8_CH4, UART5_TX, EVENTOUT - WKUP5 Pin type I/O structure Notes I/O FT_f 30 43 43 59 73 93 PB7 I/O FT_f - - 31 44 44 60 74 94 PH2-BOOT0 I/O FT - MCO1, TIM17_CH1N, LPTIM1_IN2, FDCAN1_RX, EVENTOUT - 31 - - - - - - PB8-BOOT0 I/O FT_f - TIM17_CH1, I3C1_SCL, I2C1_SCL, SPI3_NSS/I2S3_WS, UART4_RX, FDCAN1_RX, EVENTOUT - - 32 45 45 61 75 95 PB8 I/O FT_f - TIM17_CH1, I3C1_SCL, I2C1_SCL, SPI3_NSS/I2S3_WS, UART4_RX, FDCAN1_RX, EVENTOUT - - - - 46 46 62 76 96 PB9 I/O FT - I3C1_SDA, I2C1_SDA, SPI2_NSS/ I2S2_WS, SPI3_SCK/I2S3_CK, UART4_TX, FDCAN1_TX, EVENTOUT - - - - - 77 97 PE0 I/O FT - LPTIM1_ETR, SPI3_RDY, FDCAN1_RX, EVENTOUT - - - - - - 78 98 PE1 I/O FT - LPTIM1_IN2, FDCAN1_TX, EVENTOUT - 32 - 47 47 63 79 99 VSS S - - - - 1 1 48 48 64 80 100 VDD S - - - - 1. After a RTC domain reset, PC13, PC14, and PC15 operate as GPIOs. Their function depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual 3. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. page 47/130 STM32C562xx 2. PC13 port toggling might disturbs low speed crystal connected on LSE PC14 and PC15. Refer to product Errata for more details. Pinouts/ballouts, pin description, and alternate functions 30 TIM17_CH1N, I3C1_SDA, I2C1_SDA, SPI3_SCK/I2S3_CK, USART1_RX, LPUART1_RX, FDCAN1_TX, TIM16_CH1, USART3_RTS, EVENTOUT DS14927 - Rev 1 4.3 Alternate functions Table 14. Alternate functions AF0 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I3C1/LPTIM1/ SPI1/I2S1/ SPI2/I2S2/ SPI3/ I2S3/SYS SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ UART4 SPI2/I2S2/ SPI3/I2S3/ USART1/2/3 I2C2/ LPUART1/ TIM5/UART4/5 FDCAN1/ I2C1/2/ SPI2/I2S2 CRS/TIM8/16 USART1/3 - TIM8 COMP/ TIM2/UART5 SYS SYS LPTIM1/ TIM1/2/17 I3C1/ TIM1/5/8/12/15 I3C1/LPTIM1/ LPUART1/ TIM1/5/8 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN SPI2_RDY SPI3_RDY USART2_CTS/ USART2_NSS UART4_TX SPI2_NSS/ I2S2_WS - - - - TIM2_ETR EVENTOUT PA1 - TIM2_CH2 TIM5_CH2 TIM8_BKIN TIM15_CH1N LPTIM1_IN1 - USART2_RTS UART4_RX - - - - - - EVENTOUT PA2 - TIM2_CH3 TIM5_CH3 LPUART1_RX TIM15_CH1 LPTIM1_IN2 - USART2_TX - - - - - - - EVENTOUT LPUART1_TX TIM15_CH2 SPI2_NSS/ I2S2_WS SPI3_MOSI/ I2S3_SDO USART2_RX - - - - - - COMP1_OUT EVENTOUT SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART2_CK - - - - - - - EVENTOUT PA3 Port A AF2 I2C1/2/I3C1/ LPTIM1/SPI1/ I2S1/SPI3/ I2S3/ TIM15/ USART1/2 Port - TIM2_CH4 TIM5_CH4 PA4 - - TIM5_ETR - SPI3_MOSI/ I2S3_SDO PA5 - TIM2_CH1 TIM1_CH3 TIM8_CH1N - SPI1_SCK/ I2S1_CK SPI2_SCK/ I2S2_CK USART1_CTS/ USART1_NSS - - - - - - TIM2_ETR EVENTOUT - USART1_TX LPUART1_RTS - - - - - - EVENTOUT - TIM1_BKIN TIM5_CH1 TIM8_BKIN - PA7 - TIM1_CH1N TIM5_CH2 TIM8_CH1N TIM15_CH1 SPI1_MOSI/ I2S1_SDO SPI2_MISO/ I2S2_SDI USART1_RX LPUART1_CTS - - - - - - EVENTOUT PA8 MCO1 TIM1_CH1 I3C1_SDA TIM8_BKIN2 TIM15_CH2 SPI1_RDY SPI2_MOSI/ I2S2_SDO USART1_CK TIM5_CH4 I2C1_SCL - - - - TIM2_CH4 EVENTOUT PA9 MCO2 TIM1_CH2 I3C1_SCL LPUART1_TX TIM15_CH1N SPI2_SCK/ I2S2_CK - USART1_TX TIM5_ETR I2C1_SMBA - - - TIM8_CH2N - EVENTOUT PA10 - TIM1_CH3 - LPUART1_RX - - - USART1_RX - - - - - - - EVENTOUT UART4_RX USART1_CTS/ USART1_NSS I2C2_SCL FDCAN1_RX - - - - - EVENTOUT PA11 - TIM1_CH4 - LPUART1_CTS USART2_TX SPI2_NSS/ I2S2_WS PA12 - TIM1_ETR - LPUART1_RTS USART2_RX SPI2_SCK/ I2S2_CK UART4_TX USART1_RTS I2C2_SDA FDCAN1_TX - - - - - EVENTOUT PA13 JTMS/SWDIO - - - - - - - - - - - - - COMP1_OUT EVENTOUT PA14 JTCK/SWCLK - - - - - - - - - - - - - - EVENTOUT I2C2_SMBA SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART2_CK UART4_RTS - - USART1_TX - TIM8_CH4N TIM2_ETR EVENTOUT - USART2_TX UART4_CTS - - - - - - EVENTOUT JTDI TIM2_CH1 TIM1_CH2N LPTIM1_ETR PB0 - TIM1_CH2N TIM5_CH3 TIM8_CH2N - SPI3_MISO/ I2S3_SDI PB1 - TIM1_CH3N TIM5_CH4 TIM8_CH3N SPI3_SCK/ I2S3_CK SPI2_NSS/ I2S2_WS - USART3_RX - - - - - - COMP1_OUT EVENTOUT SPI3_MOSI/ I2S3_SDO - - - - - - - EVENTOUT RTC_OUT2 - - TIM8_CH4N SPI1_RDY LPTIM1_CH1 PB3 JTDO/ TRACESWO TIM2_CH2 - TIM5_CH3 I2C2_SDA SPI1_SCK/ I2S1_CK SPI3_SCK/ I2S3_CK - LPUART1_TX I2C2_SCL CRS_SYNC USART3_TX - TIM8_CH1 UART5_RTS EVENTOUT SPI3_MISO/ I2S3_SDI SPI2_NSS/ I2S2_WS LPUART1_CTS I2C2_SDA TIM16_BKIN USART3_RX - TIM8_CH2 UART5_CTS EVENTOUT page 48/130 PB4 NJTRST - TIM5_CH1 I3C1_SCL LPTIM1_CH2 SPI1_MISO/ I2S1_SDI PB5 - TIM17_BKIN TIM5_CH2 I3C1_SDA I2C1_SMBA SPI1_MOSI/ I2S1_SDO - SPI3_MOSI/ I2S3_SDO LPUART1_RTS FDCAN1_RX - USART3_CK - TIM8_CH3 UART5_RX EVENTOUT PB6 - - - I3C1_SCL I2C1_SCL - SPI3_MISO/ I2S3_SDI USART1_TX LPUART1_TX FDCAN1_TX TIM16_CH1N USART3_CTS/ USART3_NSS - TIM8_CH4 UART5_TX EVENTOUT PB7 - TIM17_CH1N - I3C1_SDA I2C1_SDA - SPI3_SCK/ I2S3_CK USART1_RX LPUART1_RX FDCAN1_TX TIM16_CH1 USART3_RTS - - - EVENTOUT STM32C562xx PB2 SPI2_SCK/ I2S2_CK Pinouts/ballouts, pin description, and alternate functions PA6 SPI1_MISO/ I2S1_SDI PA15 Port B AF1 DS14927 - Rev 1 AF0 Port B AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I3C1/LPTIM1/ SPI1/I2S1/ SPI2/I2S2/ SPI3/ I2S3/SYS SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ UART4 SPI2/I2S2/ SPI3/I2S3/ USART1/2/3 I2C2/ LPUART1/ TIM5/UART4/5 FDCAN1/ I2C1/2/ SPI2/I2S2 CRS/TIM8/16 USART1/3 - TIM8 COMP/ TIM2/UART5 SYS SYS LPTIM1/ TIM1/2/17 I3C1/ TIM1/5/8/12/15 I3C1/LPTIM1/ LPUART1/ TIM1/5/8 PB8 - TIM17_CH1 - I3C1_SCL I2C1_SCL - SPI3_NSS/ I2S3_WS - UART4_RX FDCAN1_RX - - - - - EVENTOUT PB9 - - - I3C1_SDA I2C1_SDA SPI2_NSS/ I2S2_WS SPI3_SCK/ I2S3_CK - UART4_TX FDCAN1_TX - - - - - EVENTOUT - USART3_TX - - - - - - - EVENTOUT PB10 - TIM2_CH3 TIM8_CH1 LPTIM1_IN1 I2C2_SCL SPI2_SCK/ I2S2_CK PB12 - TIM1_BKIN TIM8_CH3 - I2C2_SDA SPI2_NSS/ I2S2_WS - USART3_CK - FDCAN1_RX - - - - UART5_RX EVENTOUT PB13 - TIM1_CH1N TIM8_CH2 LPTIM1_CH1 I2C2_SMBA SPI2_SCK/ I2S2_CK - USART3_CTS/ USART3_NSS LPUART1_RX FDCAN1_TX - - - - UART5_TX EVENTOUT PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX SPI2_MISO/ I2S2_SDI - USART3_RTS UART4_RTS - - - - - - EVENTOUT PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI2_MOSI/ I2S2_SDO SPI1_MOSI/ I2S1_SDO SPI3_MOSI/ I2S3_SDO UART4_CTS - - - - - UART5_RX EVENTOUT PC0 - - - - - - - SPI2_RDY - - TIM16_BKIN - - - - EVENTOUT PC1 TRACED0 - - - - SPI2_MOSI/ I2S2_SDO - - - - - - - - - EVENTOUT PC2 PWR_CSLEEP TIM17_CH1 - - - SPI2_MISO/ I2S2_SDI - - - - - - - - - EVENTOUT LPUART1_TX - SPI2_MOSI/ I2S2_SDO - - - - - - - - - EVENTOUT PC3 PWR_CSTOP - - PC4 PC5 - TIM2_CH4 - TIM8_BKIN - I2S1_MCK - USART3_RX - - TIM16_CH1 - - - - EVENTOUT - TIM1_CH4N - TIM8_BKIN2 - - - - - - TIM16_CH1N - - - COMP1_OUT EVENTOUT PC6 - - TIM5_CH1 TIM8_CH1 - I2S2_MCK - - - - - - - - - EVENTOUT PC7 - - TIM5_CH2 TIM8_CH2 - - I2S3_MCK - - - - - - - - EVENTOUT PC8 TRACED1 - TIM5_CH3 TIM8_CH3 - - - - UART5_RTS - - - - - - EVENTOUT PC9 MCO2 - TIM5_CH4 TIM8_CH4 - AUDIOCLK - - UART5_CTS I2C1_SDA - - - - - EVENTOUT - SPI3_SCK/ I2S3_CK USART3_TX UART4_TX - - - - - - EVENTOUT USART3_RX UART4_RX - - - - - - EVENTOUT PC10 - - - TIM8_CH1N I3C1_SCL - - - TIM8_CH2N I3C1_SDA - PC12 TRACED3 - TIM15_CH1 TIM8_CH3N - - SPI3_MOSI/ I2S3_SDO USART3_CK UART5_TX - - - - - - EVENTOUT PC13 - - - - - - - - - FDCAN1_TX - - - - - EVENTOUT PC14 - - TIM12_CH1 - - - - - - FDCAN1_RX - - - - - EVENTOUT PC15 - - TIM12_CH2 - - - - - - - - - - - - EVENTOUT PD0 - - - TIM8_CH4N - - - - UART4_RX FDCAN1_RX - - - - - EVENTOUT PD1 - - - - - - - - UART4_TX FDCAN1_TX - - - - - EVENTOUT PD2 TRACED2 - - - TIM15_BKIN - - - UART5_RX - - - - - - EVENTOUT SPI2_SCK/ I2S2_CK - USART2_CTS/ USART2_NSS - - - - - - - EVENTOUT page 49/130 PD3 - PD4 PD5 PD6 - - - - - - - - - - - USART2_RTS - - - - - - - EVENTOUT - TIM1_CH4N - - - SPI2_RDY - USART2_TX - FDCAN1_TX - - - - - EVENTOUT - SPI3_MOSI/ I2S3_SDO - USART2_RX - - - - - - - EVENTOUT - - - - STM32C562xx PC11 SPI3_MISO/ I2S3_SDI Pinouts/ballouts, pin description, and alternate functions Port C AF2 I2C1/2/I3C1/ LPTIM1/SPI1/ I2S1/SPI3/ I2S3/ TIM15/ USART1/2 Port Port D AF1 DS14927 - Rev 1 AF0 Port D AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I3C1/LPTIM1/ SPI1/I2S1/ SPI2/I2S2/ SPI3/ I2S3/SYS SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ UART4 SPI2/I2S2/ SPI3/I2S3/ USART1/2/3 I2C2/ LPUART1/ TIM5/UART4/5 FDCAN1/ I2C1/2/ SPI2/I2S2 CRS/TIM8/16 USART1/3 - TIM8 COMP/ TIM2/UART5 SYS USART2_CK - - - - - - - EVENTOUT SYS LPTIM1/ TIM1/2/17 I3C1/ TIM1/5/8/12/15 I3C1/LPTIM1/ LPUART1/ TIM1/5/8 PD7 - - - - - SPI1_MOSI/ I2S1_SDO SPI3_MISO/ I2S3_SDI PD8 - - - - - - - USART3_TX - - - - - - - EVENTOUT PD9 - - - - - - - USART3_RX - - - - - - - EVENTOUT PD10 MCO2 LPTIM1_CH2 - - - - - USART3_CK - - - - - - - EVENTOUT PD11 - LPTIM1_IN2 - - - - - USART3_CTS/ USART3_NSS UART4_RX - - - - - - EVENTOUT PD12 - LPTIM1_IN1 - TIM8_CH1N - I3C1_SCL - USART3_RTS UART4_TX - - - - - - EVENTOUT PD13 - LPTIM1_CH1 - TIM8_CH2N - I3C1_SDA - - - - - - - - - EVENTOUT PD14 - - - TIM8_CH3N - - - - - - - - - - - EVENTOUT PD15 - - - TIM8_CH4N - - - - - - - - - - - EVENTOUT PE0 - LPTIM1_ETR - - - - SPI3_RDY - - FDCAN1_RX - - - - - EVENTOUT PE1 - LPTIM1_IN2 - - - - - - - FDCAN1_TX - - - - - EVENTOUT SPI3_SCK/ I2S3_CK - - - - - - - - - EVENTOUT PE2 TRACECLK LPTIM1_IN2 - - - PE3 TRACED0 - - - TIM15_BKIN - - USART1_RX - - - - - - - EVENTOUT TIM15_CH1N SPI3_NSS/ I2S3_WS - USART1_TX - - - - - - - EVENTOUT - USART1_CK - - - - - - - EVENTOUT PE4 Port E AF2 I2C1/2/I3C1/ LPTIM1/SPI1/ I2S1/SPI3/ I2S3/ TIM15/ USART1/2 Port TRACED1 - - - TRACED2 - - - TIM15_CH1 PE6 TRACED3 TIM1_BKIN2 - - TIM15_CH2 SPI3_MOSI/ I2S3_SDO - USART1_CTS/ USART1_NSS - - - - - - - EVENTOUT PE7 - TIM1_ETR - - - - - - - - - - - - - EVENTOUT PE8 - TIM1_CH1N - - - - - - - - - - - - - EVENTOUT PE9 - TIM1_CH1 - - - - - - - - - - - - - EVENTOUT PE10 - TIM1_CH2N - - - - - - - - - - - - - EVENTOUT PE11 - TIM1_CH2 - - SPI1_RDY - - - - - - - - - - EVENTOUT PE12 - TIM1_CH3N - - - - - - - - - - - - COMP1_OUT EVENTOUT PE13 - TIM1_CH3 - - - - - - - - - - - - - EVENTOUT PE14 - TIM1_CH4 - - - - - - - - - - - - - EVENTOUT PE15 - TIM1_BKIN - TIM1_CH4N - - - - - - - - - - - EVENTOUT PH0 - - - - I2C1_SDA - - - - - - - - - - EVENTOUT PH1 - - - - I2C1_SCL - - - - - - - - - - EVENTOUT PH2 MCO1 TIM17_CH1N - LPTIM1_IN2 - - - - - FDCAN1_RX - - - - - EVENTOUT PH3 - - - - - - - - - - - - - - - EVENTOUT PH4 - - - - - - - - - - - - - - - EVENTOUT PH5 - - - - - - - - - - - - - - - EVENTOUT PH15 - - - - - - - USART1_RTS - - - - - - - EVENTOUT page 50/130 STM32C562xx PE5 SPI3_MISO/ I2S3_SDI Pinouts/ballouts, pin description, and alternate functions Port H AF1 STM32C562xx Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 2.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage Device pin Device pin VIN DS14927 - Rev 1 DT47494V1 DT47493V1 C = 50 pF page 51/130 STM32C562xx Electrical characteristics 5.1.6 Power supply scheme Each power supply pair must be decoupled with filtering ceramic capacitors as shown in the following figures. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the proper functionality of the device. Figure 12. STM32C562xx power supply scheme Backup circuitry (LSE, RTC, TAMP backup registers) VCAP 2.2 µF VDD VCORE n x VDD LDO regulator OUT GPIOs 4.7 μF + n x 100 nF IN VREF 100 nF I/O logic Kernel logic (CPU, digital and memories) VDDA VREF+ VREF- ADCs/ DAC/ COMP VSSA DT76076V2 n x VSS Level shifter VDDIO1 VCORE The external capacitor on VCAP pin requires the following characteristics: • • • DS14927 - Rev 1 COUT = 2.2 μF COUT ESR < 20 mΩ at 3 MHz COUT rated voltage ≥ 10 V page 52/130 STM32C562xx Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 15, Table 16, and Table 17 may damage permanently the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard. Extended mission profiles are available on demand. Table 15. Voltage characteristics All main power (VDD) and ground (VSS) pins must always be connected to the external power supply, in the permitted range. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance, TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O. Symbols VDDX - VSS VIN(1) VREF+-VDDA |∆VDDX| |VSSx-VSS| Ratings Min Max Unit −0.3 4.0 V Input voltage on FT_xxx pins VSS−0.3 MIN (VDD + 4.0V , 6.0 V)(2) V Input voltage on TT_xx pins VSS−0.3 4.0 V Allowed voltage difference for VREF+ > VDDA - 0.4 V Variations between different VDDX power pins of the same domain - 50.0 mV Variations between all the different ground pins - 50.0 mV External main supply voltage (including VDD, VDDA and VREF+) 1. VIN maximum must always be respected. Refer to Table 16 for the maximum allowed injected current values. 2. When the analog option is selected by enabling analog peripheral or the pull-up/pull-down resistors are enabled on a given pin, VIN must not exceed 4 V. Table 16. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 200 ∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200 IVDD Maximum current into each VDD power pin (source)(1) 100 IVSS (sink)(1) 100 IIO ∑I(PIN) IINJ(PIN)(3)(4) ∑IINJ(PIN) Maximum current out of each VSS ground pin Output current sunk by any I/O and control pin 20 Output current sourced by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(2) 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xx, TT_xx, RST pins -5/0 Total injected current (sum of all I/Os and control pins)(5) ±25 Unit mA 1. All main power (VDD) and ground (VSS) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages. 3. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 15 for the minimum allowed input voltage values. 4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the negative injected currents (instantaneous values). DS14927 - Rev 1 page 53/130 STM32C562xx Electrical characteristics Table 17. Thermal characteristics Symbol TSTG Ratings Value Storage temperature range TJ Unit -65 to +150 Maximum junction temperature °C 150 5.3 Operating conditions 5.3.1 General operating conditions Table 18. General operating conditions Symbol Parameter Operating conditions Min Typ Max VDD/VDDA Standard operating voltage - 2.7(1) - 3.6 I/O Input voltage All I/O except TT_xx VSS−0.3 - MIN (VDD + 3.6V , 5.5 V)(2) TT_xx I/O VSS−0.3 - VDD + 0.3 RUN, SLEEP, STOP0 Modes 1.15 1.20 1.26 STOP1 Mode 0.9 0.95 1.0 VIN VCAP Internal regulator ON fHCLK AHB clock frequency - - - 144 fPCLK APB clock frequency - - - 144 PD Power dissipation at TA = 85 °C for suffix 6(3) Power dissipation at TA = 125 °C for suffix 3(3) V MHz See Section 6.9: Package thermal characteristics for application appropriate thermal resistance and package. Power dissipation is then calculated according ambient temperature (TA) and maximum junction temperature (TJ) and selected thermal resistance. Ambient temperature for suffix 3 version - -40 - 125 Ambient temperature for suffix 6 version - -40 - 85 Junction temperature range for suffix 3 version - -40 - 140 Junction temperature range for suffix 6 version. - -40 - 105 TA TJ - Unit mW °C °C 1. When RESET is released, the functionality is guaranteed down to PDR minimum voltage. 2. For operation with voltage higher than VDD + 0.3 V, the internal pull‑up and pull‑down resistors must be disabled. The minimum and maximum input voltage (Vin) must comply with the selected peripheral enabled on the given GPIOs. Refer to the respective peripheral characteristics for details. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.9: Package thermal characteristics). DS14927 - Rev 1 page 54/130 STM32C562xx Electrical characteristics 5.3.2 Operating conditions at power-up/power-down The parameters given in the table below are derived from tests performed under the ambient temperature condition summarized in Table 18. Table 19. Operating conditions at power-up/power-down Symbol tVDD 5.3.3 Parameter Min Max Unit VDD rise‑time rate 0 ∞ µs/V VDD fall‑time rate 0 ∞ ms/V Embedded reset and power control block characteristics The parameters given in the table below are derived from tests performed under the ambient temperature conditions summarized in Table 18. Table 20. Embedded reset and power control block characteristics The values in this table are evaluated by characterization - Not tested in production, unless otherwise specified. Symbol Parameter tRSTTEMPO(1)(2) VPOR/PDR Reset temporization after POR released Power-on/power-down reset threshold (BORH_EN =0) Conditions Min Typ Max Unit VDD rising - - 463 µs Rising edge 2.56 2.61 2.64 Falling edge 2.53 2.58 2.61 Rising edge 3.00 3.04 3.08 Falling edge 2.89 2.93 2.96 VPVD Programmable Voltage Detector threshold Vhyst_POR_PDR Hysteresis for power-on/power-down reset - - 30 - Vhyst_PVD Hysteresis voltage of PVD - - 110 - IDD_PVD(2) PVD consumption from VDD - - - 0.63 V mV µA 1. Specified by design - Not tested in production. 2. From POR threshold crossing to NRST pull-up resistor activation. 5.3.4 Inrush current and inrush electric charge characteristics The parameters provided in the following table are specified by design simulation and are not tested in production. Table 21. Embedded internal voltage reference The typical values are provided for VDD = 3.3V and for a typical decoupling capacitor value . The product consumption on VDDCORE is not included in the inrush current and inrush electric charge Symbol Parameter Typ Unit IRUSH Inrush current during voltage regulator power-on (POR) or wake-up from standby 35 mA QRUSH Inrush electric charge during voltage regulator power-on (POR) or wake-up from standby. 2.8 µC DS14927 - Rev 1 page 55/130 STM32C562xx Electrical characteristics 5.3.5 Embedded voltage reference The parameters provided in Table 22. Embedded internal voltage reference are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Section 5.3.1. Table 22. Embedded internal voltage reference The values in this table are specified by design and not tested in production. Symbol VREFINT tS_vrefint(1)(2) Parameter Conditions -40°C < TJ < 140 °C Internal reference voltages ADC sampling time when reading the internal reference voltage Reference Buffer consumption for ADC ΔVREFINT (2) Internal reference voltage spread over the temperature range Tcoeff VDDcoeff Average temperature coefficient Average Voltage coefficient Typ Max Unit 1.180 1.217 1.250 V - 4.3 - - µs - - - 4.4 µs VDDA = 3.3 V 9 13.5 23 µA -40 °C < TJ < 140 °C - 5 15 mV Average temperature coefficient - 19 67 ppm/°C 3.0 V < VDD < 3.6 V - 10 1370 ppm/V tstart_vrefint (2) Start time of reference voltage buffer when ADC is enable Irefbuf (2) Min 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Specified by design - Not tested in production. Table 23. Internal reference voltage calibration values Symbol Parameter VREFINT_CAL 5.3.6 Raw data acquired at temperature of 30 °C, VDDA = 3.3 V Memory address 0x08FFF810 - 0x08FFF811 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Current consumption measurement. Typical and maximum current consumption The MCU is placed under the following conditions: • • • • All I/O pins are in analog input mode. All peripherals are disabled except when explicitly mentioned. The flash memory access time is adjusted with the minimum wait-state number, depending on the fHCLK frequency (refer to the tables Number of wait states according to CPU clock (HCLK) frequency available in the product reference manual). When the peripherals are enabled, fPCLK = fHCLK. The parameters given in the tables below are derived from tests performed under ambient temperature and supply voltage conditions summarized in Section 5.3.1: General operating conditions. If not specified otherwise, typical data are measured with a VDD supply of 3.0 V, and maximum data are measured at 3.6 V. DS14927 - Rev 1 page 56/130 STM32C562xx Electrical characteristics 5.3.6.1 Current consumption in Run mode Table 24. Typical and maximum current consumption in Run mode Evaluated by characterization - not tested in production, unless otherwise stated. Clocked by HSI at 144MHz of HSIDIV3 at 48MHz if not otherwise specified. Symbol Parameter Conditions IDD(Run)(1) TJ = 30°C TJ = 90°C TJ = 110°C TJ = 130°C TJ = 140°C 144 11.5 12.00 13.50 14.50 17.00 18.50 48 4.1 4.35 5.75 7.15 9.45 11.00 144 9.4 10.00 11.50 12.50 15.00 16.50 48 4.0 4.35 5.70 7.05 9.35 11.00 144 9.3 9.80 11.00 12.50 15.00 16.50 48 3.4 3.60 5.05 6.40 8.70 10.50 23.5 24.50 25.50 27.00 29.50 31.50 21.0 22.50 23.50 25.00 27.50 29.00 Code in Flash, ICACHE OFF Code in SRAM2, ICACHE OFF, FLASH ON Supply current in Run mode all peripheral clocks enabled unit Typ Code in Flash, ICACHE 2Ways Supply current in Run mode all peripheral clocks disabled Max fHCLK (MHz) Code in Flash, ICACHE 2Ways 144(2) Code in Flash, ICACHE OFF mA 1. Measures done with prefetch enabled. 2. Clocked by PSI at 144 MHz with HSE at 16 MHz in bypass mode. Table 25. Typical current consumption in Run mode with CoreMark running from flash memory and SRAM Evaluated by characterization - not tested in production, unless otherwise stated. Symbol IDD(Run)(1) Conditions Parameter SYSCLK source Peripheral Supply current in Run mode fHCLK (MHz) Typ Unit Typ Code in Flash, ICACHE 2-WAY, prefetch ON 12.00 82.00 Code in Flash, ICACHE 1-WAY, prefetch ON 9.85 68.50 Code in Flash, ICACHE OFF, prefetch ON 9.45 65.50 Code in Flash, ICACHE OFF, prefetch OFF PSI (2) 144 8.40 mA Unit 58.50 µA/ MHz Code in SRAM2, ICACHE 2-WAY 11.50 78.00 Code in SRAM2, ICACHE 1-WAY 9.35 65.00 Code in SRAM2, ICACHE OFF 9.15 63.50 1. Measures done with prefetch enabled. 2. Clocked by PSI 144MHz with HSE at 16 MHz on bypass mode. 5.3.6.2 Current consumption in Sleep mode Table 26. Typical and maximum current consumption in Sleep mode Evaluated by characterization - Not tested in production. Clocked by HSI at 144MHz of HSIDIV3 at 48MHz. Symbol IDD(SLEEP) Parameter Supply current in Sleep mode DS14927 - Rev 1 Max fHCLK (MHz) Typ TJ = 30 °C TJ = 90 °C TJ = 110 °C TJ = 130 °C TJ = 140 °C All peripheral clocks disabled 144 2.05 2.35 3.95 5.50 8.05 10.00 48 0.93 1.15 2.80 4.35 6.95 8.85 All peripheral clocks enabled 144 15.00 15.50 17.00 18.50 21.00 22.50 48 5.30 5.60 7.00 8.40 11.00 12.50 Conditions Unit mA page 57/130 STM32C562xx Electrical characteristics 5.3.6.3 Current consumption in Stop mode Table 27. Typical and maximum current consumption in Stop mode Evaluated by characterization - not tested in production, unless otherwise stated. Symbol Parameter FLASH ON Conditions SRAM1/2 ON IDD(STOP) SRAM1/2 ON FLASH IN LOW POWER SRAM1/2 Powered Down Typ Max TJ = 30 °C TJ = 90 °C TJ = 110 °C TJ = 130 °C TJ = 140 °C STOP0 0.19 0.34 1.60 2.80 4.80 6.15 STOP1 0.06 0.14 0.93 1.70 3.05 3.90 STOP0 0.17 0.32 1.60 2.75 4.75 6.10 STOP1 0.05 0.13 0.92 1.70 3.05 3.85 STOP0 0.17 0.31 1.55 2.65 4.55 5.90 STOP1 0.05 0.12 0.82 1.50 2.70 3.55 Unit mA Table 28. Typical and maximum HSIKERON current consumption in Stop mode Evaluated by characterization - not tested in production, unless otherwise stated. Symbol IDD(Stop) Parameter Conditions FLASH IN LOW POWER 5.3.6.4 HSIKERON, STOP0 Typ Max TJ = 30 °C TJ = 90 °C TJ = 110 °C TJ = 130 °C TJ = 140 °C HSI144 0.49 0.63 1.85 3.00 4.90 6.20 HSI48 0.52 1.75 2.90 4.80 6.10 0.38 Unit mA Current consumption in Standby mode Table 29. Typical and maximum current consumption in Standby mode Evaluated by characterization - not tested in production, unless otherwise stated. Symbol IDD(Standby) Parameter RTC and LSE(1) Typ Max 3.3 V TJ = 30 °C TJ = 90 °C TJ = 110 °C TJ = 130 °C TJ = 140 °C Supply current in Standby OFF mode, IWDG OFF ON 2.75 2.90 3.00 3.80 9.90 18.00 36.50 51.00 3.10 3.25 3.40 - - - - - Supply current in Standby OFF mode, IWDG ON ON 3.10 3.25 3.40 5.10 10.00 18.00 37.00 51.00 3.40 3.55 3.75 - - - - - 2.7 V 3V Unit μA 1. LSE is in bypass mode at 32.768 KHz. DS14927 - Rev 1 page 58/130 STM32C562xx Electrical characteristics 5.3.6.5 Current consumption from peripherals Table 30. Peripheral current consumption measured in Sleep mode Bus AHB1 AHB2 APB1 APB2 DS14927 - Rev 1 Peripheral IDD(Typ) SRAM1 0.22 RAMCFG 0.70 ICACHE 0.20 CRC 0.70 FLASH 6.26 LPDMA1 1.22 LPDMA2 1.09 SRAM2 0.37 RNG 0.78 HASH 0.69 AES 0.92 DAC1 0.92 ADC12 5.51 GPIOA 0.07 GPIOB 0.07 GPIOC 0.09 GPIOD 0.07 GPIOE 0.08 GPIOH 0.06 FDCAN1 4.86 CRS 0.23 I2C1 1.97 I2C2 2.00 I3C1 0.28 UART4 3.47 UART5 3.43 USART2 3.69 USART3 3.62 COMP 0.19 SPI2/I2S2 1.59 SPI3/I2S3 1.50 WWDG 0.14 TIM2 0.28 TIM5 0.31 TIM6 0.26 TIM7 0.29 TIM12 0.27 USB 2.11 Unit µA/MHz µA/MHz µA/MHz µA/MHz page 59/130 STM32C562xx Electrical characteristics Bus APB2 APB3 DS14927 - Rev 1 Peripheral IDD(Typ) USART1 3.39 SPI1/I2S1 1.50 TIM1 0.30 TIM8 0.32 TIM15 0.33 TIM16 0.31 TIM17 0.34 RTC 3.47 LPTIM1 0.78 LPUART 2.68 SBS 0.32 Unit µA/MHz µA/MHz page 60/130 STM32C562xx Electrical characteristics 5.3.7 Wake-up time from low-power modes and voltage scaling transition times The wake-up times given in the table below are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (wait for event) instruction Table 31. Wake-up time from low-power modes 1. Evaluated by characterization - Not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. Symbol twu(Sleep) Wakeup from Sleep Wakeup from Stop 0 twu(Stop) Wakeup from Stop 1(1) twu(Standby) Wakeup clock fHCLK (MHz) Typ Max Unit - - 16 CPU clock cycles Flash memory in normal mode HSI 144 3.6 5 Flash memory in low-power mode HSI 144 7.2 11 Flash memory in normal mode HSIDIV3 48 5.1 7 Flash memory in low-power mode HSIDIV3 48 8.6 13.5 Flash memory in normal mode HSI 144 37.0 49 Flash memory in low-power mode HSI 144 40.5 58 Flash memory in normal mode HSIDIV3 48 39.0 53 Flash memory in low-power mode HSIDIV3 48 42.0 61 HSIDIV3 48 445 - Parameter Conditions Instruction cache enabled or disabled Wakeup from Standby mode(1) - µs 1. Those parameters depend on VCAP capacitance value and VCAP voltage at the instant of the wake-up event. Table 32. Wake-up time using USART/LPUART Symbol Parameter Condition tWUUSART/ Wake-up time needed to calculate the maximum USART/LPUART baudrate allowing to wake tWULPUART up from Stop mode when USART/LPUART clock source is 48 MHz by HSIDIV3 Stop 0 mode Stop 1 mode Typ Max(1) Unit 4.8 6.6 µs 1. Specified by design - Not tested in production. 5.3.8 External clock timing characteristics 5.3.8.1 High-speed external user clock generated from an external source In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in I/O port characteristics. However, the recommended clock input waveform is shown in the figure below. Table 33. High-speed external user clock characteristics Specified by design and not tested in production. Symbol Parameter fHSE_ext User external clock source frequency VHSEH OSC_IN input pin high-level voltage DS14927 - Rev 1 Conditions Min Typ Max Digital mode (HSEYBYP = 1, HSEEXT = 1) - - 50 Analolog mode (HSEYBYP = 1, HSEEXT = 0) 4 - 50 Digital mode (HSEYBYP = 1, HSEEXT = 1) 0.7 × VDD - VDD Unit MHz V page 61/130 STM32C562xx Electrical characteristics Symbol Parameter VHSEL tw(HSEH)(1) tw(HSEL)(1) DuCyHSE VHSE_ext_PP (2) VHSE_ext tr(HSE), tf(HSE) Conditions Min Typ Max Unit OSC_IN input pin low-level voltage Digital mode (HSEYBYP = 1, HSEEXT = 1) VSS - 0.3 × VDD V OSC_IN high or low time Digital mode (HSEYBYP = 1, HSEEXT = 1) 7 - - ns OSC_IN duty cycle Digital mode (HSEYBYP = 1, HSEEXT = 1) 45 - 55 % 0.2 - 2/3 VDD 0 - VDD 0.05 / fext_ext - 0.3 / fext_ext OSC_IN peak-to-peak amplitude OSC_IN input range Analog mode (HSEBYP = 1, HSEEXT = 0) OSC_IN rise and fall time V ns 1. There is no specified rise and fall time for a digital input signal, but the VHSEH and VHSEL conditions must be fulfilled . 2. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS. Figure 13. AC timing diagram for high-speed external clock source (digital mode) VHSE tw(HSEH) VHSEH 70% 30% t tw(HSEL) THSE DT67850V3 VHSEL Figure 14. AC timing diagram for high-speed external clock source (analog mode) VHSE_ext 90% VHSE_ext_PP tf(HSE) tr(HSE) tHSE_ext = 1/fHSE_ext DS14927 - Rev 1 t DT71538V1 10% page 62/130 STM32C562xx Electrical characteristics 5.3.8.2 Low-speed external user clock generated from an external source In bypass mode, the LSE oscillator is switched off and the input pin is directly connected to the LSE clock detector (LSECSS). The external clock signal has to respect the parameters specified in Table 34, as shown also by the waveforms in Figure 15. Table 34. Low-speed external user clock characteristics Specified by design and not tested in production. Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User external clock source frequency External digital/analog clock - 32.768 1000 kHz VLSEH Digital OSC_IN input high level External digital clock 0.7 VDD - VDD VLSEL OSC32_IN input pin low level voltage External digital clock VSS - 0.3 VDD OSC32_IN high or low time External digital clock 250 - - tw(LSEH)/tw(LSEL) Vlsw_H Analog low swing OSC_IN high level External analog low swing clock 0.6 1.225 Vlsw_L Analog low swing OSC_IN low level External analog low swing clock 0.35 0.8 VlswLSE (VLSEH VLSEL) Analog low swing OSC_IN peak-topeak amplitude External analog low swing clock 0.2 0.875 V ns V DuCyLSE Analog low swing OSC_IN duty cycle External analog Low Swing Clock 45 50 55 % trLSE/tfLSE Analog low swing OSC_IN rise and fall time Externala analog low swing clock 10 % to 90 % - 100 200 ns t W(LSE) t Figure 15. Low-speed external clock source AC timing diagram VLSEH VLSEL 90 % 10 % t r(LSE) t f(LSE) t W(LSE) External clock source f LSE_ext OSC32 _IN IL STM32 DS14927 - Rev 1 DT17529V1 TLSE page 63/130 STM32C562xx Electrical characteristics 5.3.8.3 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in the table below. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins, in order to minimize the output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 35. 4-50 MHz HSE oscillator characteristics Specified by design and not tested in production. Symbol F RF Operating conditions(1) Min Typ Max Unit Oscillator frequency - 4 - 50 MHz Feedback resistor - - 200 - kΩ startup(2) - - 10 VDD = 3 V, Rm = 20 Ω CL=10 pF at 4 MHz - 0.4 - VDD=3 V, Rm = 20 Ω CL = 10 pF at 8 MHz - 0.4 - VDD = 3 V, Rm = 20 Ω CL = 10 pF at 16 MHz - 0.6 - VDD = 3 V, Rm = 20 Ω CL = 10 pF at 32 MHz - 0.7 - VDD = 3 V, Rm = 20 Ω CL=10 pF at 48 MHz - 1.2 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During IDD(HSE) Gmcritmax tSU(3) HSE current consumption Maximum critical crystal gm Start-up time mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note 'Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs' (AN2867). Figure 16. Typical application with a 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator REXT (1) RF Bias controlled gain OSC_OUT DT19876V1 CL2 fHSE (1): REXT value depends on the crystal characteristics. DS14927 - Rev 1 page 64/130 STM32C562xx Electrical characteristics 5.3.8.4 Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in the table below. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 36. LSE oscillator characteristics (fLSE = 32.768 kHz) Specified by design and not tested in production. Symbol F Operating conditions(1) Min Typ Max Unit - - 32.768 - kHz LSEDRV[1:0] = 00, Low drive capability - 246 - LSEDRV[1:0] = 01, Medium low drive capability - 333 - LSEDRV[1:0] = 10, Medium high drive capability - 462 - LSEDRV[1:0] = 11, High drive capability - 747 - LSEDRV[1:0] = 00, Low drive capability - - 0.5 LSEDRV[1:0] = 01, Medium low drive capability - - 0.75 LSEDRV[1:0] = 10, Medium high drive capability - - 1.7 LSEDRV[1:0] = 11, High drive capability - - 2.7 VDD is stabilized - 2 - Parameter Oscillator frequency LSE current consumption IDD Gmcritmax tSU (2) Maximum critical crystal Gm Startup time nA µA/V s 1. Refer to the following note and caution paragraphs, and to the application note AN2867 “Oscillator design guide for ST microcontrollers. 2. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note 'Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs' (AN2867). Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.768 kHz resonator Drive programmable amplifier CS OSC32_OUT DT70418V1 CL2 fLSE Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance. Note: DS14927 - Rev 1 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. page 65/130 STM32C562xx Electrical characteristics 5.3.9 Internal clock timing characteristics The parameters given in the tables below are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 18. The curves provided are characterization results, not tested in production. 5.3.9.1 High-speed internal HSI144 oscillator Table 37. HSI144 oscillator characteristics Symbol Parameter Conditions Min Typ fHSI(1) HSI frequency VDD = 3.3 V, TJ = 30 °C 144.07 - TRIM(2) USER trimming step - - 0.1 0.15 USER TRIM COVERAGE(2) USER TRIMMING Coverage positive 80 steps 5.2% 8% - USER TRIMMING Coverage negative 48 steps -3.1% -4.8% - DuCy(HSI)(2) Duty Cycle - 45 ΔTEMP (HSI)(3) HSI oscillator frequency drift over temperature (the reference is 144 MHz.) TJ = -20 to 130 °C -1 - 1 TJ = −40 to TJmax °C -1.5 - 1.5 ΔVDD(HSI)(2)(4) HSI oscillator frequency drift with VDDSection 5.3.9.1: High-speed internal HSI144 oscillator (5)(the reference is 3.3V) VDD from 2.7 V to 3.6 V - - - 0.1 HSI oscillator start-up time (PSI Off) - - 3 4.5 HSI oscillator start-up time (PSI On) - - 0.5 - - - 8 - - 0.7 tsu(HSI)(3) tstab stabilization time (PSI OFF from Enable) (2) IDD(HSI)(2)(6) stabilization time (PSI ON from Enable) 55 - - 91 - HSI oscillator power consumption - - 28 - - 52 322 - 62 394 Next transition jitter(7). PT jitter(2) Paired transition jitter(8) jitter(2) Period Jitter standard deviation Unit 145.08 MHz HSI supply regulation block oscillator power consumption NT jitter(2) Per +/-1% of target freq Max % µs µA On HSIDIV3 On HSIS 15 On HSIDIV3 26 ps 1. Tested in production. 2. Specified by design - Not tested in production. 3. Evaluated by characterization - Not tested in production. 4. ΔfHSI = ΔTEMP + ΔVDD 5. These values are obtained by using formula: (Freq(3.6 V) - Freq(3.3 V)) / Freq(3.3 V) or (Freq(3.6 V) - Freq(2.7 V)) / Freq(2.7 V). 6. The supply regulation consumption is common to HSI and PSI. (To be counted once if both oscillators are ON). 7. Jitter measurements are performed without clock source activated in parallel. Typical value is standard deviation, Maximum is peak measure on TIE-8 over 36 cycles. 8. Jitter measurements are performed without clock source activated in parallel. Typical value is standard deviation, Maximum is peak measure on TIE-16 over 36 cycles. DS14927 - Rev 1 page 66/130 STM32C562xx Electrical characteristics DT76154V2 Figure 18. HSI frequency versus temperature DS14927 - Rev 1 page 67/130 STM32C562xx Electrical characteristics 5.3.9.2 PSI oscillator characteristics Table 38. PSI oscillator characteristics Symbol Parameter Min(1) Typ Max If reference is HSE - 100 - at 8, 16, 24, 32 or 48 MHz - 144 - - 160(2) - - 100 - - 141.67 - - 158.33(2) - - 100.008 - - 144.015 - - 160.006(2) - Conditions or HSIDIV18 fPSI PSI potential frequency If reference is HSE at 25 or 50 MHz If reference is LSE at 32 KHz DuCy(PSI)(3) Duty Cycle tsu(PSI)(4) IDD(PSI)(3)(5) - NT 850 1750 µs PSI startup time On 8 MHz - 25 45 µs PSI supply regulation bloc oscillator power consumption If HSI not ON - 91 - PSI oscillator power consumption 100 MHz - 95 - PSI oscillator power consumption 144 MHz - 68 - PSI oscillator power consumption 160 MHz - 77 - - 46.8 264 ps - 52.6 276 ps - 54.4 331 ps - 60.6 367 ps - 15.5 - ps - 27 - ps - 14 - ps - 24.5 - ps - 13.5 - ps - 23 - ps - - - - (48 MHz with 32 kHz CK_IN) Next transition jitter(6) On PSIDIV3 Paired transition jitter (7) (48 MHz with 32 kHz CK_IN) On PSIDIV3 (48 MHz with 8 MHz CK_IN) On PSIS (100 MHz) On PSIDIV3 (33.33 MHz) On PSIS Per Period Jitter standard deviation (144 MHz) On PSIDIV3 (48 MHz) On PSIS (160 MHz) On PSIDIV3 (53.33 MHz) On PSIS LT jitter(3) Long term jitter ethernet (100 MHz with 32 kHz CK_IN) On PSIS DS14927 - Rev 1 % - On PSIDIV3 jitter(3) 55 On 32 KHz (48 MHz with 8 MHz CK_IN) PT jitter(3) MHz PSI startup time On PSIDIV3 jitter(3) 45 Unit µA 13.7 (RMS) 96.7 (peak) 0.79 (RMS) ns ns page 68/130 STM32C562xx Electrical characteristics Symbol Parameter Conditions Long term jitter ethernet (100 MHz with 8 MHz CK_IN ) On PSIK LT jitter(3) Long term jitter FDCAN (40 MHz with 32 kHz CK_IN) On PSIK (40 MHz with 8 MHz CK_IN) Min(1) Typ Max Unit 6.69 (peak) - - - - 13.3 (RMS) 83.6 (peak) 0.775 (RMS) 6.16 (peak) ns ns 1. Tested in production. 2. Frequencies above the supported product's maximum frequency can only be used once divided through PSIK or PSIDIV4 dividers. 3. Specified by design - Not tested in production. 4. Evaluated by characterization - Not tested in production. 5. The supply regulation consumption is common to HSI and PSI. (To be counted once if both oscillators are ON) 6. Jitter measurements are performed without clock source activated in parallel. The typical value refer to the standard deviation, while the maximum is the peak measurement of TIE-8 over 36 cycles. 7. Jitter measurements are performed without clock source activated in parallel. The typical value refer to the standard deviation, while the maximum is the peak measurement of TIE-16 over 36 cycles. DS14927 - Rev 1 page 69/130 STM32C562xx Electrical characteristics 5.3.9.3 Low-speed internal (LSI) RC oscillator Table 39. LSI oscillator characteristics Symbol Conditions Min VDD = 3.3 V, TJ = 25°C 31.4(1) TJ = -40 to 130°C 29.4(2) TJ = -40 to 140°C 28.6(2) - 33.6(2) LSI oscillator startup time - - 80 130 tstab(LSI)(3) LSI oscillator stabilization time (5% of final value) - - 120 170 IDD(LSI)(3) LSI oscillator power consumption - - 130 280 fLSI tsu(LSI)(3) Parameter LSI frequency Typ Max 32 32.6(1) Unit 33.6(2) kHz µs nA 1. Guaranteed by test production. 2. Evaluated by characterization - Not tested in production. 3. Specified by design - Not tested in production. 5.3.10 Flash memory characteristics Table 40. Flash memory characteristics Specified by design and not tested in production. Symbol IDD Parameter Conditions Supply current Min Typ Max Word program - 1 - Page erase - 0.8 - Mass erase - 0.8 - Unit mA Table 41. Flash memory programming Symbol Conditions Min(1) Typ Max(1) 128 bits (user area) - 20.0 160.0 16 bits (OTP / EDATA area) - 20.0 160.0 Parameter tprog Word programming time tERASE 8KB Page (8 KB) erase time - - 2.0 2.1 tERASE 2KB Page (2 KB) erase time - - 2.0 2.1 Bank Mass erase time - - 96.0 Mass erase time - - 192.0 200.0 Programming voltage - 2.65 - 3.6 tME Vprog Unit µs ms V 1. Evaluated by characterization - Not tested in production. Table 42. Flash memory user and EDATA endurance and data retention Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) Unit TJ = -40 to 140 °C 10 Kcycle 1 Kcycle at TJ = 125 °C 10 1 Kcycle at TJ = 85 °C 30 10 Kcycle at TJ = 55 °C 30 Year 1. Evaluated by characterization - Not tested in production. DS14927 - Rev 1 page 70/130 STM32C562xx Electrical characteristics 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling two LEDs through the I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs as follows: • • Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below. They are based on the EMS levels and classes defined in application note EMC design guide for STM8, STM32 and Legacy MCUs (AN1709). Table 43. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = 25°C, fHCLK = 144 MHz, LQFP100 package conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = 25°C, fHCLK = 144 MHz, LQFP100 package conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems The EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. Note that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the application. Software recommendations The software flowchart must include the management of runaway conditions such as: • • • Corrupted program counter Unexpected reset Critical data corruption (control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for one second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note Software techniques for improving microcontrollers EMC performance (AN1015) for more details. Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling two LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard that specifies the test board and the pin loading. DS14927 - Rev 1 page 71/130 STM32C562xx Electrical characteristics Table 44. EMI characteristics for fHSE = 16 MHz and fHCLK = 144 MHz Symbol SEMI Parameter Conditions Peak(1) Monitored frequency band Value 0.1 MHz to 30 MHz 16 30 MHz to 130 MHz -1 130 MHz to 1 GHz 21 1 GHz to 2 GHz 13 0.1 MHz to 2 GHz 3.5 VDD = 3.6 V, TA = 25 ° C, LQFP100 package compliant with IEC 61967-2 Level(2) Unit dBμV - 1. Refer to the EMI radiated test section of the application note EMC design guide for STM8, STM32 and Legacy MCUs (AN1709). 2. Refer to the EMI level classification section of the application note EMC design guide for STM8, STM32 and Legacy MCUs (AN1709). 5.3.12 Electrical sensitivity characteristics Based on three different tests (ESD, latch-up) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 45. ESD absolute maximum ratings Specified by design and not tested in production. Symbol Ratings Conditions Packages VESD(HBM) Electrostatic discharge voltage (human body model) TA = 25°C conforming to ANSI/ESDA/JEDEC JS001 All Class Maximum value(1) 2 2000 Unit LQFP 100 LQFP 80 Electrostatic discharge voltage (charge device model) VESD(CDM) TA = 25°C conforming to ANSI/ESDA/JEDEC JS002 V LQFP 64 LQFP 48 C3 1000 LQFP 32 UFQFPN 48 UFQFPN 32 1. Evaluated by characterization - Not tested in production. Static latch-up The following complementary static tests are required on three parts to assess the latch-up performance: • • A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output, and configurable I/O pin. These tests are compliant with EIA/JESD 78E IC latch-up standard. Table 46. Electrical sensitivities DS14927 - Rev 1 Symbol Parameter Conditions Class LU Static latch-up class TA = 130°C conforming to JESD78 Level II A page 72/130 STM32C562xx Electrical characteristics 5.3.13 I/O current injection characteristics As a general rule, the current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V‑capable I/O pins) must be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller if abnormal injection accidentally happens, some susceptibility tests are performed on a sample basis during the device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating-input mode. While this current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out-of-range parameter, such as an ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the 5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in the table below. The negative induced leakage current is caused by the negative injection. The positive induced leakage current is caused by the positive injection. Table 47. I/O current injection susceptibility The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance, TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O. Evaluated by characterization - Not tested in production. Symbol IINJ Description Functional susceptibility Negative injection Positive injection Injected current on PA4 pins 0 0 Injected current on PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PE0, and PE1 pins 0 N/A Injected current on all other pins 5 N/A DS14927 - Rev 1 Unit mA page 73/130 STM32C562xx Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 18. All I/Os are designed as CMOS and TTL-compliant. Note: For information on GPIO configuration, refer to the application note STM32 GPIO configuration for hardware settings and low‑power consumption (AN4899). Table 48. I/O static characteristics The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance, TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O. All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in the figure below. The minimum and maximum values are specified for a junction temperature (TJ) of 125°C. Symbol VIL Parameter I/O input low level voltage I/O input low level voltage Condition Min Typ Max - - 0.3VDD (1) - - 0.4 VDD - 0.1(2) 0.7VDD (1) - - 2.7 V < VDDIOx < 3.6 V 0.52VDD + 0.18(2) - - 2.7 V < VDDIOx < 3.6 V - 300 - 0 < VIN ≤ Max(VDDXXX)(4) - - ±-200 2.7 V 200 mV with 100 mV overdrive only on positive inputs High-speed mode - 50 120 ns Medium mode - 0.5 1.2 µs Comparator offset error Full common mode range - - ±20 mV No hysteresis - 0 - Low hysteresis - 10 - Medium hysteresis - 20 - High hysteresis - 30 - Static - 5 9 With 50 kHz ±100 mV overdrive square signal - 6 - Static - 70 110 With 50 kHz ±100 mV overdrive square signal - 75 - tD(2) Voffset Vhys Comparator hysteresis Medium mode IDDA(COMP) Comparator consumption from VDDA High-speed mode µA µs µs mV µA 1. Refer to Section 5.3.5: Embedded voltage reference. 2. Evaluated by characterization - Not tested in production. 5.3.21 Timer characteristics The parameters given in Section 5.3.21, Table 62, and Section 5.3.21 are specified by design, not tested in production. Refer to Table 48. I/O static characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 61. TIMx characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER tMAX_COUNT Parameter Timer resolution time Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period Maximum possible count with 32‑bit counter Conditions Min Max Unit(1) - 1 - tTIMxCLK 6.9 - ns 0 fTIMxCLK/2 fTIMxCLK = 144 MHz 0 72 TIMx (except TIM2/TIM5) - 16 TIM2/TIM5 - 32 1 65536 tTIMxCLK 0.007 455.1 µs - 4, 294, 967, 296 tTIMxCLK - 29.826 s fTIMxCLK = 144 MHz - fTIMxCLK = 144 MHz fTIMxCLK = 144 MHz MHz bit 1. TIMx, is used as a general term in which x stands for 1, 2, 5, 6, 7, 8, 12, 15, 16, 17. DS14927 - Rev 1 page 88/130 e: STM32C562xx Electrical characteristics Table 62. IWDG min/max timeout period at 32 kHz (LSI) For the values in this table, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full RC period of uncertainty. Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms Table 63. WWDG min/max timeout value at 144 MHz (PCLK) Prescaler WDGTB Min timeout values Max timeout value 1 0 0.0284 1.820 2 1 0.0569 3.641 4 2 0.1138 7.282 8 3 0.2276 14.564 16 4 0.4551 29.127 32 5 0.9102 58.254 64 6 1.820 116.508 128 7 3.641 233.017 5.3.22 Unit ms I3C interface characteristics The I3C interface meets the timing requirements of the MIPI® I3C specification v1.1. The I3C peripheral supports: • • • I3C SDR-only as controller I3C SDR-only as target I3C SCL bus clock frequency up to 12.5 MHz The parameters given in Table 64 below are obtained with the following configuration: • • • Output speed is set to OSPEEDRy[1:0] = 10 I/O Compensation cell activated Voltage scaling range 1 The I3C timings are in line with the MIPI specification, except for the ones given in Table 64, I3C open-drain measured timing. For tSU_OD, this can be mitigated by increasing the corresponding SCL low duration in the I3C_TIMINGR0 register. For further details refer to AN5879. Table 64. Open drain timing measurements Evaluated by characterization - Not tested in production. Symbol Parameter Conditions Min Unit tSU_OD SDA data setup time in open drain mode Controller 2.7 V ≤ VDDIOX ≤ 3.6 V 22(1) ns 1. The minimum SDA data setup time during open-drain-mode is 3 ns, as specified in the MIPI Alliance specification for I3C. DS14927 - Rev 1 page 89/130 STM32C562xx Electrical characteristics 5.3.23 I²C interface characteristics The I²C interface meets the timing requirements of the I2C-bus specification and user manual rev. 03 for: • • • Standard mode (Sm): Bit rate up to 100 kbit/s. Fast mode (Fm): Bit rate up to 400 kbit/s. Fast mode plus (Fm+): Bit rate up to 1 Mbit/s. The I²C timing requirements are specified by design, not tested in production, when the I²C peripheral is properly configured (refer to the product reference manual). The SDA and SCL I/O requirements are met with the following restrictions: • The SDA and SCL I/O pins are not true open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled but remains present. • Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to Section 5.3.14: I/O port characteristics for the I²C I/Os characteristics. Al I²C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics. Table 65. I²C analog filter characteristics Evaluated by characterization - Not tested in production. Measurement points are taken at 50% VDD. Symbol tAF Parameter Min Max Unit Maximum pulse width of spikes that are suppressed by analog filter 50(1) 160(2) ns 1. Spikes with widths below tAF(min) are filtered. 2. Spikes with widths above tAF(max) are not filtered. 5.3.24 USART characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in not found, with the following configuration: • • Output speed set to OSPEEDRy[1:0] = 10 Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level I/O compensation cell activated • Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART). Table 66. USART (SPI mode) characteristics Evaluated by characterization - Not tested in production. Symbol fCK USART clock frequency Conditions Min Typ Max Master transmitter mode, 2.7 V ≤ VDD ≤ 3.6 V - - 18 Slave receiver mode, 2.7 V ≤ VDD ≤ 3.6 V - - 48 Slave transmitter mode, 2.7 V ≤ VDD ≤ 3.6 V - - 27 Unit tsu(NSS) NSS setup time Slave mode tker(1) + 2 - - th(NSS) NSS hold time Slave mode 2 - - CK high and low time Master mode 1/ fCK /2-1 1/ fCK /2 1/ fCK /2+1 Data input setup time Master mode 18 - - tw(CKH) tw(CKL) tsu(RX) DS14927 - Rev 1 Parameter ns page 90/130 STM32C562xx Electrical characteristics Symbol tsu(RX) th(RX) th(RX) Parameter Conditions Data input setup time Data input hold time tv(TX) Data output valid time th(TX) Data output hold time th(TX) Data output hold time Min Typ Max Slave mode 2.5 - - Master mode 0.5 - - Slave mode 1 - - Slave mode 2.7 V ≤ VDD ≤ 3.6 V - 13.5 18 Master mode 2.7 V ≤ VDD ≤ 3.6 V - 2 2.5 Slave mode 9 - - Master mode 0.5 - - Unit ns 1. Tker is the usart_ker_ck_pres clock period. Figure 29. USART timing diagram in SPI master mode 1/fCK CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(CKL) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(RX) th(RX) RX input MSB IN TX output MSB OUT tv(TX) LSB IN BIT6 IN LSB OUT BIT1 OUT DT65386V2 CK output CK output tw(CKH) th(TX) Figure 30. USART timing diagram in SPI slave mode NSS input th(NSS) 1/fCK tsu(NSS) tw(CKH) CK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 tv(TX) tw(CKL) First bit OUT tsu(RX) RX input DS14927 - Rev 1 Next bits OUT Last bit OUT th(RX) First bit IN Next bits IN Last bit IN DT65387V5 TX output th(TX) page 91/130 STM32C562xx Electrical characteristics 5.3.25 SPI characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 18. • • Output speed set to OSPEEDRy[1:0] = 11 Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level I/O compensation cell activated • Refer to Table 48. I/O static characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Evaluated by characterization - Not tested in production. Table 67. SPI characteristics Evaluated by characterization - Not tested in production. Symbol Parameter Conditions Min Typ Master mode fSCK SPI clock frequency NSS setup time th(NSS) NSS hold time tw(SCKH), tw(SCKL) SCK high and low time tsu(MI) Slave receiver mode Data input setup time tsu(SI) th(MI) Slave mode Master mode - - th(SI) 3 - - 1 - - TPLCK - 1 TPLCK TPLCK + 1 DDRS = 1 10-TSCK/2 - - 2 - - DDRS = 0 1 - - DDRS = 1 (TSCK/2)-7 - - Slave mode 1.5 - - Master mode ta(SO) Data output access time Slave mode 12 13.5 15.5 tdis(SO) Data output disable time Slave mode 6.5 8.5 10.5 tv(SO) Data output valid time Slave mode - 12 15.5 Master mode - 2 2.5 Slave mode, 8 - - Master mode 0 - - th(SO) th(MO) DS14927 - Rev 1 Data output hold time MHz 32 2.5 Slave mode Data input hold time 100 DDRS = 0 Master mode Unit 72 Slave mode transmitter/full duplex tsu(NSS) Max ns page 92/130 STM32C562xx Electrical characteristics Figure 31. SPI timing diagram - slave mode and CPHA = 0 NSS input th(NSS) tc(SCK) tsu(NSS) tw(SCKH) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 tv(SO) tw(SCKL) MISO output First bit OUT tsu(SI) MOSI input tdis(SO) th(SO) Next bits OUT Last bit OUT th(SI) First bit IN Next bits IN DT40458V2 ta(SO) Last bit IN Figure 32. SPI timing diagram - slave mode and CPHA = 1 NSS input th(NSS) tc(SCK) tsu(NSS) SCK input CPHA=1 CPOL=0 tw(SCKH) CPHA=1 CPOL=1 tw(SCKL) MISO output Note: DS14927 - Rev 1 th(SO) Next bits OUT First bit OUT tsu(SI) MOSI input tv(SO) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN DT40459V2 ta(SO) Measurement points are done at 0.3 VDD and 0.7 VDD levels. page 93/130 STM32C562xx Electrical characteristics Figure 33. SPI timing diagram - master mode High NSS input tc(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKL) CPHA=1 CPOL=0 CPHA=1 CPOL=1 th(MI) tsu(MI) MISO input MOSI output First bit IN First bit OUT tv(MO) Note: 5.3.26 Next bits IN Next bits OUT th(MO) Last bit IN Last bit OUT DT14136V4 SCK output SCK output tw(SCKH) Measurement points are done at 0.3 VDD and 0.7 VDD levels. I2S interface characteristics Unless otherwise specified, the parameters given in Table xx for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 68. I2S characteristics, with the following configuration: DS14927 - Rev 1 • • • Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5 × VDD • IO Compensation cell activated page 94/130 STM32C562xx Electrical characteristics Refer to Section 5.3.14: I/O port characteristics: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SDO, SDI, WS). Table 68. I2S characteristics Evaluated by characterization – Not tested in production. Symbol fMCK Conditions Min Max Unit - - 50 MHz Master Tx or RX, slave Rx - 50 Slave Tx - 19 I2S main clock output fCK I2S clock frequency tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 1 - tsu(WS) WS setup time Slave mode 2 - th(WS) WS hold time Slave mode 0.5 - tsu(SD_MR) Data input setup time Master receiver 2.5 - tsu(SD_SR) Data input setup time Slave receiver 1 - Master receiver 1.5 - Slave receiver 2.5 - th(SD_MR) th(SD_SR) 5.3.27 Parameter Data input hold time MHz ns tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 15.5 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 8 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) - 2 th(SD_MT) Data output hold time Master transmitter (after enable edge) 0.5 - ns USB_FS characteristics Table 69. USB_FS characteristics Symbol Conditions Min Typ Max Unit USB transceiver operating supply voltage - 3.0(1) - 3.6 V RPUI Embedded USB_DP pullup value during idle - 900 - 1575 RPUR Embedded USB_DP pullup value during reception - 1425 - 3090 28 36 44 VDDUSB ZDRV Parameter Output driver impedance(2) High and low driver Ω 1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range. 2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is already included in the embedded driver. 5.3.28 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 70 and Table 71 are derived from tests performed under the ambient temperature, fHCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: • • Output speed set to OSPEEDRy[1:0] = 10 Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level Refer to Table 48. I/O static characteristics for more details on the input/output characteristics. DS14927 - Rev 1 page 95/130 STM32C562xx Electrical characteristics Table 70. JTAG characteristics Evaluated by characterization - Not tested in production. Symbol Parameter Min Typ Max Unit MHz FTCK TCK clock frequency - - 34 tisu(TMS) TMS input setup time 2 - - tih(TMS) TMS input hold time 0.5 - - tisu(TDI) TDI input setup time 1.5 - - tih(TDI) TDI input hold time 0.5 - - tov(TDO) TDO output valid time - 11 14.5 toh(TDO) TDO output hold time 7.5 - - ns Figure 34. JTAG timing diagram NSS input th(NSS) tc(SCK) tsu(NSS) tw(SCKH) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 First bit OUT tsu(SI) tdis(SO) th(SO) Next bits OUT Last bit OUT th(SI) First bit IN Next bits IN DT40458V2 MISO output MOSI input tv(SO) tw(SCKL) ta(SO) Last bit IN Table 71. SWD characteristics Evaluated by characterization - Not tested in production. Symbol Parameter Min Typ Max Unit MHz FSWCLK SWCLK clock frequency - - 71 tisu(SWDIO) SWDIO input setup time 3 - - tih(SWDIO) SWDIO input hold time 0.5 - - tov(SWDIO) SWDIO output valid time - 11.5 14 toh(SWDIO) SWDIO output hold time 9.5 - - DS14927 - Rev 1 ns page 96/130 STM32C562xx Electrical characteristics Figure 35. SWD timing diagram NSS input th(NSS) tc(SCK) tsu(NSS) SCK input CPHA=1 CPOL=0 tw(SCKH) CPHA=1 CPOL=1 tw(SCKL) MISO output First bit OUT tsu(SI) MOSI input DS14927 - Rev 1 tv(SO) th(SO) Next bits OUT tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN DT40459V2 ta(SO) page 97/130 STM32C562xx Package information 6 Package information To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 Device marking Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors" (TN1433) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1. Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection. DS14927 - Rev 1 page 98/130 STM32C562xx Package information 6.2 LQFP32 package information (5V) This LQFP is a 32-pin, 7 x 7 mm, low-profile quad flat package. Note: Figure 36 is not to scale. Refer to the notes section for the list of notes on Figure 36 and Table 72. Figure 36. LQFP32- Outline BOTTOM VIEW 2 1 (2) (6) D 1/4 R1 R2 TI O N B- B H SE C E 1/4 B S bbb H A-B D 4x aaa C A-B D N 3 GAUGE PLANE 0.25 4x N/4 TIPS B L (L1) (1) (11) SECTION A-A (N – 4)x e (13) C A A1 b (12) 0.05 ddd C A-B D D (2) (5) ccc C (4) b D1 (11) c 1 A E 1/4 2 E1 (6) (3) A (Section A-A) DS14927 - Rev 1 c1(11) B 3 D 1/4 TOP VIEW WITH PLATING D (3) (10) (3) (9) (11) A (2) (5) E (4) b1 (11) SECTION B-B BASE METAL 5V_LQFP32_ME_V1 A2 page 99/130 STM32C562xx Package information Table 72. LQFP32 - Mechanical data Symbol Inches(14.) Millimeters Min Typ Max Min Typ Max θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° A - - 1.60 - - 0.0630 A1(12.) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b(9.)(11.) 0.30 0.37 0.45 0.0118 0.0146 0.0177 b1(11.) 0.30 0.35 0.40 0.0118 0.0128 0.0157 c(11.) 0.09 - 0.20 0.0035 - 0.0079 c1(11.) 0.09 - 0.16 0.0035 - 0.0063 D(4.) 9.00 BSC 0.3543 BSC D1(2.)(5.) 7.00 BSC 0.2756 BSC e 0.80 BSC 0.0315 BSC E(4.) 9.00 BSC 0.3543 BSC E1(2.)(5.) 7.00 BSC 0.2756 BSC L 0.45 L1 0.60 0.75 1.00 REF 0.0236 0.0295 0.0394 REF N(13.) DS14927 - Rev 1 0.0177 32 R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1.)(7.)(15.) 0.20 0.0079 bbb(1.)(7.)(15.) 0.20 0.0079 ccc(1.)(7.)(15.) 0.10 0.0039 ddd(1.)(7.)(15.) 0.20 0.0079 page 100/130 STM32C562xx Package information Notes: 1. 2. 3. 4. 5. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. Datums A-B and D to be determined at datum plane H. To be determined at the seating datum plane C. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeters. 8. No intrusion is allowed inwards the leads. 9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. The exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. N is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to four decimal digits. 15. Recommended values and tolerances. Figure 37. LQFP32 - Footprint example 0.45 0.8 32 25 24 8 17 7.4 1 9 9.8 1.2 REF 16 9.8 Soldering area Solder resist opening 5V_LQFP32_FP_V4 7.4 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 101/130 STM32C562xx Package information 6.3 UFQFPN32 package information (A0B8) This UFQFPN is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra-thin fine pitch quad flat package. Figure 38. UFQFPN32 - Outline D2 fff C A B EXPOSED PAD b fff bbb ddd C A B C A B C E2 e PIN 1 identifier Chamfer or Circular arc shape L e BOTTOM VIEW R0.20 A ccc C eee C A3 A1 SEATING PLANE C DETAIL A FRONT VIEW A3 SEATING PLANE A1 ddd C C B PIN 1 IDENTIFIER LASER MARKING AREA DETAIL A D TOP VIEW A A0B8_UFQFPN32_ME_V4 E 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. DS14927 - Rev 1 page 102/130 STM32C562xx Package information Table 73. UFQFPN32 - Mechanical data Symbol Millimeters(1) Inches(2) Min Typ Max Min Typ Max A(3)(4) 0.50 0.55 0.60 0.0197 0.0217 0.0236 A1(5) 0.00 - 0.05 0.000 - 0.0020 A3(6) - 0.15 - - 0.0060 - b(7) 0.18 0.25 0.30 0.0071 0.010 0.0118 D(8)(9) D2 5.00 BSC 3.50 E(8)(9) 3.60 0.1969 BSC 3.70 0.139 0.143 5.00 BSC 0.147 0.1969 BSC E2 3.50 3.60 3.70 0.139 0.143 0.147 e(9) - 0.50 - - 0.02 - N(10) 32 K 0.15 - - 0.006 - - L 0.30 - 0.50 0.0119 - 0.0199 R 0.09 - - 0.004 - - 1. All dimensions are in millimeters. Dimensioning and tolerancing schemes are conform to ASME Y14.5M-2018 except European . 2. Values in inches are converted from mm and rounded to 4 decimal digits. 3. UFQFPN stands for Ultra thin Fine pitch Quad Flat Package No lead: A ≤ 0.60mm / Fine pitch e ≤ 1.00mm. 4. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured perpendicular to the seating plane. 5. A1 is the vertical distance from the bottom surface of the plastic body to the nearest metallized package feature. 6. A3 is the distance from the seating plane to the upper surface of the terminals. 7. Dimension b applies to metallized terminal. If the terminal has the optional radius on the other end of the terminal, the dimension b must not be measured in that radius area. 8. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm. 9. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to Table 74 10. N represents the total number of terminals. Table 74. Tolerance of form and position Tolerance of form and position(2) Tolerance of form and position(3) In millimeters In inches aaa 0.15 0.006 bbb 0.10 0.004 ccc 0.10 0.004 ddd 0.05 0.002 eee 0.10 0.004 fff 0.10 0.004 Symbol(1) 1. For the tolerance of form and position definitions see Table 75. 2. All dimensions are in millimetres. Dimensioning and tolerancing schemes are conform to ASME Y14.5M-2018 except European . 3. Values in inches are converted from mm and rounded to 4 decimal digits. DS14927 - Rev 1 page 103/130 STM32C562xx Package information Table 75. Tolerance of form and position symbol definition Symbol Definition aaa The bilateral profile tolerance that controls the position of the plastic body sides. The centres of the profile zones are defined by the basic dimensions D and E. bbb The tolerance that controls the position of the terminals with respect to Datums A and B. The centre of the tolerance zone for each terminal is defined by basic dimension e as related to datums A and B. ccc The tolerance located parallel to the seating plane in which the top surface of the package must be located. ddd The tolerance that controls the position of the terminals to each other. The centres of the profile zones are defined by basic dimension e. eee The unilateral tolerance located above the seating plane wherein the bottom surface of all terminals must be located = coplanarity fff The tolerance that controls the position of the exposed metal heat feature. The centre of the tolerance zone is the data defined by the centrelines of the package body Figure 39. UFQFPN32 - Footprint example 5.50 3.75 0.65 3.60 3.60 0.50 0.25 3.75 A0B8_FP_V2 A0B8_UFQFPN32_FP_V1 3.75 5.50 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 104/130 STM32C562xx Package information 6.4 LQFP48 package information (5B) This LQFP is a 48-pins, 7 x 7 mm, low-profile quad flat package. Note: See list of notes in the notes section. Figure 40. LQFP48- Outline(15.) BOTTOM VIEW Package LQFP48 (package code 5B) 4x N/4 TIPS aaa C A-B D 2 1 (2) R1 R2 O N C TI (6) SE D 1/4 BB H B S B bbb H A-B D 4x 3 0.05 A (13) (N – 4)x e A2 A1 (12) C ddd b (10) (3) A (L1) (1) (11) SECTION A-A (4) D1 D (3) N 1 2 3 L ccc C C A-B D D (2) (5) GAUGE PLANE 0.25 E 1/4 b (9) (11) WITH PLATING E 1/4 D 1/4 B (3) (6) c E1 (2) (5) A (Section A-A) A E c1 (11) (11) (4) b1 (11) BASE METAL SECTION B-B TOP VIEW DS14927 - Rev 1 page 105/130 STM32C562xx Package information Table 76. LQFP48 - Mechanical data Symbol inches(14.) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1(12.) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106 b1(11.) 0.17 0.20 0.23 0.0067 0.0079 0.0090 c(11.) 0.09 - 0.20 0.0035 - 0.0079 c1(11.) 0.09 - 0.16 0.0035 - 0.0063 D(4.) 9.00 BSC 0.3543 BSC D1(4.)(5.) 7.00 BSC 0.2756 BSC E(4.) 9.00 BSC 0.3543 BSC E1(4.)(5.) 7.00 BSC 0.2756 BSC e 0.50 BSC 0.1970 BSC L 0.45 L1 0.60 0.75 0.0177 1.00 REF 0.0236 0.0295 0.0394 REF N(13.) 48 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 10° 12° 14° 10° 12° 14° θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1.)(7.) 0.20 0.0079 bbb(1.)(7.) 0.20 0.0079 ccc(1.)(7.) 0.08 0.0031 ddd(1.)(7.) 0.08 0.0031 Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All Dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. DS14927 - Rev 1 page 106/130 STM32C562xx Package information 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits 15. Drawing is not to scale. Figure 41. LQFP48 - Footprint example 0.50 1.20 36 25 37 24 0.30 0.20 9.70 7.30 48 13 12 1 5.80 9.70 5B_LQFP48_FP_V1 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 107/130 STM32C562xx Package information 6.5 UFQFPN48 package information (A0B9) This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package. Figure 42. UFQFPN48 - Outline D2 K fff fff M CAB DETAIL C M CAB ddd M C 2xR 14 E2 e 15 C (see FIG.2) fff Terminal 1 idenfier M CAB e BOTTOM VIEW ccc C A3 A SEATING PLANE eee C C FRONT VIEW D A SECTION A-A B A1 Terminal 1 Index area Seating plane 10 C 9 A (see FIG.2) A aaa C x4 TOP VIEW DT_A0B9_UFQFPN48_ME_V4 E 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the under side of the UFQFPN48 package. It is recommended to connect and solder this back-side pad to PCB ground. DS14927 - Rev 1 page 108/130 STM32C562xx Package information Table 77. UFQFPN48 - Mechanical data Symbol Inches (1) Millimeters Min Typ Max Min Typ Max A 0.50 0.55 0.60 0.0197 0.0217 0.0236 A1 0.00 - 0.05 0.0000 - 0.0020 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 D(2) D2(3) 7.00 BSC 5.50 E(2) E2(3) 0.2756 BSC 5.60 5.70 0.2165 0.2205 7.00 BSC 5.50 e 0.2244 0.2756 BSC 5.60 5.70 0.2165 0.2205 0.50 BSC 0.2244 0.0197 BSC N 48 L 0.30 - 0.50 0.0118 - 0.0197 R 0.10 - - 0.0039 - - aaa 0.15 0.0059 bbb 0.10 0.0039 ccc 0.10 0.0039 ddd 0.05 0.0020 eee 0.08 0.0031 fff 0.10 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm. 3. Dimensions D2 and E2 are not in accordance with JEDEC. Figure 43. UFQFPN48 - Footprint example 7.30 6.20 48 37 1 36 5.80 6.20 5.60 0.30 12 25 13 0.55 24 0.50 5.80 0.75 DT_A0B9_UFQFPN48_FP_V3 5.60 0.20 7.30 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 109/130 STM32C562xx Package information 6.6 LQFP64 package information (5W) This is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 44. LQFP64 - Outline(15.) BOTTOM VIEW 2 1 (2) R1 R2 SE C TI O N B- B H (6) S E 1/4 4x N/4 TIPS aaa C A-B D 3 GAUGE PLANE 0.25 B D 1/4 B L (L1) (1) (11) bbb H A-B D 4x SECTION A-A (13) (N – 4)x e C A A2 A1 (12) b ddd C A-B D ccc C D (10) (9) (11) D (3) N (11) c D 1/4 B (3) (6) A (Section A-A) DS14927 - Rev 1 WITH PLATING (11) A c1 (5) (2) E1 TOP VIEW b (4) E 1/4 1 2 3 (3) A (4) D1 (5) (2) E b1 (11) BASE METAL SECTION B-B 5W_LQFP64_ME_V1 0.05 page 110/130 STM32C562xx Package information Table 78. LQFP64 - Mechanical data Symbol inches(14.) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1(12.) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106 b1(11.) 0.17 0.20 0.23 00067 0.0079 0.0091 c(11.) 0.09 - 0.20 0.0035 - 0.0079 c1(11.) 0.09 - 0.16 0.0035 - 0.0063 D(4.) 12.00 BSC 0.4724 BSC D1(2.)(5.) 10.00 BSC 0.3937 BSC E(4.) 12.00 BSC 0.4724 BSC E1(2.)(5.) 10.00 BSC 0.3937 BSC e 0.50 BSC 0.0197 BSC L 0.45 L1 0.60 0.75 1.00 REF 0.0236 0.0295 0.0394 REF N(13.) DS14927 - Rev 1 0.0177 64 Θ 0° 3.5° 7° 0° 3.5° 7° Θ1 0° - - 0° - - Θ2 10° 12° 14° 10° 12° 14° Θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1.) 0.20 0.0079 bbb(1.) 0.20 0.0079 ccc(1.) 0.08 0.0031 ddd(1.) 0.08 0.0031 page 111/130 STM32C562xx Package information Notes 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. N is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. DS14927 - Rev 1 page 112/130 STM32C562xx Package information 6.7 LQFP80 package information (9X) This is a 80-pins, 12 x 12 mm, low-profile quad flat package. Note: See list of notes in the notes section. Figure 45. LQFP80 - Outline(15.) BOTTOM VIEW 2 1 (2) R1 SE C TI O N B- B R2 H D 1/4 S (6) (L1) E 1/4 bbb H A-B D 4x e (13) C A A2 A1(12) b ddd C A-B D D (2) (5) (9) (11) WITH PLATING (4) D (3) (11) N (4) E 1/4 D 1/4 (11) c c1 b1 (3) B (6) (2) (5) A (Section A-A) A (11) BASE METAL SECTION B-B E1 TOP VIEW b E 9X_LQFP80_ME_V2 e 1 2 3 (3) A ccc C D1 (10) DS14927 - Rev 1 (1) (11) SECTION A-A 4x N/4 TIPS aaa C A-B D 0.05 B L 3 (N – 4)x GAUGE PLANE 0.25 B page 113/130 STM32C562xx Package information Table 79. LQFP80 - Mechanical data Symbol inches(14.) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1(12.) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106 b1(11.) 0.17 0.20 0.23 00067 0.0079 0.0091 c(11.) 0.09 - 0.20 0.0035 - 0.0079 c1(11.) 0.09 - 0.16 0.0035 - 0.0063 D(4.) 14.00 BSC 0.5512 BSC D1(2.)(5.) 12.00 BSC 0.4724 BSC E(4.) 14.00 BSC 0.5512 BSC E1(2.)(5.) 12.00 BSC 0.4724 BSC e 0.50 BSC 0.0197 BSC L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - N(13.) DS14927 - Rev 1 80 Θ 0° 3.5° 7° 0° 3.5° 7° Θ1 0° - - 0° - - Θ2 10° 12° 14° 10° 12° 14° Θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1.) 0.20 0.0079 bbb(1.) 0.20 0.0079 ccc(1.) 0.08 0.0031 ddd(1.) 0.08 0.0031 page 114/130 STM32C562xx Package information Notes 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeters. 8. No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. Figure 46. LQFP80 - Footprint example 1.25 0.3 1.2 9.80 14.70 9X_LQFP80_FP_V1 12.30 14.70 0.5 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 115/130 STM32C562xx Package information 6.8 LQFP100 package information (1L) This LQFP is a 100-pin, 14 x 14 mm, low-profile quad flat package. Note: See list of notes in the notes section. Figure 47. LQFP100 - Outline(15.) Package LQFP100 (Package code 1L) θ1 θ2 (2) R1 R2 O N B- B H SE C TI (6) D1/4 B S E1/4 L 4x aaa C A-B D (L1) bbb H A-B D (1) (11) SECTION A-A BOTTOM VIEW (N-4) x e (13) C A 0.05 θ B θ3 4x N/4 TIPS GAUGE PLANE (9) (11) b A2 A1 (12) aaa b ccc C C A-BD WITH PLATING SIDE VIEW D D1 (2) (5) (4) (11) D (3) (10) c c1 (4) N b1 (11) 1 2 3 E1/4 D1/4 A (11) BASE METAL SECTION B-B (6) B (2) (5) E1 E SECTION A-A TOP VIEW DS14927 - Rev 1 A 1L_LQFP100_ME_DT_V5 A page 116/130 STM32C562xx Package information Table 80. LQFP100 - Mechanical data Symbol inches(14.) millimeters Min Typ Max Min Typ Max A - 1.50 1.60 - 0.0590 0.0630 A1(12.) 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106 b1(11.) 0.17 0.20 0.23 0.0067 0.0079 0.0090 c(11.) 0.09 - 0.20 0.0035 - 0.0079 c1(11.) 0.09 - 0.16 0.0035 - 0.0063 D(4.) 16.00 BSC 0.6299 BSC D1(2.)(5.) 14.00 BSC 0.5512 BSC E(4.) 16.00 BSC 0.6299 BSC E1(2.)(5.) 14.00 BSC 0.5512 BSC e 0.50 BSC 0.0197 BSC L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1(1.)(11.) - 1.00 - - 0.0394 - 3.5° 7° N(13.) Θ DS14927 - Rev 1 100 0° 3.5° 7° 0° Θ1 0° - - 0° - - Θ2 10° 12° 14° 10° 12° 14° Θ3 10° 12° 14° 10° 12° 14° R1 0.08 - - 0.0031 - - R2 0.08 - 0.20 0.0031 - 0.0079 S 0.20 - - 0.0079 - - aaa(1.) 0.20 0.0079 bbb(1.) 0.20 0.0079 ccc(1.) 0.08 0.0031 ddd(1.) 0.08 0.0031 page 117/130 STM32C562xx Package information Notes 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Datums A-B and D to be determined at datum plane H. 4. To be determined at seating datum plane C. 5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. 7. All dimensions are in millimeters. 8. No intrusion is allowed inwards the leads. 9. Dimension “b” does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. The exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. “N” is the number of terminal positions for the specified body size. 14. Values in inches are converted from mm and rounded to 4 decimal digits. 15. Drawing is not to scale. Figure 48. LQFP100 - Footprint example 75 76 51 50 0.5 0.3 14.3 100 26 1 25 12.3 16.7 1L_LQFP100_FP_DT_V1 16.7 1. Dimensions are expressed in millimeters. DS14927 - Rev 1 page 118/130 STM32C562xx Package information 6.9 Package thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following equation: T J max = TA max + PD max × Θ JA Where: • TA max is the maximum ambient temperature in °C. • ΘJA is the package junction-to-ambient thermal resistance in °C/W. • PD max is the sum of PINT max and PI/O max: PD max = PINT max + PI/O max • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins: PI/O max = VOL × IOL + VDDIOx − VOH × IOH taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 81. Package thermal characteristics Symbol Θ 6.9.1 Thermal Resistance Parameter Value Junction-ambient ΘJA Junction-board ΘJB Junction-case ΘJC LQFP100 39.2 25.1 11.4 LQFP80 42.8 27.1 13.1 LQFP64 44.3 26.6 13.5 LQFP48 51.4 28.7 16.1 LQFP32 51.4 28.7 16.1 UFQFPN48 29.9 14.2 12 UFQFPN32 40.4 22.3 20.5 Unit °C/W Reference documents • • DS14927 - Rev 1 Definition JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) available on www.jedec.org. For information on thermal management, refer to application note "Guidelines for thermal management on STM32 applications" (AN5036) available on www.st.com. page 119/130 STM32C562xx Ordering information 7 Ordering information Example: STM32 C 562 K E T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type C = General purpose Device subfamily 562 = STM32C562xx with FDCAN Pin count K = 32 pins C = 48 pins R = 64 pins M = 80 pins V = 100 pins Flash memory size E = 512 Kbytes Package U = UFQFPN T = LQFP Temperature range 6 = Temperature range, -40 to +85 °C (+105 °C junction) 3 = Temperature range, -40 to +125 °C (+140 °C junction) Packing TR = Tape and reel xxx = Programmed parts Note: DS14927 - Rev 1 For a list of available options (such as speed and package) or for further information on any aspect of this device, contact your nearest ST sales office. page 120/130 STM32C562xx Ordering information Important security notice The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: • • • • • DS14927 - Rev 1 ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. page 121/130 STM32C562xx Revision history Table 82. Document revision history DS14927 - Rev 1 Date Revision 18-Feb-2026 1 Changes Initial release. page 122/130 STM32C562xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Arm® Cortex®-M33 with FPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Instruction cache (ICACHE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.2 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.3 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.4 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.10 General-purpose inputs/outputs (GPIOs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.11 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.12 Low-power direct memory access controller (LPDMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.13.1 Nested vectored interrupt controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.13.2 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.14 Cyclic redundancy check calculation unit (CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.15 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.15.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.17 Low-power comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.18 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.19 AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.20 HASH processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.21.1 DS14927 - Rev 1 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 page 123/130 STM32C562xx Contents 3.22 4 5 3.21.2 General-purpose timers (TIM2/TIM5/TIM12/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . 22 3.21.3 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.21.4 Low-power timers (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.21.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.21.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.21.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.22.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.22.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.24 Improved inter-integrated circuit interface (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.25 Universal synchronous/asynchronous receiver transmitter (USART/UART) and lowpower universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . 29 3.25.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . . . . . . . 29 3.25.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . 30 3.26 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . . . . . . . . . . . . . . . . 31 3.27 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.28 Universal serial bus full-speed host/device interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.29 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.29.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.29.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pinouts/ballouts, pin description, and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . .35 4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DS14927 - Rev 1 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 page 124/130 STM32C562xx Contents 6 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.4 Inrush current and inrush electric charge characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.7 Wake-up time from low-power modes and voltage scaling transition times . . . . . . . . . . . . 61 5.3.8 External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.9 Internal clock timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.15 NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . . . . . . . . . . . . . . . . 79 5.3.17 12-bit analog-to-digital converter ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.18 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.19 Digital-to-analog converter characteristics (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.22 I3C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.23 I²C interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.24 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.25 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.26 I2S interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.27 USB_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.28 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.2 LQFP32 package information (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3 UFQFPN32 package information (A0B8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.4 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.5 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.6 LQFP64 package information (5W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.7 LQFP80 package information (9X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.8 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.9.1 DS14927 - Rev 1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 page 125/130 STM32C562xx Contents 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DS14927 - Rev 1 page 126/130 STM32C562xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . LPDMA2 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . LPDMA1 and LPDMA2 autonomous mode and wake-up in low-power modes ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AES features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 13 14 14 17 19 21 25 Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. I3C peripheral controller/target features versus MIPI® v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . USART, UART, and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32C562xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating conditions at power-up/power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical and maximum current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical current consumption in Run mode with CoreMark running from flash memory and SRAM . Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical and maximum HSIKERON current consumption in Stop mode . . . . . . . . . . . . . . . . . . . Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral current consumption measured in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LSE oscillator characteristics (fLSE = 32.768 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSI144 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash memory user and EDATA endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMI characteristics for fHSE = 16 MHz and fHCLK = 144 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage characteristics (all I/Os except PC14 and PC15). . . . . . . . . . . . . . . . . . . . . . . . Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output AC characteristics (all I/Os except PC13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 31 39 40 48 53 53 54 54 55 55 55 56 56 57 57 57 58 58 58 59 61 61 61 63 64 65 66 68 70 70 70 70 71 72 72 72 73 74 76 76 77 78 DS14927 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 127/130 STM32C562xx List of tables Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. EXTI input characteristics . . . . . . . . . . . . . . . . . . 12-bit ADC characteristics. . . . . . . . . . . . . . . . . . 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . Temperature sensor characteristics . . . . . . . . . . . Temperature sensor calibration values . . . . . . . . . DAC characteristics . . . . . . . . . . . . . . . . . . . . . . DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . COMP characteristics. . . . . . . . . . . . . . . . . . . . . TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . IWDG min/max timeout period at 32 kHz (LSI) . . . . WWDG min/max timeout value at 144 MHz (PCLK) Open drain timing measurements. . . . . . . . . . . . . I²C analog filter characteristics. . . . . . . . . . . . . . . USART (SPI mode) characteristics. . . . . . . . . . . . SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . USB_FS characteristics . . . . . . . . . . . . . . . . . . . JTAG characteristics . . . . . . . . . . . . . . . . . . . . . SWD characteristics . . . . . . . . . . . . . . . . . . . . . . LQFP32 - Mechanical data . . . . . . . . . . . . . . . . . UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . Tolerance of form and position . . . . . . . . . . . . . . . Tolerance of form and position symbol definition . . LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . LQFP80 - Mechanical data . . . . . . . . . . . . . . . . . LQFP100 - Mechanical data . . . . . . . . . . . . . . . . Package thermal characteristics. . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . DS14927 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . 79 . 80 . 84 . 84 . 84 . 87 . 87 . 88 . 89 . 89 . 89 . 90 . 90 . 92 . 95 . 95 . 96 . 96 100 103 103 104 106 109 .111 .114 .117 .119 122 page 128/130 STM32C562xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. STM32C562xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32C562xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32C562xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC timing diagram for high-speed external clock source (digital mode) . . . . . . . . . . . . . . . . . . . AC timing diagram for high-speed external clock source (analog mode) . . . . . . . . . . . . . . . . . . . Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSI frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O input characteristics (all I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum sampling time versus RAIN for 12 bits resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum sampling time versus RAIN for 10 bits resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum sampling time versus RAIN for 8 bits resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum sampling time versus RAIN for 6 bits resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function 12-bit buffered/non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART timing diagram in SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP32- Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 . 10 . 35 . 35 . 36 . 36 . 37 . 37 . 38 . 51 . 51 . 52 . 62 . 62 . 63 . 64 . 65 . 67 . 75 . 78 . 78 . 81 . 81 . 82 . 82 . 83 . 83 . 86 . 91 . 91 . 93 . 93 . 94 . 96 . 97 . 99 101 102 104 Figure 40. Figure 41. Figure 42. Figure 43. LQFP48- Outline(15.) . . . . . . . . LQFP48 - Footprint example . . UFQFPN48 - Outline . . . . . . . . UFQFPN48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 107 108 109 Figure 44. LQFP64 - Outline(15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Figure 45. Figure 46. LQFP80 - Outline(15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 LQFP80 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Figure 47. Figure 48. LQFP100 - Outline(15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 LQFP100 - Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 DS14927 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 129/130 STM32C562xx IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. In the event of any conflict between the provisions of this document and the provisions of any contractual arrangement in force between the purchasers and ST, the provisions of such contractual arrangement shall prevail. The purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. The purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of the purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 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